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Bit cell applied to in-memory computation and memory computation array device

A bit unit and storage unit technology, applied in the field of in-memory computing, can solve the problems of high power consumption and large area of ​​the six-tube structure, and achieve the effects of reducing power consumption, simplifying structure, and improving calculation accuracy

Active Publication Date: 2020-12-04
中科南京智能技术研究院
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The six-tube structure has a larger area and greater power consumption

Method used

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  • Bit cell applied to in-memory computation and memory computation array device
  • Bit cell applied to in-memory computation and memory computation array device
  • Bit cell applied to in-memory computation and memory computation array device

Examples

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Embodiment 1

[0060] Such as figure 1 As shown, the present invention provides a bit unit applied to in-memory calculation, the bit unit includes: a four-pipe storage unit and a peripheral storage operation for accumulating and adding the activation signal and the weight output by the four-pipe storage unit circuit; the weight output end of the four-tube storage unit is connected to the weight input end of the four-tube storage unit, and the inverse weight output end of the four-tube storage unit is connected to the inverse weight of the four-tube storage unit The input terminal is connected; the word line control terminal (the control terminal of the transistor T3 and the transistor T4) of the four-tube memory unit is connected to the word line WL, and the bit line control terminal (the input terminal of the transistor T3) of the four-tube memory unit is connected to the The bit line BL is connected, and the reverse bit line control terminal (input terminal of transistor T4) of the four-tu...

Embodiment 2

[0070] The present invention also provides a storage and calculation array device, and the storage and calculation array device includes:

[0071] Storage array module ①, column decoding module ②, row decoding module ③, input activation drive module ④ and analog-to-digital conversion output module ⑤; the storage array module includes A bit unit applied to memory calculation; n bit line output terminals of the column decoding module are respectively connected to n bit lines, and n reverse bit line output terminals of the column decoding module are respectively connected to n reverse bit lines; The m word line output terminals of the row decoding module are respectively connected to the m word lines; the m first activation signal output terminals of the memory array module are respectively connected to the m first activation signal lines; The deactivation signal output terminals are respectively connected to the m first deactivation signal lines; the m second activation signal ...

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Abstract

The invention provides a bit cell applied to in-memory computation. The bit unit comprises a four-tube storage unit and a peripheral storage circuit; wherein the weight output end of the four-tube storage unit is connected with the weight input end of the four-tube storage unit, and the anti-weight output end of the four-tube storage unit is connected with the anti-weight input end of the four-tube storage unit. The four-tube storage unit is arranged and replaces a six-tube storage unit to be applied to the storage array module, the structure of the storage array device is simplified, the peripheral storage circuit is used for carrying out accumulative addition operation, binary neural network accumulative operation is completed through analog mixed signal capacitive coupling calculation,input activation of five values is achieved, and the computational accuracy is improved; in addition, no quiescent current exists in the calculation process, so that the power consumption is reduced,and a capacitance coupling mechanism has better stability. Therefore, the storage and calculation array structure is simplified, the power consumption is reduced, and the storage and calculation efficiency and precision are improved.

Description

technical field [0001] The invention relates to the technical field of in-memory computing, in particular to a bit unit and a memory-computing array device applied to in-memory computing. Background technique [0002] Deep Convolutional Neural Networks (DCNNs) continue to demonstrate improvements in inference accuracy, and deep learning is moving to edge computing. This development has spurred work on low-resource machine learning algorithms and hardware to accelerate them. The most common operation in DCNNs is multiply and accumulate (Multiply Accumulate, MAC), which controls power and delay. MAC operations have high regularity and parallelism, so they are very suitable for hardware acceleration. However, the amount of memory access severely limits the energy efficiency of conventional digital accelerators. [0003] The current storage and calculation arrays are basically based on six or more tube storage units. MAC operations are divided into current domain calculations...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063
CPCG06N3/063
Inventor 乔树山黄茂森尚德龙周玉梅
Owner 中科南京智能技术研究院
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