Double-word-line 6TSRAM unit circuit for binary neural network

Abstract

The invention discloses a double-word-line 6TSRAM unit circuit for a binary neural network, and the circuit is characterized in that PMOS transistors M1 and M2 are pre-charging tubes, the source electrodes of M1 and M2 are connected to a power supply Vdd, the drain electrode of M1 is connected to a bit line BLB, and the drain electrode of M2 is connected to a bit line BL; grid electrodes of the M1and the M2 are jointly connected to a control end sw2; the PMOS transistor M3 is a balance voltage tube shared by a column of 6TSRAM unit arrays, and a source electrode and a drain electrode of the PMOS transistor M3 are respectively connected with bit lines BLB and BL and are used for balancing voltages on the two bit lines BL and BLB; the grid electrode of the M3 is connected to the control endsw1; and the capacitors C0 and C1 are parasitic capacitors on the bit lines BLB and BL. According to the circuit structure, the area and the power consumption are reduced, the linearity is improved,meanwhile, the operation of an analog domain and the operation of a digital domain are combined, and the calculation amount of the analog domain and the complexity of the circuit are reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a double-word-line 6TSRAM unit circuit for binary neural networks (BinaryNeural Networks). Background technique [0002] At present, deep learning is attracting more and more attention in academia and industry. Deep Neural Networks (DeepNeural Networks) is a model commonly used in artificial intelligence scenarios to achieve high-precision recognition and prediction functions. However, in the current Feng -Under the Neumann computing architecture, the data is stored in the memory, and then the data is transmitted from the storage array to the ALU computing unit during calculation. In this case, the time consumed in data transmission is much higher than the time of data calculation, so Data transmission efficiency has also become an important factor limiting the development of deep learning. The emergence of CIM (Computing-In-Memory), which embeds logical operat...

AI Technical Summary

Problems solved by technology

In the prior art, an 8TSRAM cell array is generally used to implement a binary neural network, most of which are binary neural networks that input Neuron (+1 / -1) and weight (+1 / -1), but the circuit of this implementation is complicated , The amount of calculation is large, which increases the area and power consumption, which restricts the development of deep learning

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