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Method and device for matched filtering in combined detection

A technology of matched filtering and joint detection, applied in the field of matched filtering, which can solve problems such as inability to meet system requirements, multiple hardware resources, consumption, etc.

Active Publication Date: 2009-09-09
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional implementation based on DSP software technology has a large amount of calculation and consumes more hardware resources, which can no longer meet the requirements of the system.

Method used

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  • Method and device for matched filtering in combined detection
  • Method and device for matched filtering in combined detection
  • Method and device for matched filtering in combined detection

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Embodiment Construction

[0061] In the process of performing matrix operations by the matched filter module, as shown in formula 1, the matched filter module calculates the or It is necessary to do 32*8 times of 16-bit complex multiplication and add up the multiplications. The amount of calculation is very large. In order to speed up, the method of parallel processing with 8 antennas can be used. Configuring the DSP48 in MAC (multiply-accumulate) mode can facilitate the calculation of the multiplication and accumulation of individual antennas. The accumulation and addition of 8 antennas can be realized by using the addition tree or the cascaded addition of DSP48. Using the addition tree will consume a lot of resources and The highest frequency of the circuit is limited, so in the present invention, cascaded DSP48 is used to realize 8-antenna accumulation, reduce the amount of matrix calculation, and provide a hardware implementation method for matched filtering, at the cost of calculating each symbo...

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Abstract

The invention discloses a method and a device for matched filtering in combined detection. When a matched filtering device calculates matched filtering data of each symbol of each virtual spread spectrum unit, a complex operation between matched filtering matrix data and antenna data is decomposed into four real operations on four groups of operation subunits in parallel, and the operation subunit number in each group of operation subunits is the same as the antenna number; and when the matched filtering data of one symbol are calculated, each operation subunit in the group firstly finishes a real product accumulation operation decomposed into the group from multiple complex product accumulation operations corresponding to the antenna, then accumulates the operation result of each operation subunit in the group, and finally adds two of four accumulated sums and subtracts the other two to obtain a real part and a virtual part of the matched filtering data of the symbol. The device adopts a universal circuit apparatus with a simple structure and low cost, and a hardware realizing method is provided for the matched filtering operation.

Description

technical field [0001] The present invention relates to the field of integrated circuit design, FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) design field and wireless communication field, relate in particular to be used for TD-SCDMA (Time Division-Synchronous Code Division Multiple Access, Time Division Synchronous Code Division Method and device for matched filtering in joint detection of multiple access) system. Background technique [0002] In the baseband processing of TD-SCDMA system, joint detection technology is proposed on the basis of combining multi-user and multi-antenna detection technology. After the channel estimation, the impulse response data mapped by the VRU (Virtual Spread Spectrum Unit) and the antenna data are processed by each module to output descrambling, despreading and demodulated symbol-level data, which is input into the joint detection system and processed by DSP. Symbol-level processing. Using this technology can effecti...

Claims

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Application Information

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IPC IPC(8): H04W24/00H04B17/00
Inventor 邱伟
Owner SANECHIPS TECH CO LTD
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