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812 results about "Register data" patented technology

Register data sources. Registration is the process of extracting metadata from the data source and copying that data to the Data Catalog service. The data remains where it currently resides, and it remains under the control of the administrators and policies of the current system. To register a data source, do the following:

Method for transmitting voice or data in a wireless network depending on billing account status

A method for paging network personal communications system voice and data services comprising transmitting a control channel origination data packet including data specifying an identification number, data specifying a user serial number, a voice airtime register data packet, and a sequence of dialed digits for activating a switch to activate a remote feature access control procedure. The control channel origination data packet is then transmitted through control channels or digital access channels of a paging network. The control channel origination data packet is received and stored cellular base station. The control channel origination data packet is relayed to a mobile switching center and then a selected service may be activated if debit information requirements of a user are met by loading and comparing parameter table values for the identification number and the serial number or the user at the mobile switching center. A personal communications apparatus is also disclosed having a housing and circuitry for transmitting a control channel origination data packet. A speaker is mounted in housing and includes a display screen for displaying data messages and a keypad for entering a landline telephone number or mobile number. A plurality of selection keys allow for selecting a data message for transmission from the apparatus.
Owner:AERIS COMM

Technique for efficiently managing bandwidth registration for multiple spanning tree options

A technique efficiently manages bandwidth (BW) registration for multiple spanning tree options in a computer network. According to the novel technique, an entry bridge determines multiple spanning tree paths to other bridges of the network (namely, one or more available spanning trees rooted at one or more bridges of the network) and determines a utilized (registered) BW on each of those paths. Upon receiving a request to initiate BW registration for a data flow to a destination end point, e.g., from an application source end point, the entry bridge selects one of the spanning tree paths to utilize for the data flow. Selection of the spanning tree path from among the multiple available paths may be based on (i) available bandwidth of the paths, (ii) a shortest of the paths, and (iii) a lowest bridge identifier ID for the bridge root for the path. The entry bridge sends a registration message for the data flow towards the destination end point along the selected spanning tree path. If successful, the data flow is transmitted on the selected path. If not, the entry bridge attempts to register the data flow on a next best alternate spanning tree, e.g., until a successful registration or until a determination that no further alternate spanning trees exist.
Owner:CISCO TECH INC

Data processing apparatus and method for performing rearrangement operations

A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An instruction decoder is responsive to at least one but no more than N rearrangement instructions, where N is an odd plural number, to generate control signals to control the processing circuitry to perform a rearrangement process at least equivalent to: obtaining as source data elements the data elements stored in N registers of said register data store as identified by the at least one re-arrangement instruction; performing a rearrangement operation to rearrange the source data elements between a regular N-way interleaved order and a de-interleaved order in order to produce a sequence of result data elements; and outputting the sequence of result data elements for storing in the register data store. This provides a particularly efficient technique for performing N-way interleave and de-interleave operations, where N is an odd number, resulting in high performance, low energy consumption, and reduced register use when compared with known prior art techniques.
Owner:ARM LTD

Method and apparatus for efficient handling of product return transactions

A method and apparatus for efficient handling of product returns to reduce associated costs. A computer system at a regional product return center scans a returned product for identifying information, accesses a manufacturer return approval computer system through the internet or the like, and then submits the identifying information to the manufacturer for return approval. The manufacturer computer system utilizes the identifying information to access an electronic registration database to determine whether the returned product satisfies applicable return criteria. If so, the product is approved for return to the manufacturer. The regional product return center preferably scans a plurality of returned products in a single session. In response to the product identifying information submitted by the regional product return center, the manufacturer provides a list of approved returns and unapproved returns, along with a return authorization number for the batch of approved returns. The regional product return center then assembles the approved product returns into a box, shipping pallet, or the like, applies a label indicating the return authorization label, and ships the batch to the manufacturer. Shipping costs can be saved by omitting rejected product returns from the shipment. The manufacturer can handle the approved product returns from the regional return center as a batch, thereby reducing costs.
Owner:E2INTERACTIVE INC D B A E2INTERACTIVE

Methods and systems for encoding and protecting data using digital signature and watermarking techniques

Systems and methods are provided for protecting and managing electronic data signals that are registered in accordance with a predefined encoding scheme, while allowing access to unregistered data signals. In one embodiment a relatively hard-to-remove, easy-to-detect, strong watermark is inserted in a data signal. The data signal is divided into a sequence of blocks, and a digital signature for each block is embedded in the signal via a watermark. The data signal is then stored and distributed on, e.g., a compact disc, a DVD, or the like. When a user attempts to access or use a portion of the data signal, the signal is checked for the presence of a watermark containing the digital signature for the desired portion of the signal. If the watermark is found, the digital signature is extracted and used to verify the authenticity of the desired portion of the signal. If the signature-containing watermark is not found, the signal is checked for the presence of the strong watermark. If the strong watermark is found, further use of the signal is inhibited, as the presence of the strong watermark, in combination with the absence or corruption of the signature-containing watermark, provides evidence that the signal has been improperly modified. If, on the other hand, the strong mark is not found, further use of the data signal can be allowed, as the absence of the strong mark indicates that the data signal was never registered with the signature-containing watermark.
Owner:INTERTRUST TECH CORP

Data processing apparatus and method for performing arithmetic operations in SIMD data processing

A data processing apparatus, method and a computer program product. A data processing apparatus comprising: a register data store operable to store data elements; an instruction decoder operable to decode an arithmetic returning high half instruction; a data processor operable to perform data processing operations controlled by said instruction decoder wherein: in response to said decoded arithmetic returning high half instruction, said data processor is operable to specify within said register data store, one or more source registers operable to store a plurality of source data elements of a first size, and one or more destination registers operable to store a corresponding plurality of resultant data elements of a second size, said second size being half the size of said first size; and to perform the following operations in parallel on said plurality of source data elements to produce said corresponding plurality of resultant data elements: perform an arithmetic operation on said source registers specified by said instruction to produce a plurality of corresponding intermediate result data elements; form said resultant data elements from information derived from a high half of a corresponding one of said plurality of intermediate result data elements; store said resultant data elements in said destination register.
Owner:ARM LTD

Debug interface including timing synchronization logic

A system for debugging a processor includes a logic circuit for communicating commands and data between an input/output port which operates at a first clock frequency, and trace control logic which operates at a second clock frequency that is different from the first clock frequency. In some embodiments, the input/output port is a JTAG (Joint Test Action Group) port operating at a maximum clock frequency of 25 MHz and the trace control logic operates at a clock frequency of 33 Mhz, 66 MHz, 99 MHz, or 133 mhz. A suitable JTAG clock frequency is a minimum of either half the CPU internal clock frequency or 2.25 Mhz for synchronizing the internal signals between different clock frequencies. When the input/output port, which is typically a serial/parallel input/output port, writes data to debug registers, including ITCR, DCSR, soft-address, and RX-DATA registers, timing strobe signals to the registers are synchronized to a processor clock to reduce the synchronization logic for register bits that are used by the processor and trace control logic. By synchronizing the debug register data write operations to the processor clock timing, the data bits of the registers are used by the processor and the trace logic without further synchronization. Advantageously, the amount of synchronization logic is reduced. Synchronizing the signals that cross the blocks with different clock timing facilitates communication between the processor, the trace control logic, and the serial and parallel input/output ports and reduces the amount of synchronization logic.
Owner:ADVANCED MICRO DEVICES INC
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