Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision

Abstract

A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.

Description

[0001]This application is a Div. of Ser. No. 09 / 169,255 filed Oct. 9, 1998, now U.S. Pat. No. 6,343,356, and claims benefit of Provisional Application No. 60 / 092,148 filed Jul. 9, 1998.FIELD OF THE INVENTION[0002]The present invention relates generally to improvements to processing, and more particularly to advantageous techniques for providing a scalable building block register file which in a first application of the register file provides a low cost lower capacity register file, while in a second application, a higher capacity register file with dynamic reconfiguration support for flexible data type operations is provided. The present invention also relates to advantageous techniques for providing a dynamically reconfigurable register file of variable size width for different levels of data precision operations when executing algorithms demanding variable data types of variable precision requirements and for conducting multiple parallel operations on lower precision data in 32 bi...

AI Technical Summary

Benefits of technology

[0004]The present invention advantageously addresses these problems while achieving a variety of advantages as addressed in further detail below. In one aspect of the present invention, to achieve the effect of a doublewide register file, two single wide register files, each with the same number of registers, are used in combination to provide a single register model that uses less read and write ports individually than a single register file of twice the capacity would require. Due to the reduced size of the register files and reduced number of read and write ports, higher performance implementations can be achieved as compared to a single register file of equivalent combined capacity of data width and read and write ports. The architecture designates one reduced register file to contain even register addresses and the other to contain odd register addresses. In a second aspect of this invention, the architecture designates one register file configured as two banks of registers wherein the even and odd registers are selectable by means of the read / write port address lines. In a third aspect of this invention, an additional register set of at least one register can be dynamically associated with any register in the register file to flexibly provide extended precision data width to any selected file register.

[0005]By appropriate multiplexing and control logic, single width, double width, and extended precision accessing are made available. By architecture definition, double width accesses are constrained to only work on even-odd register pairs thereby treating the two separate register files as a single addressable file of twice the width of an individual register. By convention and as dictated by the architecture, either the even or odd register file is designated as containing the upper half of the bits in a double width access. Double width accesses may occur on the read, write operations, or both depending on the operation to be performed. In this way, the access width of the register file is doubled without the addition of costly read / write ports or more bits per each register and the number of required read and write ports per half is reduced. The double width register file achieved by this invention provides the single width accesses for a simpler programming model when dealing with data types of single width. Additionally, since the same number of read and write ports exist on both halves, single width accesses across the full even plus odd register address space are possible.

Problems solved by technology

This desire is offset by the hardware cost to implement a wider register file or the hardware cost to implement additional read and write ports.

The problem is how to achieve a dynamically configurable register file with extended precision at a reduced hardware cost without affecting general capabilities including performance.

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