42 results about "MIMD" patented technology

Executing MIMD programs on a SIMD machine, including establishing SIMD partitions on the SIMD machine; booting SIMD partitions in MIMD mode; executing MIMD programs on the compute nodes of a first SIMD partition booted in MIMD mode; re-executing a launcher program by an operating system on a compute node in the first SIMD partition booted in MIMD mode upon termination of the MIMD program executed by the launcher program; determining by a scheduler that the first SIMD partition booted in MIMD mode is required to establish a new SIMD partition large enough to run a SIMD program that is scheduled for execution; moving by the scheduler data processing operations from the first SIMD partition booted in MIMD mode to the second SIMD partition booted in MIMD mode; and establishing by the scheduler the new SIMD partition.

Executing MIMD programs on a SIMD machine, the SIMD machine including a plurality of compute nodes, each compute node capable of executing only a single thread of execution, the compute nodes initially configured exclusively for SIMD operations, the SIMD machine further comprising a data communications network, the network comprising synchronous data communications links among the compute nodes, including establishing one or more SIMD partitions, booting one or more SIMD partitions in MIMD mode; establishing a MIMD partition; executing by launcher programs a plurality of MIMD programs on two or more of the compute nodes of the MIMD partition; and re-executing a launcher program by an operating system on a compute node in the MIMD partition upon termination of the MIMD program executed by the launcher program.

A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.

Executing Multiple Instructions Multiple Data (‘MIMD’) programs on a Single Instruction Multiple Data (‘SIMD’) machine, the SIMD machine including a plurality of compute nodes, each compute node capable of executing only a single thread of execution, the compute nodes initially configured exclusively for SIMD operations, the SIMD machine further comprising a data communications network, the network comprising synchronous data communications links among the compute nodes, including establishing a SIMD partition comprising a plurality of the compute nodes; booting the SIMD partition in MIMD mode; executing by launcher programs a plurality of MIMD programs on compute nodes in the SIMD partition; and re-executing a launcher program by an operating system on a compute node in the SIMD partition upon termination of the MIMD program executed by the launcher program.

Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation. Multiple data shift commands may be utilized such that the plurality of code blocks have an individual shifting command to thereby implement different data shifting with respect to each code block.

Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the PEs, where P<S, operate as an instruction cache. The remaining memories operate as data memories or as data cache memories. One out of S sets of general-purpose registers, inherently belonging to the PEs, directly operates as a general register group for the PU. Out of the remaining S−1 sets, T set or a required number of sets, where T<S−1, are used as storage registers that store tags of the instruction cache.

Executing MIMD programs on a SIMD machine, including establishing on the SIMD machine a plurality of SIMD partitions; booting a first SIMD partition in MIMD mode; executing, on a compute node of the first SIMD partition booted in MIMD mode, a MIMD accelerator program; executing a SIMD program in a second SIMD partition, one instance of the SIMD program executing on each compute node of the second SIMD partition, each instance of the SIMD program carrying out a portion of the data processing effected by the SIMD program; and accelerating, by an instance of the SIMD program through the MIMD accelerator program, a portion of the data processing of the instance of the SIMD program.

In one embodiment a method for controlling instruction flow in a multiprocessor environment is disclosed. The method can include retrieving at least one slice instruction that is executable by more than one processing unit in a plurality of processing units. The method can also retrieve a global instruction that indicates a processing unit from a plurality of processing units that will receive the at least one slice instruction and the method can load the at least one slice instruction to the more than one processing unit in response to the global instruction. Such instruction control can allow the system to operate in a single input multiple data (SIMD) mode, a multiple instruction multiple data (MIMD) mode or a hybrid thereof.

The invention discloses a wavefront signal processing platform of a thousand-unit-level self-adaptive optical system. The wavefront signal processing platform of the thousand-unit-level self-adaptive optical system uses a wavefront error detecting module (1) to perform wavefront slope detection on a subspot; with a subaperture line as a pace, slope data is sent to three resetting control modules (2) in a broadcasting way through a set of local bus I on an interconnecting backplate (4); the three resetting control modules form an MIMD (multiple instruction multiple data) array machine to perform voltage solving and PID (proportion integration differentiation) control operation of a deformable mirror actuator; three paths of digital control voltages are output to an amplifying system of the deformable mirror actuator; data communication is realized among the three resetting control modules through another set of local bus III; and a signal processing platform uses a monitoring host (3) to load parameters and monitor signals of the wavefront error detecting module and the three resetting control modules through a PCI (peripheral component interconnecting) bus II. Compared with the conventional implementing way, the wavefront signal processing platform of the thousand-unit-level self-adaptive optical system has the characteristics of good timeliness, small volume and high integration.

Systems and methods are described for low density parity check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel. The parallel LDPC decoder can be reset to simultaneously decode multiple codewords with a resettable size. While the parallel LDPC decoder is running, multiple active portions of the decoder logic are configured to process multiple code blocks in parallel, with each active region processing a respective code block. A decoder-restricted cyclic shifter that supports multiple instruction multiple data (MIMD) is used to provide a decoder logic active portion in which multiple separate different data shifts are performed on multiple code blocks while the data shift is running Bit. Multiple data shift commands can be used such that multiple code blocks have separate shift commands, thereby implementing different data shifts for each code block.

The disclosed invention enables the operation of an MIMD type, an SIMD type, or coexistence thereof in a multiprocessor system including a plurality of CPUs and reduces power consumption for instruction fetch by CPUs operating in the SIMD type. A plurality of CPUs and a plurality of memories corresponding thereto are provided. When the CPUs fetch instruction codes of different addresses from the corresponding memories, the CPUs operate independently (operation of the MIMD type). On the other hand, when the CPUs issue requests for fetching an instruction code of a same address from the corresponding memories, that is, operate in the SIMD type, the instruction code read from one of the memories by one access is parallelly supplied to the CPUs.

An MIMD processor for Java and Net processing includes a plurality of “half-processors,” separate execution units, and memory caches. Each half-processor is an MIMD processing element having resources for instruction fetch and decode and for instruction stream context management, but excluding execution resources. In other words, the execution resources are removed from the processing elements (resulting in the half-processors) and provided as separate elements for being shared by all the half-processors. The execution units, memory caches, and half-processors are operably connected by two interconnection networks that use a priority-based communications scheme for administering shared access to the execution units and memory caches by the half-processors. The MIMD machine uses a Java and/or .Net instruction set and is capable of running both separate and combined Java and .Net instructions. An instruction stream management unit may be connected to the interconnection networks for controlling communications between the half-processors and shared resources.