Parallel LDPC decoder

A decoder and code block technology, applied in the field of decoding and correcting encoded data, can solve the problems of not providing flexible design, low configuration efficiency, etc., achieve effective processing and power consumption, flexible design, and promote flexibility and efficiency.

Active Publication Date: 2019-06-28
HONG KONG APPLIED SCI & TECH RES INST
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Problems solved by technology

Existing LDPC decoder configurations are...

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  • Parallel LDPC decoder
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Embodiment Construction

[0026] Figure 1 shows a conventional LDPC decoder, which is typically used by receivers in 5G cellular networks to decode data encoded using QC-LDPC codes for data correction. Accordingly, the conventional LDPC decoder 100 of FIG. 1 includes a 5G LDPC error-correcting code decoder that receives encoded bits (eg, in log-likelihood ratios (LLRs)) from a noise signal 110 and outputs decoded bits as a decoding result 120 . At runtime, conventional LDPC decoder 100 employs hierarchical decoding logic to iteratively process the parity check equations with respect to the coded bits of a single code block for which valid codewords satisfy all the parity check equations. It can be understood from the foregoing that the conventional LDPC decoder 100 can only decode one code block at a time.

[0027] At runtime, the LDPC decoder input is a code block whose size depends on various factors. In a 5G cellular network according to current standards, base graph (base graph, BG) matrices BG1 a...

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Abstract

Systems and methods are described for low density parity check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel. The parallel LDPC decoder can be reset to simultaneously decode multiple codewords with a resettable size. While the parallel LDPC decoder is running, multiple active portions of the decoder logic are configured to process multiple code blocks in parallel, with each active region processing a respective code block. A decoder-restricted cyclic shifter that supports multiple instruction multiple data (MIMD) is used to provide a decoder logic active portion in which multiple separate different data shifts are performed on multiple code blocks while the data shift is running Bit. Multiple data shift commands can be used such that multiple code blocks have separate shift commands, thereby implementing different data shifts for each code block.

Description

[0001] Cross References to Related Applications [0002] This application is related to the commonly assigned US Patent Application No. [HKAP.P0131US.10010543349] entitled "RECONFIGURABLE SEGMENTED SCALABLE SHIFTER" filed concurrently with this application, the entire content of which is incorporated by reference is incorporated herein for all applicable purposes. technical field [0003] The present invention relates to data communication, and more particularly to decoding corrected encoded data. Background technique [0004] Today's society relies extensively on data communications for a variety of purposes, such as messaging between individuals, broadcast communications, controlling machines, networking of processor-based systems, and the like. Data can be transmitted over a variety of channels, including wired, wireless, and optical, and is subject to various sources of noise, interference, and / or other signal degradation. For example, in a cellular radio system, wirel...

Claims

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Application Information

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IPC IPC(8): H04L1/00H03M13/11
Inventor 林兴武赛义德·穆赫辛·阿巴斯杨卓函张中慧关文伟梁靖康曾江州
Owner HONG KONG APPLIED SCI & TECH RES INST
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