Method, system and apparatus for multi-level processing

A processor and data processing technology, applied in data processing power supply, electrical digital data processing, program control design, etc., to achieve the effect of reducing bandwidth requirements, simplifying parallel programming, and reducing power

Inactive Publication Date: 2013-06-12
CONVERSANT INTPROP MANAGEMENT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This requires the processors to use the bus or network again, and for N processors the cost will be:

Method used

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  • Method, system and apparatus for multi-level processing
  • Method, system and apparatus for multi-level processing
  • Method, system and apparatus for multi-level processing

Examples

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Embodiment Construction

[0044] The following embodiments focus on addressing fundamental issues of parallel processing including synchronization. A solution suitable for current and future massively parallel systems is desired. This embodiment eliminates the need for locks and provides synchronization through the upper-level processor. Upper-level processor control issues permissions to use shared data or access critical sections directly to each processor at processor speed without requiring each processor to contend for a lock. Synchronization overhead is reduced to one clock for access to shared data. Traditional synchronization using locks costs N 2 bus cycles, compared to N processor cycles for synchronization in the multi-stage processing of the present invention. For a 32 conventional multiprocessor system using a 100-cycle bus, synchronization takes 32 x 32 x 100 cycles, compared to only 32 x 1 cycles for multi-stage processing, providing a gain of 3200 times.

[0045] figure 2 is a bloc...

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Abstract

A Multi-Level Processor (200) for reducing the cost of synchronization overhead including an upper level processor (201) for taking control and issuing the right to use shared data and to enter critical sections directly to each of a plurality of lower level processors (202, 203...20n) at processor speed. In one embodiment the instruction registers of lower level parallel processors are mapped to the data memory of upper level processor (201). Another embodiment (1300) incorporates three levels of processors. The method includes mapping the instructions of lower level processors into the memory of an upper level processor and controlling the operation of lower level processors. A variant of the method and apparatus facilitates the execution of Single Instruction Multiple Data (SIMD) and single to multiple instruction and multiple data (SI>MIMD). The processor includes the ability to stretch the clock frequency to reduce power consumption.

Description

technical field [0001] This invention relates to computer data processing and in particular to multiprocessor data processing. The present invention more particularly relates to devices, methods and systems for synchronizing multi-stage processors. Background technique [0002] Due to recent improvements in technology and architecture, the capabilities of a single microprocessor have continued to increase in performance, speed, and complexity. This improvement has recently encountered diminishing returns. Due to the growing memory / processor speed gap and the delays caused by the conductors within the chip, the performance of individual processors has begun to reach its limits. At the same time, power and thermal management constraints due to higher component densities have slowed clock rate increases. [0003] Although the performance of individual processors is reaching its limits, computing power is being challenged by new multimedia applications, more complex digital s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/46G06F1/08G06F1/32G06F9/30
CPCG06F1/12G06F9/30079G06F9/30087G06F9/3851G06F9/3869G06F9/3887G06F9/526G06F15/76G06F1/08G06F1/32G06F9/30G06F9/46
Inventor N·梅克希尔
Owner CONVERSANT INTPROP MANAGEMENT INC
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