7 results about "Instruction register" patented technology

The application provides a data decoding method, and relates to the technical field of data decoding, and the method comprises the following steps: receiving serial port data, determining the byte length of each data segment in the serial port data based on a preset serial port protocol; storing instruction bits, address bits and data bits in the serial port data in instruction registers, address registers and data registers respectively; obtaining operation instructions, operation addresses and operation data based on the instruction registers, the address registers and the data registers, and performing operations corresponding to the operation instructions, the operation addresses and the operation data to complete decoding of the serial port data. The application can realize decoding of the serial port data through only registers, avoids the problem that the decoding system structure is excessively redundant and complex in the prior art serial port data decoding technology, and improves the decoding speed of the serial port data.

A memory component includes: a memory cell comprising an array of memory cells; a controller for the memory cell; and a JTAG test interface including a plurality of contact pads adapted to connect the memory component to a host device and / or a test machine, wherein the test interface further includes a plurality of test registers configured to store operational instructions for performing the tests on the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. Related system-on-a-chip devices and related methods are also disclosed.

An instruction is executed within a computing environment. Executing the instruction includes obtaining a plurality of operands of the instruction. Obtaining the plurality of operands includes retrieving from a register of the instruction multiple designations of multiple operand locations. The multiple operand locations are used to provide multiple operands of the plurality of operands of the instruction. Multiple operands of the instruction are determined from the multiple operand locations. One or more operations of the instruction are performed using one or more operands of the plurality of operands of the instruction to obtain a result of the instruction.

The present disclosure relates to a thread scheduling system and method, an electronic device and a storage medium, the system comprising: an instruction cache module, an instruction register module, an execution module; the instruction cache module is configured to pre-read instruction data of a plurality of threads; the instruction register module is configured to store the pre-read instruction data of the plurality of threads, and in one clock cycle, determine a target thread and a target instruction of the target thread according to the instruction data of the plurality of threads; and the instruction register module is configured to send the target instruction of the target thread to the execution module. The embodiment of the present disclosure effectively reduces the thread scheduling time in the instruction pipeline scenario, and improves the utilization rate of the execution module.

The invention discloses an on-chip debugging system and method for a multi-core processor. The on-chip debugging system comprises an external module ET and a core internal module DU which are shared by all processor cores. The ET module comprises an interface circuit for realizing a JTAG protocol, an IDEC with a core selection instruction decoding function and a CDAP containing a core selection module. When a core selection instruction is decoded, the CDAP maps core identification data in an IR instruction register to different bits of a CoreID register, each bit of which corresponds to a processor core. And when the corresponding bit of the CoreID is 1, the CPDC module in the DU executes assembly line debugging operation on the core. A single TAP controller is shared, a core selection instruction is expanded in a JTAG standard instruction, and flexible configuration of a debugging core is achieved through a CoreID. The flexibility of multi-core debugging is improved, and the chip area is effectively reduced by eliminating intra-core redundant TAP controllers.

In some embodiments, a data processing method for generating a synthetic view rendering of a custom product, the method comprises: initializing, for a digital asset, a coverage mapping array; wherein each member of the coverage mapping array represents a possible coverage of sub-pixel regions of a pixel, and can be held in a scalar instruction register of a computer microprocessor; calculating a distance of each edge of the triangle from a center of a sub-pixel using a single scalar set instruction, operating on a pair of two scalar instruction set registers; using the distance and an angle of the edge to select a member of the array; combining pairs of found members of the coverage mapping array using the single scalar set instruction, operating on the pair, to assemble a sub-pixel coverage map array; rendering the pixel using the sub-pixel coverage mapping array and the sub-pixel regions of the pixel.

Embodiments of the present application provide an information obtaining method, device, equipment, storage medium and program product. The method comprises: obtaining an assembly sequence of an MSA vector program, the assembly sequence comprising a first MSA assembly instruction, the first MSA assembly instruction comprising an operation instruction, a register identifier and a first memory address of execution information, the execution information being information stored in a target register indicated by the register identifier; executing the first MSA assembly instruction, and storing the execution information in the target register or at the first memory address according to the operation instruction; and when a trigger instruction is received, obtaining the execution information stored at the first memory address from the memory, the data length of the execution information being equal to the data bits of the target register. The information obtaining method, device, equipment, storage medium and program product provided by the embodiments of the present application can obtain complete execution information in a target vector register.