58 results about "Instruction register" patented technology

The invention provides a QSPI serial port switching method and system and a storage medium, and the method comprises the steps: responding to a serial port signal sent by a QSPI serial port host, recognizing a target instruction according to the serial port signal, and determining the total data interaction direction of an internal communication interface according to the target instruction; then, first configuration information of the instruction register is read, and a target flash memory is determined in the multiple flash memories according to the first configuration information; then, reading second configuration information of the instruction register, determining a target partition bit in the target flash memory according to the second configuration information, and setting the numerical value of the target partition bit to be one so as to divide the target flash memory into a plurality of target storage partitions; finally, when the number of the target flash memories is multiple, according to the total data interaction direction, the target storage partitions in the multiple target flash memories and the QSPI serial port host are controlled to synchronously conduct data switching in a triple-modular redundancy mode, and then the QSPI serial port host can easily achieve the triple-modular redundancy transmission function in the flash memory data reading process.

The invention provides a system and method for processing different instructions on the same assembly line. The system comprises a control unit and an arithmetic unit, wherein the control unit is electrically connected with the arithmetic unit; the control unit comprises an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder and a pipeline management subunit; the instruction registers include a first instruction register and a second instruction register. According to the method, instruction pipeline fusion is adopted for the two different types of instructions, and the two different instructions can run on the same pipeline through pipeline fusion, so that it is guaranteed that single-core hardware can process the two instructions on the same pipeline in a mixed mode, hardware resources are saved, and the hardware cost needed by the system is reduced; and meanwhile, the system has the advantages of high processing speed for the instruction of the first instruction type and high processing efficiency for the instruction of the second instruction type.

A processor includes a plurality of register sets of a register file, and a plurality sets of functional units which are coupled by sets of dedicated read and write buses to allow parallel execution of instruction. The register sets and functional units are organized as odd and even sets. Shared buses may also be employed. The processor may also include a time counter and a time-resource matrix and provides a method for statically dispatching instructions.

The invention discloses a control method of an embedded flash memory, which belongs to the technical field of embedded control, and comprises the following steps: data on-line writing: an AXI bus interface receives a writing instruction and writing data, and a register control module configures corresponding writing parameters; the protocol conversion control module performs format conversion and caching on the written data; the ECC error correction function module generates error-correctable data according to the converted data; the Flash control interface writes the error-correctable data into the Flash memory according to the write-in instruction; and / or data online reading: the AXI bus interface receives a reading instruction, and the register control module configures corresponding reading parameters; the Flash control interface reads error-correctable data from the Flash memory according to the reading instruction; the ECC error correction function module can carry out error correction on the error correction data; the protocol conversion control module performs format conversion on the data after error correction; and the AXI bus interface outputs the converted data, so that efficient and flexible data read-write operation is realized.

The invention discloses a data processing method, a solid state disk, a system and a storage medium, and relates to the technical field of solid state disk storage, and the data processing method comprises the steps that it is detected that an NVMe PCIe link configures an instruction register, and an NVMe KV instruction is loaded from a host memory; based on the NVMe KV instruction, obtaining a key value pair configured by a host according to to-be-operated data and an operation code corresponding to a host demand operation type; the KV operation corresponding to the operation code is executed according to the key value pair, and the configuration operation of the key value pair is unloaded to the host to be executed, so that the computing resource occupation amount of the SSD is reduced, and the service quality of the SSD is improved.

The invention provides a method for achieving out-of-order transmission and order preservation of an AXI bus. A bus controller sends instructions with the same ID of the same channel to an instruction register module for storage according to an instruction sending sequence; the bus controller distributes the received multiple instructions to different slave devices according to the slave devices pointed by the instructions; the state matrix module reads a plurality of instructions stored in the instruction register one by one, analyzes instruction information and stores the instruction information, the state matrix module adds state information and decoding / masking operation to each piece of instruction information, and only one instruction is given to a plurality of instructions with the same ID value each time to respond to the state information and decoding operation of the instructions; and the bus controller selects an instruction execution result returned by the slave device corresponding to the instruction of which the state information is a response instruction in the instruction information to the host. The invention further provides a device for realizing out-of-order transmission and order preservation of the AXI bus and a computer readable storage medium.

The present disclosure relates to a system and method for providing a flowchart-based user interface to a user and generating instruction codes of a microcontroller unit based on an operation process of the microcontroller unit designed by the user. The system for generating the instruction codes of the microcontroller unit according to an embodiment of the present disclosure includes: a memory configured to store at least one instruction; a component storage; a code conversion logic storage; and a processor, wherein the at least one instruction includes instructions for: generating a first flowchart instance based on at least one flowchart component; further receiving a target component and at least one of a property, and a value of the first flowchart instance to generate an operation process; and converting the operation process into an instruction code including an instruction, a register address, and data based on the code conversion logic.

The invention discloses a high-security chip scan chain test mode circuit and an entry method, and relates to the field of integrated circuit design, the high-security chip scan chain test mode circuit comprises a boundary scan test interface, a boundary scan test interface controller, a data register, a first data selector, a second data selector, an instruction decoder and an instruction register; the data register comprises an equipment marker register, a boundary scan register, a bypass register and a test register; the test register comprises N stages of test registers and M coding and decoding modules, and the coding and decoding modules are used for generating read-write enable signals of each stage of test register; opening the read-write permission of the test register through the instruction register and the coding and decoding module; according to the invention, the JTAG port is multiplexed, the number of pins required for testing is reduced, the difficulty of entering a scan chain test mode is increased, and the safety performance of the chip is improved.

A system and method for designing a programmable sequencer capable of modifying power up and power down sequences for power control in a power domain using a no-code approach. According to one embodiment, the system includes a memory to store at least one instruction, a component storage configured to store power component information and instruction component information, a code logic storage configured to store software code logic for generating executable code based on an instruction instance, and at least one processor configured to execute the stored instruction(s). The instruction(s) include operations for generating at least one power instance based on a power component, generating a first instruction instance based on an instruction component, determining a target power instance among the generated power instances and setting a value, and generating code including an instruction, a register address, and data based on the instruction instance, the target power instance, and the value.

The present invention discloses a joint test workgroup microcode update module, method and system. The joint test workgroup microcode update module includes a JTAG interface, a buffer and drive unit, a security and protection unit, a test access port controller, an instruction register, a data register and a microcode interface logic unit; external microcode data is loaded through the JTAG interface, and the buffer and drive unit performs signal enhancement processing on the output signal of the JTAG interface; the security and protection unit receives and verifies the security and correctness of the microcode data loaded through the JTAG interface, and controls the further transmission of the verified microcode data and intercepts the microcode data that fails the verification; the test access port controller is electrically connected to the instruction register and the data register respectively to control the transmission of data and instructions; and the microcode interface logic unit transmits the microcode data to the system interface unit. The present invention can safely and reliably update the external microcode to the processor system.

Method for detecting an attempt at linear extraction of the contents of a memory Method for detecting an attempt at linear extraction of a program code stored in a memory (10) of an electronic circuit (1), the code comprising program instructions which, to be read by a microprocessor core (14), are loaded sequentially via an instruction bus (11) into an instruction register (12) for storing the instructions controlled at least by a clock signal (clk) and a reset signal (reset), the loading of each instruction into the instruction register (12) being carried out on an edge of the clock signal (clk), the code comprising discontinuity instructions and / or so-called "security marker" instructions inserted among the program instructions so as to be read during the execution of the program, the method comprising the triggering of a predefined alert action (300),in case of non-detection of a discontinuity instruction or a security marker, according to a predefined monitoring rule. Figure for abstract: Fig. 4,

The application provides a data decoding method, and relates to the technical field of data decoding, and the method comprises the following steps: receiving serial port data, determining the byte length of each data segment in the serial port data based on a preset serial port protocol; storing instruction bits, address bits and data bits in the serial port data in instruction registers, address registers and data registers respectively; obtaining operation instructions, operation addresses and operation data based on the instruction registers, the address registers and the data registers, and performing operations corresponding to the operation instructions, the operation addresses and the operation data to complete decoding of the serial port data. The application can realize decoding of the serial port data through only registers, avoids the problem that the decoding system structure is excessively redundant and complex in the prior art serial port data decoding technology, and improves the decoding speed of the serial port data.

A memory component includes: a memory cell comprising an array of memory cells; a controller for the memory cell; and a JTAG test interface including a plurality of contact pads adapted to connect the memory component to a host device and / or a test machine, wherein the test interface further includes a plurality of test registers configured to store operational instructions for performing the tests on the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. Related system-on-a-chip devices and related methods are also disclosed.

According to the routing type CGRA fault-tolerant simulation platform, when the simulation platform runs, the instruction register sends an operation code to the PE for configuration, the PE loads a data packet from the data register, and the PE completes corresponding operation and outputs an operation result to the local router or the data register; the local router sends the data to the target PE node through a multi-hop route to complete calculation and output a result; wherein the data packet contains operands and address information. The platform realizes a routing type CGRA interconnection structure model, a user can flexibly configure all PE, network scale, routing algorithm and other parameters, and can read a data packet from any specified PE node and forward the data packet to a target PE through multi-hop routing so as to simulate time delays under different conditions.

The present invention discloses a system for implementing an asymmetric algorithm multi-core parallel architecture using a single instruction memory for multiple lightweight processors. The system comprises an AXI bus, an interface terminal, an ultra-high-speed interface, a high-speed interface, a master processor, an instruction register, an asymmetric key memory, and multiple lightweight processors. Each lightweight processor is connected to an asymmetric algorithm core and an asymmetric interface memory, and each lightweight processor is connected to the instruction register and the asymmetric key memory. The asymmetric key memory, asymmetric interface memory, interface terminal, ultra-high-speed interface, high-speed interface, and master processor are all connected to the AXI bus. Advantages of the system include: using one instruction memory to provide instruction reading for multiple lightweight processors and one asymmetric key memory to provide asymmetric keys for multiple lightweight processors to implement an asymmetric algorithm chip with a reduced area, thereby reducing costs and preventing excessive heat generation during chip operation.

A processing element array of a processor, comprising a plurality of processing elements or nodes, each of the processing elements including at least one instruction register, a control unit, at least one arithmetic or logic unit, and one or more storage elements, and being configured to store, decode and execute an instruction; the instruction register and the storage elements are configured to be writable from one or more data buses; and the arithmetic or logic unit is configured to receive input from one of the storage elements and to output a result to one or more other processing elements of the array of processing elements via the one or more data buses. Also, a fabric cell or tile of a processor, comprising such a processing element array, an S bus that constitutes the data bus, and a cell or tile interface node. The interface node connects an external message bus to the S bus of the fabric cell; the S bus implements the datapath of the processing elements, and facilitates data exchange between the processing elements, and between the interface node and the cell or tile interface node and processing elements; and the interface node comprises a plurality of message registers and is configured to forward instructions to the processing elements, coordinate eviction and restoring locally, and assist the processing elements during the execution of communication and fragment instance management instructions.

The present application relates to the field of integrated circuit test and embedded chip debugging technology, and particularly relates to a JTAG communication implementation method without IR decoding, comprising the following steps: S1, receiving a reset signal to make a JTAG state machine enter a Test-Logic-Reset state; S2, detecting a TMS pin level in the Test-Logic-Reset state, if the TMS pin level is low, jumping to a Run-Test / Idle state, otherwise maintaining the current state; S3, counting a TCK clock rising edge in the Run-Test / Idle state, the count value is recorded as C, and jumping to a SelectDR-Scan state when the TMS is high; S4, in the SelectDR-Scan state, if the TMS is high, returning to the Test-Logic-Reset, if the TMS is low, entering a Capture-DR state. The present application discards all IR related states in the standard JTAG protocol, simplifies the original 16 state machine into 9 effective states containing only the DR path, and does not need to perform scanning and decoding operations of the instruction register in the communication process, directly determines the access target by counting the TCK clock, which removes the IR decoding circuit on the one hand, and saves multiple IR state periods in the traditional JTAG on the other hand.

An instruction is executed within a computing environment. Executing the instruction includes obtaining a plurality of operands of the instruction. Obtaining the plurality of operands includes retrieving from a register of the instruction multiple designations of multiple operand locations. The multiple operand locations are used to provide multiple operands of the plurality of operands of the instruction. Multiple operands of the instruction are determined from the multiple operand locations. One or more operations of the instruction are performed using one or more operands of the plurality of operands of the instruction to obtain a result of the instruction.

The invention discloses an optical module and an optical module energy consumption control method. The optical module comprises a golden finger, a light emitting chip, a TEC chip, a CDR chip, an APD circuit, a light receiving chip and an MCU. The MCU comprises a power consumption register and an optical instruction register. The MCU is configured to control the TEC chip to be closed, the CDR chip to be closed, the voltage of the APD circuit to be reduced and the optical receiving chip to be closed when a power consumption instruction value in the power consumption register is a first preset value. And when the power consumption instruction value in the power consumption register is a second preset value and the optical instruction value in the optical instruction register is a third preset value, controlling the CDR chip to be turned on, controlling the optical receiving chip to be turned on, increasing the voltage of the APD circuit, controlling the emission driving chip to be turned on and controlling the TEC chip to be turned on. And when the power consumption instruction value in the power consumption register is a second preset value and the optical instruction value in the optical instruction register is a fourth preset value, controlling the optical emission chip to be closed.

In some embodiments, a data processing method for generating a synthetic view rendering of a custom product, the method comprises: initializing, for a digital asset, a coverage mapping array; wherein each member of the coverage mapping array represents a possible coverage of sub-pixel regions of a pixel, and can be held in a scalar instruction register of a computer microprocessor; calculating a distance of each edge of the triangle from a center of a sub-pixel using a single scalar set instruction, operating on a pair of two scalar instruction set registers; using the distance and an angle of the edge to select a member of the array; combining pairs of found members of the coverage mapping array using the single scalar set instruction, operating on the pair, to assemble a sub-pixel coverage map array; rendering the pixel using the sub-pixel coverage mapping array and the sub-pixel regions of the pixel.

The data processing method, the electronic device and the storage medium are applied to the network device, the network device comprises a local trusted processing unit and a pipeline processing unit, the local trusted processing unit is internally provided with an instruction register supporting quick reading and writing, and the method comprises the steps that the local trusted processing unit receives pipeline configuration information, according to a pre-configured assembly line expansion instruction set, the assembly line configuration information is converted into an assembly line configuration instruction, and the assembly line configuration instruction is registered in an instruction register; the assembly line processing unit reads the assembly line configuration instruction from the instruction register and dynamically updates the assembly line processing logic according to the assembly line configuration instruction to obtain updated target assembly line processing logic; and the pipeline processing unit obtains the to-be-processed data and performs data processing on the to-be-processed data according to the target pipeline processing logic to obtain a pipeline processing result. According to the method and the device, the data processing logic of the network equipment can be quickly reconfigured online.

The present disclosure relates to a thread scheduling system and method, an electronic device and a storage medium, the system comprising: an instruction cache module, an instruction register module, an execution module; the instruction cache module is configured to pre-read instruction data of a plurality of threads; the instruction register module is configured to store the pre-read instruction data of the plurality of threads, and in one clock cycle, determine a target thread and a target instruction of the target thread according to the instruction data of the plurality of threads; and the instruction register module is configured to send the target instruction of the target thread to the execution module. The embodiment of the present disclosure effectively reduces the thread scheduling time in the instruction pipeline scenario, and improves the utilization rate of the execution module.

An electronic circuit comprising: a processing unit comprising or connected to a memory containing a firmware with executable instructions; the processing unit comprising: an instruction decoder, instruction registers and an arithmetic Logical Unit; wherein the instruction decoder is configured for receiving instructions, and for converting them into operation codes and operands; and being further configured for generating one or more groupcode corresponding to the received instruction, thereby forming a stream of groupcodes during execution of said firmware by said processing unit; wherein the electronic circuit further comprises a groupcode analyser configured for receiving said stream of groupcodes, and for detecting anomalies in the firmware execution by analysing said stream of groupcodes. A method of detecting firmware anomalies.

The invention discloses an on-chip debugging system and method for a multi-core processor. The on-chip debugging system comprises an external module ET and a core internal module DU which are shared by all processor cores. The ET module comprises an interface circuit for realizing a JTAG protocol, an IDEC with a core selection instruction decoding function and a CDAP containing a core selection module. When a core selection instruction is decoded, the CDAP maps core identification data in an IR instruction register to different bits of a CoreID register, each bit of which corresponds to a processor core. And when the corresponding bit of the CoreID is 1, the CPDC module in the DU executes assembly line debugging operation on the core. A single TAP controller is shared, a core selection instruction is expanded in a JTAG standard instruction, and flexible configuration of a debugging core is achieved through a CoreID. The flexibility of multi-core debugging is improved, and the chip area is effectively reduced by eliminating intra-core redundant TAP controllers.

An apparatus has a collection of ring oscillators. An instruction register block is configured to sequentially address and activate each ring oscillator in the collection of ring oscillators. A multiplexer with input lines is connected to each ring oscillator in the collection of ring oscillators and an output line. A pulse counter is connected to the output line of the multiplexer to count the number of oscillations of a selected ring oscillator within a selected time period to form a multiple bit frequency count output signal. A data shift register receives the multiple bit frequency count output signal and produces a serial frequency count output signal.

In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

The invention discloses an RISC-V architecture-oriented non-blocking virtual-real address conversion device and method, and the device comprises an instruction transmitting region which comprises a retransmission judgment register, an id register and an instruction register, the retransmission judgment register is used for recording an instruction where TLB miss occurs, the id register is used for distributing an id value for the instruction entering the instruction transmitting region, and the instruction register is used for storing the id value in the instruction transmitting region; the instruction register is used for storing instruction information of an instruction; and the TLB processor is used for converting the virtual addresses of the instruction and the data into corresponding physical addresses. According to the method, different ids are distributed to instructions entering an instruction transmitting area through an id register, meanwhile, a retransmission judgment register is used for recording the instructions where DTLB miss occurs, and after JTLB filling is completed, the oldest instruction where DTLB miss occurs is retransmitted. According to the method, the virtual and real address conversion mode is changed from blocking to non-blocking, so that the data access efficiency of the processor is remarkably improved.

The test vector generation method provided by the invention comprises the following steps: acquiring a chip function test instruction, and analyzing task content and task input parameters contained in the function test instruction; selecting a corresponding instruction template based on the task content, calling the instruction template, assigning an instruction register value, and obtaining a TDI data sequence and TDO data according to a corresponding address parameter and write / read data in task input parameters; the instruction template is created based on a jtag protocol, an ADI protocol and a data transmission protocol of a chip test circuit, and the instruction template is associated with a jtag test driving function; calling the jtag test driving function according to the instruction register value, the TDI sequence and the TDO data, and outputting the content of the function test instruction as the combination of the TDI data, the TCK signal, the TMS signal and the TDO signal at different moments. The invention further provides a test vector generation system and a computer readable storage medium.

In some embodiments, a data processing method for generating a synthetic view rendering of a custom product, the method comprises: initializing, for a digital asset, a coverage mapping array; wherein each member of the coverage mapping array represents a possible coverage of sub-pixel regions of a pixel, and can be held in a scalar instruction register of a computer microprocessor; calculating a distance of each edge of the triangle from a center of a sub-pixel using a single scalar set instruction, operating on a pair of two scalar instruction set registers; using the distance and an angle of the edge to select a member of the array; combining pairs of found members of the coverage mapping array using the single scalar set instruction, operating on the pair, to assemble a sub-pixel coverage map array; rendering the pixel using the sub-pixel coverage mapping array and the sub-pixel regions of the pixel.

The name of the invention is "de-blocking integer pipelines during mathematical pipeline phases in a graphical environment". An apparatus for facilitating de-blocking of integer pipelines during a mathematical pipeline phase in a graphical environment is disclosed. The apparatus includes execution resources comprising: a thread arbiter; a plurality of execution pipeline hardware circuitry modules including mathematical execution pipelines and integer execution pipelines for sharing resources of the thread arbiter; the arbitration hardware circuit module is used for determining whether the mathematical execution pipeline can be used for loading mathematical operation object data of the mathematical instruction; the mathematical instruction temporary storage buffer is used for storing mathematical operation object data in response to the fact that the mathematical execution pipeline is not available; wherein the integer execution pipeline is used for receiving integer operation object data of an integer instruction and bypassing mathematical operation object data in the mathematical instruction temporary storage buffer at the same time; and wherein the mathematical execution pipeline is to receive the mathematical operation object data from the mathematical instruction register buffer in response to the mathematical execution pipeline becoming available.