28 results about "Instruction register" patented technology

The invention provides a system and method for processing different instructions on the same assembly line. The system comprises a control unit and an arithmetic unit, wherein the control unit is electrically connected with the arithmetic unit; the control unit comprises an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder and a pipeline management subunit; the instruction registers include a first instruction register and a second instruction register. According to the method, instruction pipeline fusion is adopted for the two different types of instructions, and the two different instructions can run on the same pipeline through pipeline fusion, so that it is guaranteed that single-core hardware can process the two instructions on the same pipeline in a mixed mode, hardware resources are saved, and the hardware cost needed by the system is reduced; and meanwhile, the system has the advantages of high processing speed for the instruction of the first instruction type and high processing efficiency for the instruction of the second instruction type.

The invention discloses a control method of an embedded flash memory, which belongs to the technical field of embedded control, and comprises the following steps: data on-line writing: an AXI bus interface receives a writing instruction and writing data, and a register control module configures corresponding writing parameters; the protocol conversion control module performs format conversion and caching on the written data; the ECC error correction function module generates error-correctable data according to the converted data; the Flash control interface writes the error-correctable data into the Flash memory according to the write-in instruction; and / or data online reading: the AXI bus interface receives a reading instruction, and the register control module configures corresponding reading parameters; the Flash control interface reads error-correctable data from the Flash memory according to the reading instruction; the ECC error correction function module can carry out error correction on the error correction data; the protocol conversion control module performs format conversion on the data after error correction; and the AXI bus interface outputs the converted data, so that efficient and flexible data read-write operation is realized.

The invention discloses a data processing method, a solid state disk, a system and a storage medium, and relates to the technical field of solid state disk storage, and the data processing method comprises the steps that it is detected that an NVMe PCIe link configures an instruction register, and an NVMe KV instruction is loaded from a host memory; based on the NVMe KV instruction, obtaining a key value pair configured by a host according to to-be-operated data and an operation code corresponding to a host demand operation type; the KV operation corresponding to the operation code is executed according to the key value pair, and the configuration operation of the key value pair is unloaded to the host to be executed, so that the computing resource occupation amount of the SSD is reduced, and the service quality of the SSD is improved.

The present disclosure relates to a system and method for providing a flowchart-based user interface to a user and generating instruction codes of a microcontroller unit based on an operation process of the microcontroller unit designed by the user. The system for generating the instruction codes of the microcontroller unit according to an embodiment of the present disclosure includes: a memory configured to store at least one instruction; a component storage; a code conversion logic storage; and a processor, wherein the at least one instruction includes instructions for: generating a first flowchart instance based on at least one flowchart component; further receiving a target component and at least one of a property, and a value of the first flowchart instance to generate an operation process; and converting the operation process into an instruction code including an instruction, a register address, and data based on the code conversion logic.

A system and method for designing a programmable sequencer capable of modifying power up and power down sequences for power control in a power domain using a no-code approach. According to one embodiment, the system includes a memory to store at least one instruction, a component storage configured to store power component information and instruction component information, a code logic storage configured to store software code logic for generating executable code based on an instruction instance, and at least one processor configured to execute the stored instruction(s). The instruction(s) include operations for generating at least one power instance based on a power component, generating a first instruction instance based on an instruction component, determining a target power instance among the generated power instances and setting a value, and generating code including an instruction, a register address, and data based on the instruction instance, the target power instance, and the value.

The application provides a data decoding method, and relates to the technical field of data decoding, and the method comprises the following steps: receiving serial port data, determining the byte length of each data segment in the serial port data based on a preset serial port protocol; storing instruction bits, address bits and data bits in the serial port data in instruction registers, address registers and data registers respectively; obtaining operation instructions, operation addresses and operation data based on the instruction registers, the address registers and the data registers, and performing operations corresponding to the operation instructions, the operation addresses and the operation data to complete decoding of the serial port data. The application can realize decoding of the serial port data through only registers, avoids the problem that the decoding system structure is excessively redundant and complex in the prior art serial port data decoding technology, and improves the decoding speed of the serial port data.

A memory component includes: a memory cell comprising an array of memory cells; a controller for the memory cell; and a JTAG test interface including a plurality of contact pads adapted to connect the memory component to a host device and / or a test machine, wherein the test interface further includes a plurality of test registers configured to store operational instructions for performing the tests on the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. Related system-on-a-chip devices and related methods are also disclosed.

According to the routing type CGRA fault-tolerant simulation platform, when the simulation platform runs, the instruction register sends an operation code to the PE for configuration, the PE loads a data packet from the data register, and the PE completes corresponding operation and outputs an operation result to the local router or the data register; the local router sends the data to the target PE node through a multi-hop route to complete calculation and output a result; wherein the data packet contains operands and address information. The platform realizes a routing type CGRA interconnection structure model, a user can flexibly configure all PE, network scale, routing algorithm and other parameters, and can read a data packet from any specified PE node and forward the data packet to a target PE through multi-hop routing so as to simulate time delays under different conditions.

The present invention discloses a system for implementing an asymmetric algorithm multi-core parallel architecture using a single instruction memory for multiple lightweight processors. The system comprises an AXI bus, an interface terminal, an ultra-high-speed interface, a high-speed interface, a master processor, an instruction register, an asymmetric key memory, and multiple lightweight processors. Each lightweight processor is connected to an asymmetric algorithm core and an asymmetric interface memory, and each lightweight processor is connected to the instruction register and the asymmetric key memory. The asymmetric key memory, asymmetric interface memory, interface terminal, ultra-high-speed interface, high-speed interface, and master processor are all connected to the AXI bus. Advantages of the system include: using one instruction memory to provide instruction reading for multiple lightweight processors and one asymmetric key memory to provide asymmetric keys for multiple lightweight processors to implement an asymmetric algorithm chip with a reduced area, thereby reducing costs and preventing excessive heat generation during chip operation.

A processing element array of a processor, comprising a plurality of processing elements or nodes, each of the processing elements including at least one instruction register, a control unit, at least one arithmetic or logic unit, and one or more storage elements, and being configured to store, decode and execute an instruction; the instruction register and the storage elements are configured to be writable from one or more data buses; and the arithmetic or logic unit is configured to receive input from one of the storage elements and to output a result to one or more other processing elements of the array of processing elements via the one or more data buses. Also, a fabric cell or tile of a processor, comprising such a processing element array, an S bus that constitutes the data bus, and a cell or tile interface node. The interface node connects an external message bus to the S bus of the fabric cell; the S bus implements the datapath of the processing elements, and facilitates data exchange between the processing elements, and between the interface node and the cell or tile interface node and processing elements; and the interface node comprises a plurality of message registers and is configured to forward instructions to the processing elements, coordinate eviction and restoring locally, and assist the processing elements during the execution of communication and fragment instance management instructions.

An instruction is executed within a computing environment. Executing the instruction includes obtaining a plurality of operands of the instruction. Obtaining the plurality of operands includes retrieving from a register of the instruction multiple designations of multiple operand locations. The multiple operand locations are used to provide multiple operands of the plurality of operands of the instruction. Multiple operands of the instruction are determined from the multiple operand locations. One or more operations of the instruction are performed using one or more operands of the plurality of operands of the instruction to obtain a result of the instruction.

The invention discloses an optical module and an optical module energy consumption control method. The optical module comprises a golden finger, a light emitting chip, a TEC chip, a CDR chip, an APD circuit, a light receiving chip and an MCU. The MCU comprises a power consumption register and an optical instruction register. The MCU is configured to control the TEC chip to be closed, the CDR chip to be closed, the voltage of the APD circuit to be reduced and the optical receiving chip to be closed when a power consumption instruction value in the power consumption register is a first preset value. And when the power consumption instruction value in the power consumption register is a second preset value and the optical instruction value in the optical instruction register is a third preset value, controlling the CDR chip to be turned on, controlling the optical receiving chip to be turned on, increasing the voltage of the APD circuit, controlling the emission driving chip to be turned on and controlling the TEC chip to be turned on. And when the power consumption instruction value in the power consumption register is a second preset value and the optical instruction value in the optical instruction register is a fourth preset value, controlling the optical emission chip to be closed.

In some embodiments, a data processing method for generating a synthetic view rendering of a custom product, the method comprises: initializing, for a digital asset, a coverage mapping array; wherein each member of the coverage mapping array represents a possible coverage of sub-pixel regions of a pixel, and can be held in a scalar instruction register of a computer microprocessor; calculating a distance of each edge of the triangle from a center of a sub-pixel using a single scalar set instruction, operating on a pair of two scalar instruction set registers; using the distance and an angle of the edge to select a member of the array; combining pairs of found members of the coverage mapping array using the single scalar set instruction, operating on the pair, to assemble a sub-pixel coverage map array; rendering the pixel using the sub-pixel coverage mapping array and the sub-pixel regions of the pixel.

The present disclosure relates to a thread scheduling system and method, an electronic device and a storage medium, the system comprising: an instruction cache module, an instruction register module, an execution module; the instruction cache module is configured to pre-read instruction data of a plurality of threads; the instruction register module is configured to store the pre-read instruction data of the plurality of threads, and in one clock cycle, determine a target thread and a target instruction of the target thread according to the instruction data of the plurality of threads; and the instruction register module is configured to send the target instruction of the target thread to the execution module. The embodiment of the present disclosure effectively reduces the thread scheduling time in the instruction pipeline scenario, and improves the utilization rate of the execution module.

An electronic circuit comprising: a processing unit comprising or connected to a memory containing a firmware with executable instructions; the processing unit comprising: an instruction decoder, instruction registers and an arithmetic Logical Unit; wherein the instruction decoder is configured for receiving instructions, and for converting them into operation codes and operands; and being further configured for generating one or more groupcode corresponding to the received instruction, thereby forming a stream of groupcodes during execution of said firmware by said processing unit; wherein the electronic circuit further comprises a groupcode analyser configured for receiving said stream of groupcodes, and for detecting anomalies in the firmware execution by analysing said stream of groupcodes. A method of detecting firmware anomalies.

The invention discloses an on-chip debugging system and method for a multi-core processor. The on-chip debugging system comprises an external module ET and a core internal module DU which are shared by all processor cores. The ET module comprises an interface circuit for realizing a JTAG protocol, an IDEC with a core selection instruction decoding function and a CDAP containing a core selection module. When a core selection instruction is decoded, the CDAP maps core identification data in an IR instruction register to different bits of a CoreID register, each bit of which corresponds to a processor core. And when the corresponding bit of the CoreID is 1, the CPDC module in the DU executes assembly line debugging operation on the core. A single TAP controller is shared, a core selection instruction is expanded in a JTAG standard instruction, and flexible configuration of a debugging core is achieved through a CoreID. The flexibility of multi-core debugging is improved, and the chip area is effectively reduced by eliminating intra-core redundant TAP controllers.

An apparatus has a collection of ring oscillators. An instruction register block is configured to sequentially address and activate each ring oscillator in the collection of ring oscillators. A multiplexer with input lines is connected to each ring oscillator in the collection of ring oscillators and an output line. A pulse counter is connected to the output line of the multiplexer to count the number of oscillations of a selected ring oscillator within a selected time period to form a multiple bit frequency count output signal. A data shift register receives the multiple bit frequency count output signal and produces a serial frequency count output signal.

The invention discloses an RISC-V architecture-oriented non-blocking virtual-real address conversion device and method, and the device comprises an instruction transmitting region which comprises a retransmission judgment register, an id register and an instruction register, the retransmission judgment register is used for recording an instruction where TLB miss occurs, the id register is used for distributing an id value for the instruction entering the instruction transmitting region, and the instruction register is used for storing the id value in the instruction transmitting region; the instruction register is used for storing instruction information of an instruction; and the TLB processor is used for converting the virtual addresses of the instruction and the data into corresponding physical addresses. According to the method, different ids are distributed to instructions entering an instruction transmitting area through an id register, meanwhile, a retransmission judgment register is used for recording the instructions where DTLB miss occurs, and after JTLB filling is completed, the oldest instruction where DTLB miss occurs is retransmitted. According to the method, the virtual and real address conversion mode is changed from blocking to non-blocking, so that the data access efficiency of the processor is remarkably improved.

In some embodiments, a data processing method for generating a synthetic view rendering of a custom product, the method comprises: initializing, for a digital asset, a coverage mapping array; wherein each member of the coverage mapping array represents a possible coverage of sub-pixel regions of a pixel, and can be held in a scalar instruction register of a computer microprocessor; calculating a distance of each edge of the triangle from a center of a sub-pixel using a single scalar set instruction, operating on a pair of two scalar instruction set registers; using the distance and an angle of the edge to select a member of the array; combining pairs of found members of the coverage mapping array using the single scalar set instruction, operating on the pair, to assemble a sub-pixel coverage map array; rendering the pixel using the sub-pixel coverage mapping array and the sub-pixel regions of the pixel.

In some embodiments, a data processing method for generating a synthetic view rendering of a custom product, the method comprises: initializing, for a digital asset, a coverage mapping array; wherein each member of the coverage mapping array represents a possible coverage of sub-pixel regions of a pixel, and can be held in a scalar instruction register of a computer microprocessor; calculating a distance of each edge of the triangle from a center of a sub-pixel using a single scalar set instruction, operating on a pair of two scalar instruction set registers; using the distance and an angle of the edge to select a member of the array; combining pairs of found members of the coverage mapping array using the single scalar set instruction, operating on the pair, to assemble a sub-pixel coverage map array; rendering the pixel using the sub-pixel coverage mapping array and the sub-pixel regions of the pixel.

A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

Embodiments of the present application provide a machine code instruction conversion method and device, electronic equipment and readable storage medium, and relate to the technical field of computers. The method comprises: obtaining a machine code instruction to be converted, wherein the machine code instruction can comprise an operation code, a first operand, a second operand, a third operand and an original immediate number; analyzing the machine code instruction to determine a target assembly instruction corresponding to the operation code and the second operand, register names corresponding to the first operand and the third operand respectively, and a target immediate number obtained after conversion based on the original immediate number; and obtaining an assembly code corresponding to the machine code instruction based on preset rule information combination of the obtained target assembly instruction, register names and target immediate number, which realizes convenient conversion of the machine code instruction into the assembly code, is conducive to further analysis of the assembly code by technical personnel, and effectively fills the technical gap of conversion of the machine code into the assembly code.

The present invention relates to a system and a method for providing a user with a user interface based on a flow chart and generating an instruction code of a micro-control unit based on an action flow of the micro-control unit designed by the user. The instruction code generation system of the micro-control unit according to one embodiment of the present invention comprises a memory for storing at least one command, a component repository, a transcoding logic repository and a processor, wherein the at least one command comprises the following commands: generating a first flow chart instance based on at least one flow chart component; receiving at least one of a target component and an attribute and a value of the first flow chart instance to generate an action flow; and translating the action flow into instruction code including an instruction, a register address, and data based on transcoding logic.

Embodiments of the present application provide an interface calling method, a chip and a computing device. A specific implementation of the method includes: receiving an access request of a first application based on a general interface, the access request being used to access a Joint Test Action Group (JTAG) register; calling an intermediate interface based on the access request, the intermediate interface being used to call a first operation instruction registered in a JTAG structure; and performing an access operation on the JTAG register through a JTAG controller based on the first operation instruction to respond to the access request. Thus, when the JTAG controller or the JTAG register changes, only the first operation instruction needs to be reconstructed to maintain the original general interface and the intermediate interface to respond to the access request, thereby improving the development efficiency of the system and reducing the maintenance cost of the system.

The present invention provides a test vector generation method, comprising: obtaining a chip functional test instruction, and parsing the task content and task input parameters contained in the functional test instruction; selecting a corresponding instruction template based on the task content, calling the instruction template, assigning an instruction register value, and obtaining a TDI data sequence and TDO data based on the corresponding address parameters and write / read data in the task input parameters; the instruction template is created based on a jtag protocol, an ADI protocol, and a data transmission protocol of a chip test circuit, and the instruction template is associated with a jtag test driver function; calling the jtag test driver function based on the instruction register value, the TDI data sequence, and the TDO data, and outputting the functional test instruction content as a combination of a TDI signal, a TCK signal, a TMS signal, and a TDO signal at different times. The present invention also provides a test vector generation system and a computer-readable storage medium.

The present invention relates to systems and methods for designing a programmable sequencer that can vary the power-on / power-off sequence for controlling power in a power domain in a code-free manner. The system comprises a memory for storing at least one instruction; a component repository storing power component information and instruction component information; a code logic repository storing software code logic for generating code based on the instruction instance; and at least one processor to execute at least one instruction stored in the memory, the at least one instruction comprising: instructions to generate at least one power instance constituting the programmable sequencer based on the power component; instructions to generate a first instruction instance based on the instruction component; an instruction for determining a target power instance of a first instruction instance in the at least one power instance and setting a value; and an instruction to generate code including the instruction, the register address, and the data based on the first instruction instance, the target power instance, and the value.

Embodiments of the present application provide an information obtaining method, device, equipment, storage medium and program product. The method comprises: obtaining an assembly sequence of an MSA vector program, the assembly sequence comprising a first MSA assembly instruction, the first MSA assembly instruction comprising an operation instruction, a register identifier and a first memory address of execution information, the execution information being information stored in a target register indicated by the register identifier; executing the first MSA assembly instruction, and storing the execution information in the target register or at the first memory address according to the operation instruction; and when a trigger instruction is received, obtaining the execution information stored at the first memory address from the memory, the data length of the execution information being equal to the data bits of the target register. The information obtaining method, device, equipment, storage medium and program product provided by the embodiments of the present application can obtain complete execution information in a target vector register.

The invention relates to a thread scheduling system and method, electronic equipment and a storage medium. The system comprises an instruction cache module, an instruction register module and an execution module. The instruction caching module is used for pre-reading instruction data of a plurality of threads; the instruction register module is used for storing pre-read instruction data of the multiple threads and determining a target thread and a target instruction of the target thread according to the instruction data of the multiple threads in a clock period; and the instruction register module is used for sending a target instruction of the target thread to the execution module. According to the embodiment of the invention, the time consumption of thread scheduling in an instruction pipeline scene is effectively reduced, and the utilization rate of the execution module is improved.