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Image processing method based on FPGA accelerated convolution neural network framework

A convolutional neural network and image processing technology, applied in the field of convolutional neural network implementation, can solve the problems of increased FPGA computing time, lack of convolutional neural network algorithm optimization, and inability to fully utilize FPGA computing resources to achieve transmission efficiency , The effect of maximizing transmission efficiency

Active Publication Date: 2018-06-12
XIDIAN UNIV
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Problems solved by technology

[0005] In the current patent and research direction, the OpenCL programming language is basically used as the core of the construction. The purpose is to reduce the implementation time of converting the convolutional neural network algorithm into a hardware description language, but it does not involve the acceleration of the hardware description language code in the FPGA algorithm. At the same time, since the OpenCL programming language is not the language that actually runs on the FPGA, the running speed of the actual FPGA is not ideal.
At present, the existing technology based on OpenCL programming mainly focuses on the acceleration of the DSP module in the FPGA, and has not implemented the convolutional neural network algorithm as a whole and optimized the underlying hardware description language, and cannot make full use of the computing resources of the FPGA. It leads to an increase in FPGA calculation time, and the acceleration effect is not obvious

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  • Image processing method based on FPGA accelerated convolution neural network framework
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  • Image processing method based on FPGA accelerated convolution neural network framework

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Embodiment Construction

[0037] The embodiments and effects of the present invention will be described in detail below in conjunction with the accompanying drawings;

[0038] Step 1, process parameters.

[0039] 1.1) Read the picture and FPGA board resource parameters input by the user. The FPGA parameters include: picture size N, total block ram resource S sum , synchronous dynamic dynamic random access memory DDR3 number P and calculation function chip DSP number A;

[0040] 1.2) Design parameters, including: FPGA operation frequency f, convolution kernel size m, convolution layer number J, channel number T, pooling layer number C, activation function layer number E, multi-classification function softmax layer number G, softmax layer input number I in , softmax layer output number I out , fully connected layers Q, pooling function and activation function;

[0041] 1.3) The computer calculates the size value set X of each layer of pictures according to the read parameter values, the maximum numbe...

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Abstract

The invention discloses a image processing method based on an FPGA accelerated convolution neural network framework, which mainly solves the problems of low resource utilization rate and slow speed ofthe prior art. The plan comprises the following steps of:1) calculating a picture division fixed value according to the designed picture parameter and the FPGA resource parameter; 2) determining theDDR3 number according to the picture fixed value and distributing the block ram resource; 3) constructing a convolution neural network framework according to 1) and 2), wherein the framework comprisesa picture storage module, a picture data distribution module, a convolution module, a pool module, a picture storage back DDR3 module and an instruction register group; 4) obtaining a control instruction from the instruction register set through a handshake signal and interacts with each other, and processing the picture data according to the control instruction. The invention improves the resource utilization and acceleration effect through the FPGA-accelerated convolutional neural network framework, and can be used for image classification, target recognition, speech recognition and naturallanguage processing.

Description

technical field [0001] The invention belongs to the technical field of computer design, in particular to a convolutional neural network implementation method, which can be used for image classification, target recognition, speech recognition and natural language processing. Background technique [0002] With the advancement of integrated circuit design and manufacturing technology, the field programmable gate array with high-speed, high-density programmable logic resources has been developed rapidly, and the integration level of a single chip is getting higher and higher. In order to further improve FPGA performance, mainstream chip manufacturers have integrated digital signal processing chips DSP custom computing units with high-speed digital signal processing capabilities inside the chips. It is widely used in image processing, network communication and information security, bioinformatics and other application fields. [0003] Convolutional neural network CNN is a struct...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G06N3/04G06N3/08
CPCG06N3/063G06N3/08G06N3/045
Inventor 王坚灿董刚杨银堂
Owner XIDIAN UNIV
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