28 results about "Kernel size" patented technology

The invention discloses a road occupation construction identification method and device based on deep learning, electronic equipment and a program product. According to the recognition method, an AW-MSSPP module is introduced into a backbone network, multi-level information in a first input feature is extracted by using a multi-scale fusion structure, feature weights of different positions are adjusted through an adaptive space attention mechanism, accurate alignment of each scale feature in space is ensured, and the recognition accuracy is improved. Therefore, the recognition effect of the model on road occupation construction of different scales is improved. The neck network integrates an MSFSA module, performs multi-scale feature extraction and fusion in combination with different convolution kernel sizes, focuses a key region through space attention, inhibits interference information, enhances feature expression ability, and improves the perception effect on complex targets with different scales. Besides, an MSE-C2f module is arranged in the backbone network, and multi-scale convolution and an improved CSP bottleneck structure are fused, so that the modeling capability of the model for a complex mode is remarkably enhanced, and the overall recognition performance is effectively improved.

The invention provides a defect detection method and device for improving a YOLO model based on an attention mechanism. The method provided by the invention comprises the following steps: acquiring image data of a to-be-detected industrial product; the improved YOLOv10 model performs feature extraction, multi-scale feature fusion and defect positioning identification on the industrial product image data to obtain a defect detection result of the industrial product; wherein the SE module is used for strengthening a channel dependency relationship and detail representation of local detail features, and the CBAM module is used for modeling channel attention and space attention on global semantic features; the bridging layer controls middle and low layer features and high layer features to keep uniform channel dimension and spatial resolution by adjusting the size and stride of a convolution kernel; introducing a 1 * 1 convolutional layer after Concat operation of multi-scale feature fusion, and performing channel compression, linear fusion and semantic alignment on multi-scale fusion features; and constructing a loss function fusing the GHM loss and the dynamic IoU loss.

The application provides a remote sensing small target detection method based on large kernel convolution, and relates to the technical field of remote sensing image target detection. The method designs a C2f_UniRepLKNetBlock module, which is used in the backbone network. The module can flexibly adjust the convolution task according to the specific convolution kernel size of each convolution operation, flexibly aggregate multi-scale information, fully extract relevant feature information, play the advantages of large convolution kernel and effectively improve the detection precision. An LSKA-SPPF module is designed as a spatial pyramid pooling module of the backbone network. The LSKA-SPPF module combines the advantages of the self-attention mechanism and the large kernel convolution, decomposes the two-dimensional convolution into one-dimensional convolution, thereby reducing the interference of background information, reducing the computational complexity and memory occupation. In the regression loss calculation, the NWD method is introduced, the traditional CIoU method is combined with the NWD method, the sensitivity for detecting different scale objects in the remote sensing image is reduced, and the detection capability is improved.

This invention belongs to the field of multi-objective evolutionary neural architecture search, proposing a multi-objective evolutionary neural architecture search method that integrates convolution and self-attention. By constructing an improved multi-objective evolutionary algorithm, the efficiency of neural architecture search is increased, allowing for faster discovery and preservation of individual neural architectures during the search process, while balancing convergence and diversity. By constructing a search space that integrates convolution and attention operations, the processing capability of global and local information in image processing tasks is improved, enhancing the plasticity of the search space and the generalization performance of individuals across different task sets. Decision variables such as convolution kernel size and number of layers in the search space are encoded as individuals in the population of the improved multi-objective evolutionary algorithm. The optimal individual is searched through the operation of the improved multi-objective evolutionary algorithm and decoded into the optimal network architecture. This invention effectively improves search efficiency and obtains the best-performing neural architecture.

The application provides a method for accelerating ADD convolution implementation calculation, and the method comprises an ADD convolution process: if the convolution kernel size is kh and kw, the step is sh and sw, if kh is 2, kw is 1, sh is 2, and sw is 1, there are input image data a[1][1] = p, a[2][1] = q, and convolution kernel data b[1][1] = 1 and b[2][1] = 1, the calculation flow is: the ADD calculation process can be converted into a convolution calculation process with kernel_x = 1, kernel_y = 2, stride_x = 1 and stride_y = 2, wherein the convolution kernel data are all 1, the two input image data of the ADD need to be written into ORAM in a row interlaced manner, then written into FRAM, then the convolution kernel data are written into WRAM, NNA is started, and the convolution calculation result, which is also the ADD calculation result, can be obtained. Through the ADD convolution, the NNA is used for convolution calculation acceleration, and the ADD calculation acceleration is completed.

The application discloses a neural network structure, a feature extraction method, a device and a medium, and the method comprises the following steps: a first convolution layer with a convolution kernel size of (3*N)*N is used to perform convolution on an input feature map, and then a first activation layer is used for processing, so that a first feature map is obtained; a second convolution layer with a convolution kernel size of N*(3*N) is used to perform convolution on the first feature map, and then a first batch normalization layer and a second activation layer are used for processing, so that a second feature map is obtained; a third convolution layer with a convolution kernel size of (3*N)*N is used to perform convolution on the second feature map, and then a third activation layer is used for processing, so that a third feature map is obtained; a fourth convolution layer with a convolution kernel size of N*(3*N) is used to perform convolution on the third feature map, and then a second batch normalization layer and a fourth activation layer are used for processing, so that a fourth feature map is obtained; the fourth feature map is subjected to upsampling processing, and then pixel category prediction is performed to output a semantic segmentation map. The method improves the segmentation precision of a target with an aspect ratio that is not 1:1.

Systems, apparatuses and methods may provide technology for optimizing an inference neural network model that performs asymmetric quantization by generating a quantized neural network, wherein model weights of the neural network are quantized as signed integer values, and wherein an input layer of the neural network is configured to quantize input values as unsigned integer values, generating a weights accumulation table based on the quantized model weights and a kernel size for the neural network, and generating an output restoration function for an output layer of the neural network based on the weights accumulation table and the kernel size. The technology may also perform per-input channel quantization. The technology may also perform mixed-precision auto-tuning.

This invention provides a method for accelerating computation by concatenating Concat data to convolution. The method includes: converting the Concat calculation formula into a regular convolution formula; introducing a new convolution kernel to convert Concat to regular convolution; the kernel data being always 1 and having a fixed size of 1*1; the Concat process being converted into a regular convolution process where each input image data and the kernel data are multiplied and accumulated to obtain the output image data, i.e., the first point of the output image is the result of multiplying and accumulating the first point of the first input image and the kernel data, where the kernel size is 1*1 and the data is always 1; as the kernel slides sequentially across each input image, the data of all points in the output image is obtained, i.e., n input image data are sequentially written to FRAM along a certain dimension, and then the kernel data is written to WRAM; by configuring the NNA register to set the kernel size to 1*1 and the stride to 1*1, NNA is started, and the convolution calculation result, which is also the Concat calculation result, can be obtained.

This invention discloses a hyperspectral image classification method, medium, device, and product, relating to the field of image processing. The method includes: performing standardized preprocessing and superpixel segmentation on a hyperspectral image, and constructing a superpixel graph structure; constructing a hyperspectral image classification model including three parallel branches; each branch includes a spectral transform sub-network, a superpixel-level graph sub-network, and a pixel-level convolutional sub-network, wherein the spectral transform sub-network is a convolutional network with different kernel sizes, used to extract features from the hyperspectral image; based on the hyperspectral image features and graph structure, the parallel superpixel-level graph and pixel-level convolutional sub-networks extract superpixel-level and pixel-level features and perform feature concatenation and fusion, and obtain a classification probability distribution based on the fused features; the three parallel branches of the classification model are trained independently, and the trained model is used to classify hyperspectral images; the classification results of the three branches are determined by a majority voting method to determine the final classification result.

The invention relates to the technical field of neural network accelerators, and provides a data scheduling method suitable for a neural network accelerator and electronic equipment, and the method comprises the steps: obtaining an extended index of an input feature based on a filling mask, and determining a mapping relation between the extended index and an original index; performing convolution calculation on the input features based on the mapping relation, the convolution kernel size and a convolution traversal sequence to obtain a plurality of convolution results, and determining the convolution traversal sequence based on the pooling traversal sequence; when each convolution result is obtained, activation and pooling calculation are carried out to obtain a corresponding pooling result, and the input of each pooling calculation comprises an activation result corresponding to the current pooling calculation and a pooling result corresponding to the previous pooling calculation; and calculating a quantization result based on the pooling result corresponding to the Mth pooling calculation, and storing the quantization result in a buffer, M = a * N, a being a positive integer, and N being the size of the pooling window. The problem that the time-space overhead of data scheduling for a neural network accelerator is large is solved.

The invention relates to the technical field of super-long visual design modeling, in particular to a super-long visual design dynamic modeling system based on multi-scale feature fusion, which can dynamically judge whether to adjust the initial parameters of a multi-stage feature extraction unit, and can improve the modeling efficiency around details, components and global scale progressive logic. The convolution kernel size, the step length and the output channel number of the shallow layer unit, the middle layer unit and the deep layer unit are synchronously optimized, it is ensured that the performance of each level of unit is accurately matched with a design target, and feature extraction is changed from passive matching to active matching; pixel-level dynamic weight adaptation of each spatial position is realized, a cross-scale feature semantic incidence matrix is constructed, semantic similarity of different scale features of each position is quantified, and the weight is optimized by combining a scale priority vector of a design target, so that a generated fusion feature map can not only accurately reserve core features of each position, but also accurately retain the core features of each position. And the semantic coherence of the full-scale features can be ensured, and high-quality feature input is provided for precise modeling of a subsequent super-long visual design target.

The application provides a signal and image recognition method and system based on two-dimensional cosine convolution, and belongs to the technical field of signal and image recognition, and comprises the following steps: obtaining two-dimensional data, the two-dimensional data being an image, a time-frequency spectrum or other two-dimensional tensors; pre-processing the two-dimensional data; inputting the pre-processed two-dimensional data into a two-dimensional cosine convolution module to perform feature extraction and obtain a feature map; wherein the two-dimensional cosine convolution module generates a two-dimensional convolution kernel matrix for any convolution kernel size, and when the rank component number is 1, two-dimensional separable cosine convolution is adopted to realize: performing one-dimensional convolution on the pre-processed two-dimensional data along a width direction to obtain an intermediate feature map, and then performing one-dimensional convolution along a height direction; and outputting a classification result according to the feature map.

One embodiment provides a computing device for performing machine learning operations, the computing device comprising a hardware accelerator comprising a computing unit for performing a Winograd convolution, the computing unit being configurable to perform the Winograd convolution for a first kernel size using a transform associated with a second kernel size.

The invention discloses an attention method and device for adaptively fusing multi-scale large kernel features. The method comprises the following steps: constructing a plurality of large convolution kernel feature extraction branches with different convolution kernel sizes, and carrying out multi-scale feature extraction on convolution features of an input image to obtain multi-scale large kernel features; splicing the multi-scale large-kernel features along channel dimensions, and generating an adaptive space selection weight through pooling, convolution and activation function operations; multiplying the adaptive space selection weight of each branch by the large kernel feature of the corresponding branch element by element, and performing fusion to obtain a fusion attention weight; and performing element-by-element multiplication on the fusion attention weight and the input feature to obtain an enhanced feature of the input image. According to the invention, attention weights of different scales are adaptively fused through the attention method, so that multi-scale information is effectively fused, features of a detection target in an input image are enhanced, irrelevant features are inhibited, and target detection performance is improved.

The present disclosure belongs to the technical field of neural network processing methods, and in particular to a deep learning processing method based on Winograd, comprising: obtaining the size of a unit to be calculated; obtaining the sizes of a plurality of acceleration cores with different sizes; obtaining a calculation ratio according to the sizes of the plurality of acceleration cores; obtaining a division region of the unit to be calculated according to the size of the unit to be calculated and the calculation ratio, the division region of the unit to be calculated corresponding to the size of the acceleration core; performing calculation according to the division region, and then collecting and completing the acceleration calculation of the unit to be calculated. The present disclosure utilizes the difference in flexibility and efficiency of Winograd acceleration cores (Wino-Core) with different convolution kernel sizes and output sizes, combines a plurality of Wino-Cores with different sizes in a highly scalable deep learning processor architecture, forms a multi-core mixed heterogeneous deep learning processor, and realizes the overall improvement of the flexibility and efficiency of the Wino-DPU through the optimal allocation of the calculation power between the cores.

Systems, apparatuses and methods may provide technology for optimizing an inference neural network model that performs asymmetric quantization by generating a quantized neural network, wherein model weights of the neural network are quantized as signed integer values, and wherein an input layer of the neural network is configured to quantize input values as unsigned integer values, generating a weights accumulation table based on the quantized model weights and a kernel size for the neural network, and generating an output restoration function for an output layer of the neural network based on the weights accumulation table and the kernel size. The technology may also perform per-input channel quantization. The technology may also perform mixed-precision auto-tuning.

This invention discloses a configurable convolution acceleration device and method supporting shared micro-exponential format data, belonging to the field of neural network hardware acceleration for very large-scale integrated circuits. This acceleration device accelerates convolutional neural networks quantized using a shared micro-exponential data format. The device features a configurable design, supporting the following convolution modes: a kernel size of [value missing], a stride of 2, and zero padding of 1; and a kernel size of [value missing], a stride of 1, and zero padding of 0. The supported input feature map channels and the maximum number of rows and columns supported for these channels are: 32 / 320, 64 / 160, 128 / 80, and 256 / 40. Furthermore, the design method for this configurable convolution acceleration device, supporting new data formats, can also achieve convolution support for different MX quantization formats for input feature map data and weight data by modifying the design parameters.

The application provides a model pruning method and system for federated learning, belongs to the technical field of federated learning, calculates the importance index of convolution kernels in each convolution layer of a neural network model, prunes the convolution kernels with an importance index lower than a threshold value in terms of the number of convolution kernels, calculates the L1 norm of each vector inside the remaining convolution kernels, prunes the convolution kernels based on a preset threshold value, completes convolution kernel size pruning, and thus reduces the dimension of the convolution kernel size. The application realizes sufficient pruning of redundant parameters, greatly improves the model compression efficiency, and the proposed dynamic threshold model pruning framework dynamically adjusts the pruning range in each training round, makes the setting of the pruning rate more reasonable, and dynamically prunes the sensitive layers and non-sensitive layers of the model at different compression rates, so as to better control the pruning strength of each part of the model in the pruning process, improve the performance of the model, and be beneficial to the recovery of the accuracy of the model after pruning.

This invention relates to a method for detecting partial discharge in power transmission lines, comprising the following steps: S1, acquiring raw electrical signals from the power transmission line and dividing them into training samples and test samples; S2, batch inputting the training samples into a multi-scale one-dimensional convolutional neural network, setting thresholds and the structure and kernel size of the multi-scale one-dimensional convolutional neural network, propagating forward layer by layer to obtain the features of the training samples, and calculating the error between the expected output and the actual output; S3, propagating the error backward from the output to the input, fine-tuning the network parameters layer by layer; S4, repeating steps S2 and S3 until all training samples are completed, calculating the network's accuracy on the test samples, if the accuracy is greater than the set threshold, an ideal network is obtained; otherwise, returning to step S2; S5, outputting the accuracy of the ideal network on the test samples. This invention solves the problem of partial discharge diagnosis in power transmission lines, achieving good results under different frequency data and different convolution kernel settings.

The invention discloses a left ventricle segmentation method based on artificial intelligence and a CTA image. According to the technical scheme, the left ventricle segmentation method is characterized by comprising the steps of obtaining a CT image; inputting the CT image into the 8-layer U-Net convolutional neural network to obtain a left ventricle segmentation image; the convolutional neural network comprises a contraction path and an expansion path; the contraction path comprises nine encoder blocks, each encoder block comprises two convolutions, the kernel size is 3 * 3 pixels, the stride is 1 pixel, the zero filling number is 1 pixel, and batch normalization and rectification linear units are used as activation functions, so that the number of feature channels is doubled; the extension path comprises eight decoder blocks, each decoder comprises two convolutions, the kernel size is 3 * 3 pixels, the stride is one pixel, the zero padding number is one pixel, then batch normalization and rectification linear units are used as activation functions, the number of feature channels is halved, and the left ventricle segmentation accuracy of CT can be further improved.

The application provides an implementation method of a cavity convolution based on NNA1.0, comprising the following steps: S1, for the cavity convolution, due to the range limitation of the NNA register parameters, when the size of the expanded convolution kernel is greater than 3x3, the convolution kernel matrix needs to be split; S2, the cavity convolution process of the NNA: write the convolution kernel data into the WRAM, then write the required input image data into the FRAM, set the convolution kernel size through the NNA hardware register, wherein KH and KW must be less than or equal to 3, the pad and stride parameters, then start the NNA to perform the convolution calculation, obtain the convolution result output, and finally obtain the cavity convolution output result of one row and four pixels. The method is based on the implementation method of the fast cavity convolution calculation of the NNA1.0, and the operation speed of the cavity convolution is improved.

The present invention discloses a design method for a fast convolution and cache mode of a convolutional neural network, which fully utilizes FPGA to complete the design of the Winograd algorithm. Under a convolution kernel size of 3*3, the multiplication operation is reduced from 36 times to 16 times, and the convolution operation can be accelerated by fully utilizing DSP resources. By optimizing the cache of repeated row and column data required for the convolution sliding window operation through feature map cache and pipeline transmission, the working efficiency of the cache and conversion module is improved. The reconfigurable design of the matrix conversion module is achieved by configuring parameters. The saved DSP resources are fully utilized, the Winograd convolution calculation array is reused, the hardware resources of the FPGA are fully utilized, the computing power of the convolution acceleration module is further improved, and the dot product step is designed with low power consumption.

The patent discloses a convolution calculation method and device for optimizing energy consumption and efficiency in existing convolution calculation process. The main technical scheme of the patent is that the feature data and weight data are input to the calculation unit through the internal memory according to the block, and the input end queue of the multiplier is dynamically allocated. The patent optimizes the calculation process in the calculation unit, utilizes the channel data characteristics, makes the output results in a single multiplier group coherent, the input end weight data of each multiplier in the same multiplier group belongs to different convolution kernels, so that data competition does not occur, the adder can be directly operated, and the multiplier output does not need to wait in the queue. In addition, the convolution kernel size, form and data reading mode have no influence on the calculation process of the patent, so the corresponding calculation of different strides, different padding forms, different forms of convolution (such as various deformation convolutions) has good adaptability.

The invention provides a rolling bearing fault diagnosis model training method and device and electronic equipment, and relates to the technical field of mechanical fault intelligent diagnosis. The method comprises the following steps: acquiring original vibration signals of a rolling bearing with or without manual annotation data, constructing a source domain data set and a target domain data set, respectively inputting the data sets into a feature extraction convolutional neural network, and extracting deep features; the network comprises a plurality of convolution modules which are connected in series; the convolution kernel size of each convolution module is changed according to a preset rule; extracting features corresponding to the target domain data set are input into a domain self-adaptive module, a pseudo-label cooperative training mechanism is introduced, classification loss, domain discrimination loss and distribution alignment loss are calculated, and total loss of a system is calculated; the module comprises a domain discriminator module, a JMMD module and an MK-MMD module. And performing optimization training on the feature extraction convolutional neural network based on an Adam optimizer to obtain a rolling bearing fault diagnosis model. The adaptive capacity and stability under different working conditions can be improved.

This invention relates to the field of neural network accelerator technology, and provides a data scheduling method and electronic device suitable for neural network accelerators. The method includes: obtaining an expanded index of input features based on a padding mask, and determining the mapping relationship between the expanded index and the original index; performing convolution calculations on the input features based on the mapping relationship, the kernel size, and the convolution traversal order to obtain multiple convolution results, wherein the convolution traversal order is determined based on the pooling traversal order; performing activation and pooling calculations on each obtained convolution result to obtain a corresponding pooling result, wherein the input for each pooling calculation includes the activation result corresponding to the current pooling calculation and the pooling result corresponding to the previous pooling calculation; calculating a quantization result based on the pooling result corresponding to the Mth pooling calculation, and storing it in a buffer, where M = a × N, a is a positive integer, and N is the size of the pooling window. This addresses the problem of high time and space overhead in data scheduling for neural network accelerators.

Embodiments of the present disclosure provide a solution for visual data processing. In one embodiment, a method for visual data processing includes applying a neural network (NN)-based model including a first module for predictive fusion and a second module for a variance decoder utilizing hyper-priori information to video data for a conversion between visual data and a bitstream of visual data, the neural network (NN)-based model including a first module for predictive fusion and a second module for a variance decoder utilizing hyper-priori information, wherein at least one of a first module for predictive fusion and / or a second module for a variance decoder utilizing hyper-priori information is satisfied: the number of channels in a convolutional layer is less than or equal to a first threshold number, the total number of convolutional layers is less than or equal to a second threshold number, or a kernel size is less than or equal to a threshold size; and performing the conversion based on a first module for predictive fusion and a second module for a variance decoder utilizing the hyper-priori information.

The present invention discloses a lightweight real-time object detection method, device, server and storage medium. The method includes: extracting shallow image features by using a basic convolution module of an RT-DETR model backbone network; extracting context features by using a lightweight downsampling sub-module of a multi-scale dilated convolution module and fusing them with local features; extracting multi-scale features by using a multi-scale dilated attention sub-module of the multi-scale dilated convolution module and fusing them to obtain deep image features; and obtaining an object detection result of image data by using a hybrid encoder and decoder. By improving the BasicBlock module with the lightweight downsampling sub-module and the multi-scale dilated attention sub-module, using dilated convolution to capture surrounding context semantic information without changing the convolution kernel size instead of the original method, and the sparsity of multi-scale dilated attention at different scales, the number of model parameters and the amount of computation are reduced, enabling the model to be deployed on devices with limited computing power.

The present invention relates to a feature extraction method, convolutional neural network, on-board computing system, and computer storage medium based on an automated parking model. The method comprises: A. feeding a captured image of the parking environment into the automated parking model as input information; B. extracting features from the input information using the automated parking model's backbone network. The backbone network comprises four feature extraction stages, each of which includes a series of convolutional layers with kernel sizes of 1*3, 3*3, and 3*1, resulting in a larger receptive field than an equivalent convolutional layer structure with a kernel size of 5*5.