7 results about "Kernel size" patented technology

This invention belongs to the field of multi-objective evolutionary neural architecture search, proposing a multi-objective evolutionary neural architecture search method that integrates convolution and self-attention. By constructing an improved multi-objective evolutionary algorithm, the efficiency of neural architecture search is increased, allowing for faster discovery and preservation of individual neural architectures during the search process, while balancing convergence and diversity. By constructing a search space that integrates convolution and attention operations, the processing capability of global and local information in image processing tasks is improved, enhancing the plasticity of the search space and the generalization performance of individuals across different task sets. Decision variables such as convolution kernel size and number of layers in the search space are encoded as individuals in the population of the improved multi-objective evolutionary algorithm. The optimal individual is searched through the operation of the improved multi-objective evolutionary algorithm and decoded into the optimal network architecture. This invention effectively improves search efficiency and obtains the best-performing neural architecture.

The application provides a method for accelerating ADD convolution implementation calculation, and the method comprises an ADD convolution process: if the convolution kernel size is kh and kw, the step is sh and sw, if kh is 2, kw is 1, sh is 2, and sw is 1, there are input image data a[1][1] = p, a[2][1] = q, and convolution kernel data b[1][1] = 1 and b[2][1] = 1, the calculation flow is: the ADD calculation process can be converted into a convolution calculation process with kernel_x = 1, kernel_y = 2, stride_x = 1 and stride_y = 2, wherein the convolution kernel data are all 1, the two input image data of the ADD need to be written into ORAM in a row interlaced manner, then written into FRAM, then the convolution kernel data are written into WRAM, NNA is started, and the convolution calculation result, which is also the ADD calculation result, can be obtained. Through the ADD convolution, the NNA is used for convolution calculation acceleration, and the ADD calculation acceleration is completed.

Systems, apparatuses and methods may provide technology for optimizing an inference neural network model that performs asymmetric quantization by generating a quantized neural network, wherein model weights of the neural network are quantized as signed integer values, and wherein an input layer of the neural network is configured to quantize input values as unsigned integer values, generating a weights accumulation table based on the quantized model weights and a kernel size for the neural network, and generating an output restoration function for an output layer of the neural network based on the weights accumulation table and the kernel size. The technology may also perform per-input channel quantization. The technology may also perform mixed-precision auto-tuning.

This invention provides a method for accelerating computation by concatenating Concat data to convolution. The method includes: converting the Concat calculation formula into a regular convolution formula; introducing a new convolution kernel to convert Concat to regular convolution; the kernel data being always 1 and having a fixed size of 1*1; the Concat process being converted into a regular convolution process where each input image data and the kernel data are multiplied and accumulated to obtain the output image data, i.e., the first point of the output image is the result of multiplying and accumulating the first point of the first input image and the kernel data, where the kernel size is 1*1 and the data is always 1; as the kernel slides sequentially across each input image, the data of all points in the output image is obtained, i.e., n input image data are sequentially written to FRAM along a certain dimension, and then the kernel data is written to WRAM; by configuring the NNA register to set the kernel size to 1*1 and the stride to 1*1, NNA is started, and the convolution calculation result, which is also the Concat calculation result, can be obtained.

This invention discloses a hyperspectral image classification method, medium, device, and product, relating to the field of image processing. The method includes: performing standardized preprocessing and superpixel segmentation on a hyperspectral image, and constructing a superpixel graph structure; constructing a hyperspectral image classification model including three parallel branches; each branch includes a spectral transform sub-network, a superpixel-level graph sub-network, and a pixel-level convolutional sub-network, wherein the spectral transform sub-network is a convolutional network with different kernel sizes, used to extract features from the hyperspectral image; based on the hyperspectral image features and graph structure, the parallel superpixel-level graph and pixel-level convolutional sub-networks extract superpixel-level and pixel-level features and perform feature concatenation and fusion, and obtain a classification probability distribution based on the fused features; the three parallel branches of the classification model are trained independently, and the trained model is used to classify hyperspectral images; the classification results of the three branches are determined by a majority voting method to determine the final classification result.

This invention discloses a configurable convolution acceleration device and method supporting shared micro-exponential format data, belonging to the field of neural network hardware acceleration for very large-scale integrated circuits. This acceleration device accelerates convolutional neural networks quantized using a shared micro-exponential data format. The device features a configurable design, supporting the following convolution modes: a kernel size of [value missing], a stride of 2, and zero padding of 1; and a kernel size of [value missing], a stride of 1, and zero padding of 0. The supported input feature map channels and the maximum number of rows and columns supported for these channels are: 32 / 320, 64 / 160, 128 / 80, and 256 / 40. Furthermore, the design method for this configurable convolution acceleration device, supporting new data formats, can also achieve convolution support for different MX quantization formats for input feature map data and weight data by modifying the design parameters.

The patent discloses a convolution calculation method and device for optimizing energy consumption and efficiency in existing convolution calculation process. The main technical scheme of the patent is that the feature data and weight data are input to the calculation unit through the internal memory according to the block, and the input end queue of the multiplier is dynamically allocated. The patent optimizes the calculation process in the calculation unit, utilizes the channel data characteristics, makes the output results in a single multiplier group coherent, the input end weight data of each multiplier in the same multiplier group belongs to different convolution kernels, so that data competition does not occur, the adder can be directly operated, and the multiplier output does not need to wait in the queue. In addition, the convolution kernel size, form and data reading mode have no influence on the calculation process of the patent, so the corresponding calculation of different strides, different padding forms, different forms of convolution (such as various deformation convolutions) has good adaptability.