General convolutional neural network acceleration structure based on ZYNQ and design method

Abstract

The invention provides a method for accelerating multichannel convolution operation in a convolutional neural network. the accelerator can accelerate neural networks of any structure, can achieve programming and online configuration can be realized; the supported feature map size, feature map channel number, convolution kernel size, convolution kernel channel number and convolution stride are flexible and variable, the control logic is simple, the convolution operation parallelism degree is high, the accelerator can be applied to any ZYNQ architecture platform, and a user can cut an acceleration circuit according to dsp resources in a chip of the user; 128 dsp (Digital Signal Projection) resources can be supported at least. The universal convolutional neural network acceleration structurebased on ZYNQ comprises an ARM processor, bus interconnection, a DDR4 controller, a memory bank, a register, a convolution operation path, an auxiliary operation path, a pooling operation path and a memory access module.

Description

technical field [0001] The invention relates to the technical field of convolutional neural network hardware acceleration, in particular to a general convolutional neural network acceleration structure and design method based on ZYNQ. Background technique [0002] Convolution Neural Network (CNN) is widely used in the field of computer vision, especially in object detection and image recognition, showing good application prospects. Edge computing is a brand-new computing model whose concept is to process data directly at the edge near the data center without sending it back to the server for processing. The use of edge computing in target detection can bring a series of benefits: directly process the image on the hardware device at the acquisition end without sending it back to the host computer, saving data transmission time and reducing data transmission overhead. It is of great practical significance to realize efficient processing on hardware devices by optimizing and a...

AI Technical Summary

Problems solved by technology

The currently proposed FPGA design methods mainly focus on specific neural network acceleration methods, and only realize the acceleration of the circuit structure for specific algorithms. The versatility is poor, and the reuse of other algorithms cannot be realized.

[0004] With the increase of the number of deep convolutional neural network layers and the explosive growth of the number of parameters, its computational complexity and computing power requirements have also increased.

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