39results about How to "Limit performance" patented technology

A transceiver architecture for wireless base stations wherein a broadband radio frequency signal is carried between at least one tower-mounted unit and a ground-based unit via optical fibers, or other non-distortive media, in either digital or analog format. Each tower-mounted unit (for both reception and transmission) has an antenna, analog amplifier and an electro-optical converter. The ground unit has ultrafast data converters and digital frequency translators, as well as signal linearizers, to compensate for nonlinear distortion in the amplifiers and optical links in both directions. In one embodiment of the invention, at least one of the digital data converters, frequency translators, and linearizers includes superconducting elements mounted on a cryocooler.

Methods and systems for detecting and correcting chromatic aberration and purple fringing are disclosed. Chromatic aberration can be addressed by separating an image into color planes and then adjusting these to reduce chromatic aberration by using a specific calibration image (calibration chart) as an empirical method to calibrate the image acquisition device. Purple fringing can be corrected by initially addressing color aberration resulting from the lateral chromatic aberration (LCA). The LCA is first removed and then the correction is extended to purple fringing. A discovery is relied upon that the purple fringing is created in the direction of the chromatic aberration and is more pronounced in the direction of the chromatic aberration.

A transceiver architecture for wireless base stations wherein a broadband radio frequency signal is carried between at least one tower-mounted unit and a ground-based unit via optical fibers, or other non-distortive media, in either digital or analog format. Each tower-mounted unit (for both reception and transmission) has an antenna, analog amplifier and an electro-optical converter. The ground unit has ultrafast data converters and digital frequency translators, as well as signal linearizers, to compensate for nonlinear distortion in the amplifiers and optical links in both directions. In one embodiment of the invention, at least one of the digital data converters, frequency translators, and linearizers includes superconducting elements mounted on a cryocooler.

A technique for providing event-based secondary information to a user equipment is disclosed. According to one embodiment, the technique may be realized as a method for providing secondary information to a user equipment. The method may comprise the steps of: detecting at least one triggering event in a user equipment while the user equipment is receiving a primary content via a first communication channel; transmitting, in response to the at least one triggering event, a request for a secondary content to a phonepage server via a second communication channel, the requested secondary content comprising at least one data object; locating the at least one data object; causing the at least one data object to be transmitted to the user equipment via a third communication channel; and rendering the at least one data object on the user equipment.

A system comprising a personal computer configured to operate with another computer connected to a network of computers. The personal computer includes a microchip having a microprocessor with a control unit and at least two processing units, the control unit being configured to allow a user of the personal computer to control the two processing units, and the microchip including a power management component. The personal computer includes an internal firewall configured to allow and/or deny access to portions of the microchip both to the user of the personal computer and to a user of the microchip from the network of computers during a shared use of the microchip; and the internal firewall is configured to deny access to portions of the microchip from the network of computers.

Disclosed is a method for achieving timing closure in the design of a digital integrated circuit or system by selecting portions of the circuit or system to be optimized and portions of the circuit or system in which the effects of such optimization are to be analyzed during the optimization process. Optimized portions will include gates whose design parameters are to be changed, a first analyzed portion includes gates whose delays and edge slews are to be recomputed, and a second analyzed portion includes gates whose ATs and RATs are to be recomputed during optimization. Constraints are imposed at selected boundaries between these portions to prevent unwanted propagation of timing information and to ensure the validity of timing values used during optimization. Through this selection, the size of the problem posed to the underlying optimization method will be reduced, allowing larger circuits or systems to be optimized and allowing optimization to be performed more quickly.

The invention provides a mimicry defense method for an annular mimicry architecture without a protocol state. The method comprises the following steps that: a request side sends request information toan input agent, and the input agent copies and distributes the request information to each equivalent heterogeneous execution body through a one-way communication channel after normalizing a protocol; each equivalent heterogeneous execution body processes the request information and sends response information to a judgment module through a one-way communication channel; and the judgment module judges the response information, sends the response information to a request side through a one-way request side communication channel if judgment succeeds, and sends the judgment information to a feedback controller if judgment fails so as to adjust the state of each heterogeneous execution body. According to the mimicry defense method, the requirement on the input agent is reduced, the structure of the agent is simplified, the agent is prevented from becoming a performance bottleneck, the problem that the agent is easily attacked is solved, and the security of the whole mimicry architecture isimproved.

Aspects of increasing the quality and reliability of desktop class storage disks in enterprise storage applications are described. The aspects include monitoring a number of idle states and busy states in a disk drive, and limiting performance of read/write commands by the disk drive based on whether a sufficient number of idle states has been monitored to avoid exceeding a duty cycle rating of the disk drive.

The invention discloses a three-dimensional graphene foam flexible strain sensor and a preparation method thereof. The three-dimensional graphene foam flexible strain sensor comprises three-dimensional graphene foam; the two ends of the three-dimensional graphene foam are coated with conductive colloid; electrodes are arranged in the center of the upper surfaces of the conductive colloid, and cured high-molecular polymers are arranged on the peripheries of the three-dimensional graphene foam and the conductive colloid. According to the preparation method of the three-dimensional graphene foamflexible strain sensor, graphene is attached to a polymer template, and the three-dimensional graphene foam flexible strain sensor based on the polymer template is prepared after permeation of a high-molecular polymer material. The sensor disclosed by the invention has the advantages of high strain capacity, high sensitivity, flexibility, low cost, simple preparation method and good repeatabilityand consistency.

A carrier body for electrical or electronic component elements or circuits, the carrier body being electrically nonconductive or virtually nonconductive. In order to simplify the carrier body while at the same time providing extremely improved heat dissipation, the invention process that the carrier body is provided integrally with heat-dissipating or heat-supplying cooling elements.

A cone valve assembly including an upper valve member with a conical top portion and an axially stepped and spiraled top surface and a lower valve member including a central opening with a stepped and spiraled valve surface or edge surrounding the central opening. The upper valve member is mounted in the lower valve member such that the lower valve member is rotatable and axially movable relative to the upper valve member. Rotation of the lower valve member allows for the adjustment of an arcuate slot opening that provides a conically shaped discharge stream of water from the cone valve nozzle assembly directly onto the rotating distributor to provide the desired arc of sprinkler coverage.

A cone valve assembly including an upper valve member with a conical top portion and a stepped and spiraled top surface and a lower valve member including a central opening with a stepped and spiraled valve surface surrounding the central opening. The upper valve member is mounted in the lower valve member such that the lower valve member is rotatable and axially movable relative to the upper valve member. Rotation of the lower valve member allows for the adjustment of an arcuate slot opening that provides a conically shaped discharge stream of water from the cone valve nozzle assembly directly onto the rotating distributor to provide the desired arc of sprinkler coverage.

A cathode electrode for a fuel cell, includes a conductive carrier having pores and a catalyst having a platinum alloy supported in the pores of the conductive carrier, wherein the catalyst has in a pore diameter range of 2 to 6 nm when diameters of the pores is plotted in relation with volumes of the pores a peak value of more than 1 cm³/g and also a BET specific surface area of 1300 m²/g.

A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command.

The invention relates to a nuclear magnetic resonance atomic gyroscope based on multiple reflection cavities and an implementation method. The nuclear magnetic resonance atomic gyroscope is characterized in that two isotope gases of alkali metal atoms and xenon are filled into a gas chamber containing the multiple reflection cavities; polarization is transferred to nuclear spins of inert gas atomsby spin exchange collisions of polarized alkali metal atoms; the inert gas atoms are continuously driven by the excitation magnetic field, and the frequency of the inert gas atoms is kept resonant through the phase-locked loop to realize closed-loop work of the gyroscope; a Herriott multi-reflection cavity is introduced into the atom pool to improve the sensitivity of the system, and meanwhile, the interference caused by the introduction of an additional modulation magnetic field can be avoided, so that the stability of the system is improved; and a built-in rubidium atom magnetometer is usedfor obtaining nuclear spin signals of xenon atoms, rotation information measured by nuclear spin is obtained, and the function of the gyroscope is achieved.

The invention, which belongs to the field of infrared detection technology, provides a photovoltaic infrared detector based on a GaSb/InSb/InP heterogeneous PIN structure. The detector is composed ofa back electrode, a heavily-doped N+ type InP substrate, a heavily-doped N+ type InP electron transport layer, an undoped narrow-stopband InSb active region, and a heavily-doped P+ type GaSb hole transport layer, and a grid bar type upper electrode that are arranged successively from bottom to top. With the low-voltage metal organic chemical vapor phase epitaxy technique, a corresponding structureis prepared at the heavily-doped N+ type InP substrate and the upper electrode and the back electrode are prepared by using a magnetron sputtering technology, so that the obtained device has characteristics of high detection rate, fast response speed, high working temperature and simple preparation process and the like. At a room temperature, the normalized detection rate D* is 2.4*1010cm Hz1/2W-1. The photovoltaic infrared detector can be applied to aerospace, military, industrial and civil fields.

A method of surface grinding a Zr-rich bulk amorphous alloy article includes providing a substrate; providing a first surface grinder for rough surface grinding; and providing a second surface grinder for finish surface grinding. During the rough surface grinding, the rotating speed is in the range from 20 r/min to 30 r/min, the grinding time period is from 3 minutes to 12 minutes, and the grinding pressure is from 1 kg/cm2 to 2 kg/cm2, and a first pump circularly conveys a first lubricant to a first rotating abrasive wheel. During the finish surface grinding, the rotating speed is in the range from 30 r/min to 40 r/min, the grinding time period is from 5 minutes to 7 minutes, and the grinding pressure is from 1 kg/cm² to 2 kg/cm², and a second pump circularly conveys a second lubricant to a second rotating abrasive wheel.

The invention belongs to the technical field of multimode composite guidance information fusion, and discloses a feature fusion method based on multi-kernel learning, which specifically comprises thefollowing steps: 1) performing standardization processing on radar and infrared training feature sets respectively; 2) respectively extracting nonlinear features X (f) and Y (g) of radar and infraredby using neural networks f and g; 3) constructing a fusion criterion function on an output layer of the neural network to maximize a correlation coefficient corr (X (f), Y (g)); 4) optimizing the neural network to obtain a fused feature vector; 5) determining a pre-selected basis kernel function; 6) obtaining a synthetic kernel by adopting a weighted summation mode; 7) training a synthetic kernelby using a simple multi-kernel learning algorithm; 8) repeating the steps 1-4 for the radar and infrared test feature set during online identification, and replacing a single kernel function in a traditional support vector machine with the trained synthetic kernel; and 9) confirming the identity of the to-be-attacked target, and reducing the feature dimension and improving the identification performance of information fusion while ensuring the maximum inter-class scatter matrix and the minimum intra-class scatter matrix.

The invention relates to a hydrokinetic coupling device (10) characterized by the fact that the web (74) comprises, at the inner radial end thereof, a collar (86), which axially extends toward the front between the turbine wheel (32) and the turbine hub (40) and which is rotationally joined by friction welding respectively: at the front, to the turbine wheel (32) by a first weld joint (88) provided between a front annular contact face (90) of the collar (86) and a rear welding face (92) opposite the inner radial periphery of the turbine wheel (32) and; at the rear, to the turbine hub (40) by a second rear weld joint (96) provided between a rear annular contact face (98) of the collar (86) and a front welding face (100) opposite the outer radial periphery of the turbine hub (40).

The invention discloses a high-frequency induction heating solidification device and method for preparing high-temperature alloy, and relates to a thermal solidification device and method. The invention aims to solve the problems of coarse structure and serious element segregation of the existing NbSi-based alloy after a large number of alloying elements are added. A material spoon transmission mechanism is installed on the upper end face of a furnace body, a material turning spoon is installed on the material spoon transmission mechanism in a sealed mode to rotate and lift the material turning spoon, and a water-cooling copper crucible is cooled in an upper water-cooling mode and located in the furnace body; the lower portion of the high-frequency vibration rod is installed in the rack assembly, the high-frequency vibration rod upwards penetrates through the furnace body and then stretches into the water-cooling copper crucible, the induction coil is arranged on the water-cooling copper crucible in a sleeving mode, the alloy solidification process is effectively regulated and controlled through ultrasonic treatment, the alloy structure is improved, and the purpose of greatly improving the alloy performance is achieved. The induction coil is used for heating, so that the problems of overhigh heating speed and difficulty in temperature gradient control caused by heating by an electric arc melting method are avoided. The method is used for preparing the high-temperature alloy.

The invention provides an FPGA for high-capacity data and an opencl-based FPGA algorithm, and belongs to the technical field of data calculation. The FPGA comprises an FPGA controller, a pcie interface in instruction communication with the FPGA controller, a Flash controller, a DDR controller and an algorithm module, and also comprises a Flash memory controlled by the Flash controller and a DDR memory controlled by the DDR controller. The Flash controller is in instruction communication with the DDR controller, and the DDR controller is in instruction communication with the algorithm module; the data transmission is carried out between the pcie interface and the Flash controller, the data transmission is carried out between the Flash controller and the DDR controller, and the data transmission is carried out between the DDR controller and the algorithm module. According to the method, the Flash controller and the Flash memory are arranged on an original FPGA, so that a large amount ofto-be-calculated data is moved to the Flash memory at one time by the host through the pcie interface, and then each piece of to-be-calculated data is moved to the DDR memory, so that the situation that the data is moved through the pcie interface for multiple times is avoided, and the algorithm acceleration effect is realized.