29 results about "Algorithm acceleration" patented technology

The invention discloses a national cryptographic algorithm acceleration system supporting SM4-ZUC dual-core dynamic collaboration, and belongs to the technical field of information security and hardware acceleration. The system comprises an AXI read-write module, a configuration register module, an SM4 algorithm module and a ZUC algorithm module. The configuration register receives and distributes information such as a secret key, an initial vector and a mode through an APB interface; the AXI read-write module supports burst transmission and dynamic scheduling data read-write; the SM4 algorithm module supports three modes of GCM, CTR and ECB; and the ZUC algorithm module is compatible with ZUC-128 / 256. And the corresponding ZUC-128 / 256 and SM4 algorithms can be dynamically selected for operation by judging an encryption mode in the ZUC and SM4 algorithms. The system adopts a three-level assembly line architecture, space-time multiplexing of read-write data and encryption is realized, and throughput rate is improved.

The invention discloses a target scattering characteristic efficient solving method of a multilayer fast multi-pole collaborative principal component analysis compression algorithm. The method comprises the following steps: dividing a target model by using a hybrid tree, changing an impedance matrix into a laminated matrix by binary tree grouping, and dividing a target into a near field and a far field by octree grouping; a multi-layer fast multi-pole algorithm acceleration principal component analysis compression algorithm is adopted to compress the low-rank impedance matrix; performing nearest layer-by-layer inversion on the impedance matrix according to an SMW formula; and finally, current is obtained through matrix vector multiplication of a series of inverse matrixes and a right vector, and target scattering characteristics are solved. The method achieves the solving of the electromagnetic scattering characteristics of the complex target, and can improve the calculation efficiency of the analysis of the electromagnetic scattering characteristics of the complex target.

The utility model relates to the technical field of data processing equipment, in particular to decision fusion algorithm acceleration operation equipment. According to the decision fusion algorithm acceleration operation equipment provided by the utility model, the technical problem of poor heat dissipation performance of the decision fusion algorithm acceleration operation equipment in the prior art is solved. The utility model discloses decision fusion algorithm acceleration operation equipment, which comprises a box body, the data processing assembly is arranged in the box body; the heat dissipation assembly is connected into the box body in a sliding mode, and the data processing assembly is installed on the heat dissipation assembly; by arranging the air cooler, the air inlet hole and the air outlet hole, the data processing assembly is cooled in a forced heat dissipation mode, and therefore the heat dissipation efficiency of the equipment is effectively improved. And the air cooler blows air flow with lower temperature to the data processing assembly, and the air flow with lower temperature exchanges heat with the data processing assembly and then is discharged in time through the air outlet holes, so that the heat dissipation efficiency of the equipment is greatly improved.

The application provides an independent data isolation system based on hardware-level physical isolation, comprising: a special security processing unit which is a multi-core heterogeneous system-level chip, and integrated with the following through a hardware security bus: a national encryption algorithm acceleration core for realizing encryption and decryption and operation processing of national encryption algorithms; a general control core for executing task scheduling, inter-core communication and external interface protocol processing; a security storage core for generating a unique physical key and supporting quantum key injection; an isolation control core for controlling physical isolation of data flow through a hardware mutex and a bus tag controller; and a fuse self-destruction module connected with the special security processing unit and controlled by the isolation control core, for quickly destroying key data and paths. The application has the beneficial effects of optimizing data security isolation, key protection and emergency response, effectively improving the overall security of the system and resisting more complex attacks.

The invention belongs to the technical field of cryptographic algorithm hardware implementation, and particularly discloses a post quantum cryptographic algorithm acceleration method and device based on an ASIP architecture, and the method comprises the steps: obtaining a program code of a Kyber algorithm; continuously executing the microcode instruction of the Kyber algorithm until the Kyber algorithm is completely executed; executing the microcode instruction of the Kyber algorithm, wherein the microcode instruction to be executed is obtained; analyzing the microcode instruction to be executed to obtain instruction analysis information; acquiring data of a source operand address as source data; on the basis of the operation code, an operation object is determined in hardware resources, input of the operation object is configured on the basis of the source data, and the hardware resources comprise an ALU and a Hash and sampling module; and configuring the data of the target operand address based on the data output by the operation object. According to the method and the device, the operation efficiency of the Kyber algorithm can be improved through hardware acceleration.

The invention relates to the technical field of integrated circuit design, and particularly discloses a device and method for accelerating high-precision ADC data operation, and the device comprises a bus which comprises an address bus and a data bus; the hardware algorithm accelerator comprises an address mapping logic module, an input and output mapping module, a register module and an algorithm acceleration core function module; the address mapping logic module is used for splitting an address access request from an address bus into a read-write access command of the register module and a parameter and operation command of the algorithm acceleration core function module; the register module includes a configuration register, a plurality of operand registers, and a configuration register. According to the method and the device, the address access request from the address bus is divided into two parts, meanwhile, calculation input and output are selected through address mapping, a calculation result can be directly imported into a newly-initiated calculation input end, read-write of a processor to an operand register can be reduced, and the calculation efficiency is improved.

The invention discloses an RAFT consensus algorithm acceleration system, which belongs to the technical field of block chain algorithm acceleration and comprises a CPU (central processing unit), a bus bridging system, a network communication module, an RAFT algorithm acceleration module, a memory and a network interface. The CPU is used for completing control of an acceleration system, scheduling data to the RAFT algorithm acceleration module and converting message data conforming to a message frame format; the bus bridging system is formed by combining a plurality of buses and is used for carrying out protocol conversion on data according to different data frame formats; the network communication module is used for communicating with the RAFT algorithm acceleration module; the RAFT algorithm acceleration module is used for maintaining nodes, performing voting and election initiating operations through the network communication module, and completing RAFT consensus acceleration; the memory is composed of a high-speed memory array. The implementation of the RAFT consensus algorithm in the block chain is completed, the time delay is greatly reduced, and the effect of optimizing the performance is achieved.

The application provides a Hawk algorithm acceleration method based on GPU multi-thread parallelism. The Hawk algorithm acceleration method based on GPU multi-thread parallelism comprises the following steps: (1) thread resource division and task mapping; (2) kernel fusion and throughput peak detection; (3) NTT / iNTT parallelization reconstruction and memory access optimization; (4) FFT / iFFT structured parallelization optimization and butterfly operator fusion. The application realizes a coarse-grained parallel butterfly operator execution mode without complex address calculation, without shared memory synchronization, and without competition between threads, greatly improving the throughput efficiency on the GPU; meanwhile, the application unifies the parallel execution framework in the forward and inverse transformations of FFT / NTT, wherein the inverse transformation only needs to use the corresponding inverse rotation factor and perform simple normalization processing at the end to complete the overall recovery.

The invention discloses a game and optimization-based robot online motion planning method, which comprises the following steps of: establishing a game model of a robot and a threat target, and outputting a game action instruction: acquiring current parameters of the robot and the threat target; defining a discrete action set according to the current parameter, and setting a game grade rule; judging the game grade, determining the robot game grade, and predicting the future trajectory of the threat target; based on a reward function, combining action space reduction and MCTS algorithm accelerated search, and selecting the first action of the optimal action sequence as a game action instruction; and optimizing the motion path on line according to a game result. According to the embodiment, the game theory and the optimization method are introduced, the motion path of the robot is adjusted in real time in the dynamic environment, and the task execution capacity and safety of the robot in the complex and dangerous environment can be effectively improved. The method not only considers the moving target of the robot, but also considers the strategy and dynamic change of the threatening target in the environment, and has higher adaptability and robustness.

The application provides a micro-isolation and differential encryption method and system based on industrial protocol awareness, a storage medium, and first acquires a first communication message to be analyzed by performing static filtering on original traffic through a preset port; then analyzes the message behavior mode using a time sequence feature analysis model to extract semantic tags containing function codes, data point addresses and data values; if the data values exceed a safety threshold, real-time blocking and warning are performed; otherwise, a dynamic communication strategy is generated based on the function codes and data point addresses; when a micro-isolation rule is triggered, the access permission of the equipment is dynamically limited; when a differential encryption rule is triggered, an encryption algorithm is selected according to the data sensitivity, and an algorithm acceleration module is called to execute. The application realizes micro-isolation through protocol semantic analysis to prevent illegal function code injection; adopts a differential encryption mechanism to reduce encryption overhead while meeting the real-time requirements of industrial scenarios; in addition, the encryption strength is dynamically adjusted in combination with channel quality to ensure operation reliability under extreme working conditions.

The present disclosure belongs to the technical field of neural network storage, and relates to a Winograd-based correlation algorithm accelerator storage method, which comprises the following steps: S1, acquiring the size of a correlation result matrix block and a real-time graph matrix block, and acquiring the size of a correlation result matrix and a real-time graph tensor and the channel parallelism of an acceleration unit; S2, storing a reference graph tensor block from off-chip storage to a first area of a reference tensor; S3, storing a real-time graph tensor block from off-chip storage to a real-time tensor cache; S4, reading data from the first area in the reference graph tensor cache and writing the last two rows of the read data to the first two rows in the second area in the reference graph tensor cache; S5, reading a tensor block from the reference tensor cache and prewriting the tensor block to a reference tensor register group; S6, writing a tensor block from the real-time graph tensor cache to a real-time graph tensor graph register; S7, moving the front column data of the reference register group to the rear column, and reading data from the reference tensor cache to the front column of the register group; and S8, writing a tensor register group after processing and calculation between different register groups.

The invention provides a Hawk algorithm acceleration method based on GPU (Graphics Processing Unit) multi-thread parallel. The GPU multi-thread parallel-based Hawk algorithm acceleration method comprises the following steps of (1) thread resource division and task mapping; (2) kernel fusion and throughput peak detection; (3) NTT / iNTT parallel reconstruction and memory access optimization are carried out; and (4) carrying out FFT / iFFT structured parallel optimization and butterfly operator fusion. According to the method, a coarse-grained parallel butterfly operator execution mode which does not need complex address calculation, does not need shared memory synchronization and does not compete among threads is realized, and the throughput efficiency on the GPU is greatly improved; meanwhile, a parallel execution framework is unified in forward and reverse transformation of the FFT / NTT, and overall recovery can be completed only by using a corresponding reverse twiddle factor and performing simple normalization processing at the tail end in the reverse transformation.

The invention discloses a high-speed parallel Viterbi decoder based on a CUDA (Compute Unified Device Architecture) and a decoding method. The decoder comprises an input cache module, a parallel data de-puncturing module, a parallel measurement calculation module, a backtracking path processing module and an output control module, and multi-level parallel processing is realized by utilizing a CUDA (Compute Unified Device Architecture) of a GPU (Graphics Processing Unit). The method comprises the following steps: segmenting a receiving sequence and then distributing the segmented receiving sequence to GPU thread blocks; rapidly reading a state transition matrix and an output matrix by adopting a pre-calculation table look-up strategy; adopting a parallel prefix scanning algorithm to accelerate state measurement calculation; and reducing the global memory access delay by using the shared memory. According to the invention, the performance bottleneck of the traditional serial Viterbi algorithm is broken through, on the premise of keeping the decoding precision, the throughput rate is obviously improved, the real-time processing of multi-code-rate and multi-code-stream convolutional codes is supported, and a remarkable acceleration effect can be obtained compared with CPU (Central Processing Unit) implementation. The method is especially suitable for high-throughput ACM scenes, such as 5G communication and satellite navigation, requiring real-time processing of multiple code streams and long constraint length convolutional codes.

The application relates to the technical field of integrated circuit design, and particularly discloses an apparatus and method for accelerating high-precision ADC data operation, which comprises a bus including an address bus and a data bus; a hardware algorithm accelerator including an address mapping logic module, an input-output mapping module, a register module and an algorithm acceleration core function module; the address mapping logic module is used for splitting an address access request from the address bus into two parts of a read-write access command of the register module and parameters and operation commands of the algorithm acceleration core function module; and the register module comprises a configuration register, a plurality of operand registers and the configuration register. According to the application, the address access request from the address bus is split into two parts, the calculation input and output are selected through address mapping, the calculation result can be directly introduced into a newly initiated calculation input end, the read-write of the operand register by the processor can be reduced, and the operation efficiency is improved.

The invention relates to the technical field of radar, and provides an FPGA-based pulse-space segmentation parallel BP algorithm acceleration system, which is realized based on a full-pipeline FPGA parallel BP imaging architecture, and comprises a communication module, a scene partitioning module, a pulse-space segmentation module and a BP algorithm full-pipeline processing module. The communication module is used for transmitting radar original data corresponding to a target scene to the FPGA onboard DDR3 memory from an upper computer through a PCIE interface in a zero-copy manner; the scene partitioning module is used for decomposing a target scene into a plurality of sub-blocks; the pulse-space segmentation module is used for decoupling the imaging pulse and sub-blocks decomposed from a target scene into a plurality of parallel calculation units; the BP algorithm full-pipeline processing module is used for realizing full-pipeline processing of a BP algorithm between pulses for each calculation unit in parallel; and the communication module is also used for carrying out data fusion on the BP imaging results of all the sub-blocks to obtain a BP imaging result of the target scene and uploading the BP imaging result to an upper computer.

The application discloses a kind of big model instruction security protection method, system and storage medium based on four-layer cooperative closed-loop protection mechanism, belong to artificial intelligence security and trusted computing field.The application is deployed non-intrusive independent protection layer between user input layer and big model inference execution layer, through instruction weight dynamic control, context integrity check, multi-modal public power subject credible verification, four big links cooperative linkage of security rule priority rigid locking, combined with shared semantic label library, dynamic threshold value synchronization mechanism and cross-layer abnormal feedback channel constructs whole-link closed-loop protection system.The application realizes high semantic weight content attenuation by instruction weight system, resists split bypass attack by context governance, guarantees public power identity credible by multi-modal double verification, realizes permission control and algorithm transparent by rule priority rigid locking, built-in global multi-jurisdiction compliance rule library, adapt to global regulatory requirements and have anti-black-box auditable characteristics.The application does not need to modify model bottom code, supports hardware-level isolation and national encryption algorithm acceleration, can be widely applied to government, finance, military industry and other high-end security scene, provides non-intrusive, global, high-security compliance protection solution for big model.

The invention belongs to the technical field of electronic information engineering, and particularly discloses a multi-core collaborative board-level signal processing system integrated with a storage and calculation integrated unit. The system comprises an FPGA, an ARM, an AI co-processing chip and a storage and calculation integrated chip. The FPGA is connected with the ARM, and the AI co-processing chip and the storage and calculation integrated core are respectively connected with the AMR and the FPGA; the FPGA is a core calculation engine, executes parallel data processing and algorithm acceleration, and responds to a complex signal processing task in real time; the AI co-processing chip processes a multi-thread task, executes neural network reasoning with complex calculation, processes mathematical operation and data analysis tasks and provides a calculation basis; the storage and calculation integrated chip directly carries out data processing in the storage unit; the embedded ARM processor is used for overall system control, task scheduling and resource management to ensure cooperative work of each unit. According to the scheme, the technical problem of processing performance improvement limitation caused by a single-core processor architecture is solved.

The application discloses a reinforced concrete structure improvement time domain synthetic aperture imaging fast algorithm, and steps are as follows: a reinforced concrete two-dimensional finite element simulation model is established, and a half diffusion angle is calculated; simulation testing is carried out on an ultrasonic probe in the reinforced concrete two-dimensional finite element simulation model, and full matrix data are formed; the reinforced concrete two-dimensional finite element simulation model is pixelated, and a diffusion angle factor is calculated; whether synthetic aperture processing is carried out is compared according to the half diffusion angle in step one and the diffusion angle factor in step three; and imaging processing is carried out on the full matrix data in step two according to a time domain synthetic aperture full focusing algorithm. The application has the beneficial effects that the application determines the diffusion angle factor of each pixel point to each transmission ultrasonic probe, the area outside the diffusion angle of the ultrasonic probe is not subjected to sound path calculation and amplitude superposition, the algorithm efficiency is greatly improved, meanwhile, imaging of the pseudo defects outside the diffusion angle is avoided. The smaller the diffusion angle is, the more the data quantity is, and the more obvious the algorithm acceleration effect is.

The invention relates to the technical field of network security, and discloses an SHA-2 algorithm acceleration method and system based on an RISC-V platform, and the method comprises the steps: compiling a compression function of an SHA-2 algorithm through an RISC-V assembly instruction set; performing data stream recombination and sliding window register mapping on a message expansion process of the SHA-2 algorithm, and mapping sequential access to a plurality of word arrays on the algorithm into cyclic coverage access to a plurality of registers or memory units; performing complete expansion on multiple rounds of iteration loops in the compression function, and statically and sequentially arranging calculation of each round of iteration; operation optimization of RISC-V instruction characteristics is carried out on the SHA-2 algorithm; and adjusting the calculation sequence in the sub-function and the lifetime of the intermediate result to reduce the number of temporary registers. According to the method, the compression function in the SHA-2 algorithm is optimized by using the RISC-V assembly instruction set, so that the operation efficiency is remarkably improved, the processing speed and performance are improved, and the optimization effect range is expanded; the memory access frequency is reduced, and the calculation efficiency is improved.

The method of single cycle super parallel comparison is designed by using FPGA, programmable logic or TCAM chip, which can complete the bitwise comparison between the key item and multiple table rows in a single logic cycle, output the address of the matched table row, and output the statistics data and position information of the same and different points. The algorithm supports table reconfiguration, same and different point processing, filter filtering, table mapping, one-dimensional array, two-dimensional data and multi-dimensional data comparison; the system includes a comparator array, reconfigurable logic, same and different point processor, mapping memory, filter, communication interface. It can form an independent comparison server and PCIE acceleration card. The method can speed up more than 10 9 orders of magnitude compared with the fastest CPU von Neumann computer comparison algorithm when comparing 10M table rows.

This disclosure provides a robot motion control method, device, electronic device, and storage medium, relating to the field of artificial intelligence technology. The method includes: initializing computational variables for the current control cycle according to preset MPPI control parameters; generating multiple control noise sequences based on the preset MPPI control parameters; generating actual control inputs based on the historical control sequences and the control noise sequences; and predicting the predicted state trajectory corresponding to each control noise sequence based on the actual control inputs; parallel computing of the sampling weights of each control noise sequence; updating the historical control sequences based on the sampling weights to obtain the target control sequence for the current control cycle; and generating control commands based on the target control sequence and sending them to the robot using a first computing resource. Parallel computing accelerates the MPPI algorithm, meeting the requirements of real-time motion control.

The invention discloses an equipment maintenance task optimization scheduling method based on DRO-CVaR. The method comprises the steps of theoretical basis, uncertainty analysis and modeling, and maintenance scheduling model and algorithm design based on DRO-CVaR. The theoretical basis comprises core elements of equipment maintenance task scheduling, a distributed robust optimization theory, a conditional value-at-risk theory and a DRO-CVaR fusion mechanism; the uncertainty analysis and modeling comprises uncertainty factor identification and classification, uncertainty modeling and an influence mechanism of uncertainty on scheduling; the maintenance scheduling model based on the DRO-CVaR comprises problem description, decision variables, a two-stage DRO-CVaR optimization model and model conversion; the algorithm design comprises an algorithm selection basis, an algorithm flow and an algorithm acceleration strategy; the method is suitable for equipment maintenance task scheduling and solves the problem of maintenance robust optimization.

The application belongs to the field of computers, and particularly relates to a convolution operation acceleration method, a circuit, a system, a device, a medium and an image processing method. The convolution operation acceleration method comprises the following steps: determining a channel sliding point-by-point convolution kernel and a corresponding sliding step length based on the number of channels; splitting the channel sliding point-by-point convolution kernel according to the sliding step length and a predetermined convolution acceleration algorithm; and accelerating the sliding convolution calculation of the split channel sliding point-by-point convolution kernel in the channel dimension by using the predetermined convolution acceleration algorithm. The convolution operation acceleration scheme provided by the application uses a channel sliding point-by-point convolution to replace a traditional ordinary convolution, and uses an acceleration algorithm to accelerate the sliding calculation of the channel sliding point-by-point convolution in the data channel, so that the energy efficiency ratio can be significantly improved.

This invention provides an artificial intelligence algorithm acceleration system and method for real-time junction temperature prediction of IGBTs, including a parameter acquisition module, an artificial intelligence algorithm acceleration module, and a host computer. The parameter acquisition module is used to acquire the saturated on-state collector-emitter voltage VCE(Sat), collector current IC, and substrate temperature TC during IGBT operation. The artificial intelligence algorithm acceleration module is based on a Zynq7000 series FPGA to build a SoC architecture, integrating a dual-core ARM Cortex-A9 processor and a dedicated neural network processor (NPU). The host computer is used to receive the junction temperature prediction results and raw acquired parameters transmitted by the artificial intelligence algorithm acceleration module, enabling real-time data display, historical data storage, junction temperature anomaly alarms, and model parameter calibration. This invention aims to solve the high latency, high communication cost, and data privacy issues of cloud computing solutions through collaborative optimization design of algorithms and hardware, while simultaneously overcoming the bottlenecks in computing power, energy efficiency, and accuracy of existing edge computing platforms.

A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.

The invention discloses a multi-sensor signal processing method based on an FPGA (Field Programmable Gate Array) common operator library, which constructs a three-layer software architecture of common operator library logic, algorithm acceleration control logic and application algorithm aiming at the problems of long dynamic reconfiguration time and low hardware resource utilization rate of the FPGA in the prior art. An FPGA dynamic partition is divided into a common operator library partition which is kept stable after being loaded and an algorithm acceleration control logic partition which can be quickly reconfigured, and a time-triggered scheduling mechanism is combined, so that only lightweight algorithm control logic needs to be dynamically configured during task switching; and thus, bottom-layer common computing resources can be reused by various heterogeneous algorithms such as radar pulse compression, infrared image filtering, integrated navigation and the like. According to the invention, the data volume and time of dynamic reconfiguration are reduced, microsecond-level switching is realized, the utilization rate of FPGA computing resources and the real-time performance of the system are improved, the flexibility and expandability of the system are enhanced, and the requirements of the unmanned system for high real-time performance, low power consumption and small size are met.

The application relates to the field of computer vision, and particularly discloses an unfolding multi-view unsupervised feature selection method for scene interaction, which comprises the following steps: S1, acquiring multi-view data output by a feature extraction module of a VR or AR device; S2, constructing a multi-view unsupervised feature selection model and determining an overall objective function; S3, realizing feature selection and de-outlier value based on low-dimensional representation and reconstruction; S4, constructing a high-order similarity graph and fusing to obtain a consensus high-order similarity graph; S5, updating model parameters by using an alternating iteration algorithm; S6, accelerating model operation by using a deep unfolding algorithm; and S7, screening features based on model output. The technical scheme provided by the application solves the multi-view, semantic mining and time delay problems of the existing method LSAG, effectively improves the VR or AR interaction precision and stability, and reduces the cost.

The invention relates to the field of computer vision, and particularly discloses an expanded multi-view unsupervised feature selection method for scene interaction, which comprises the following steps: S1, acquiring multi-view data output by VR (Virtual Reality) or AR (Augmented Reality) equipment through a feature extraction module; s2, constructing a multi-view unsupervised feature selection model and determining an overall objective function; s3, realizing feature selection and abnormal value removal based on low-dimensional representation and reconstruction; s4, constructing a high-order similarity graph and fusing the high-order similarity graph to obtain a consensus high-order similarity graph; s5, updating model parameters by adopting an alternating iteration algorithm; s6, accelerating model operation through a depth expansion algorithm; and S7, outputting screening features based on the model. According to the technical scheme provided by the invention, the problems of LSAG multi-view, semantic mining and time delay of the existing method are solved, the VR or AR interaction precision and stability are effectively improved, and the overhead is reduced.