64 results about "Algorithm acceleration" patented technology

The invention discloses a regional energy internet hierarchical control method considering flexible loads, which comprises the following steps of: constructing a global layer, dividing a regional energy internet into a plurality of electrically strongly coupled sub-regions by adopting a dynamic partitioning algorithm, aggregating equivalent adjustable capacities of the flexible loads in the sub-regions, and performing rolling optimization in an hour-level time scale, an improved Benders decomposition algorithm is adopted to accelerate solving and generate a partition-level power regulation instruction; constructing a regional layer, designing a thermodynamic-economic hybrid constraint model according to flexible load physical characteristics and user behavior elasticity, introducing a user comfort recovery time constraint and elastic electricity price response function, and decomposing an adjustment instruction issued by the global layer to each flexible load cluster in a minute-level time scale by adopting a parallel ADMM optimization algorithm; and constructing a load layer, constructing a millisecond-level adjustable load priority switching mechanism based on FPGA hardware acceleration and finite-state machine logic, calculating a load adjustable power boundary in real time, and dynamically adjusting a response queue in combination with system frequency deviation.

The invention provides a sparse approximate inverse Shenwei parallel preprocessing method and system for electromagnetic scattering, and relates to the technical field of processor parallel computing, and the method comprises the steps: carrying out the performance hotspot analysis of a sparse approximate inverse preprocessor in an electromagnetic scattering simulation process, and determining a hotspot function of the sparse approximate inverse preprocessor; extracting a sparse matrix vector multiplication operation of a hotspot function, performing master-slave core parallel calculation on the sparse matrix vector multiplication operation, migrating the sparse matrix vector multiplication operation to slave core calculation, and accelerating hotspot calculation by using a heterogeneous parallel sparse approximate inverse algorithm; parallel computing of master-slave core intensive numerical computing tasks is achieved; in the parallel computing process, the slave cores communicate with the master core in a direct memory access mode, and during the period, the master core is in a waiting state to ensure data consistency and communication synchronization until all the slave cores compute distributed tasks.

The present invention discloses a computing system based on a DSP chip array, comprising a DSP chip array and an array support unit connected by a hardware link; the DSP chip array comprises a plurality of DSP chips; the hardware link comprises a number of computing data flow channels equal to the number of the plurality of DSP chips and a number of loading and maintaining data flow channels equal to the number of the plurality of DSP chips; wherein each DSP chip in the DSP chip array is connected to the array support unit through a corresponding computing data flow channel and a loading and maintaining data flow channel; the array support unit comprises a loading and maintaining data flow channel for completing program burning and program booting, and a computing data flow channel for completing data sharing and algorithm acceleration between a plurality of DSP chips. The present invention supports parallel computing, greatly improves the computing power of module-level computing units, starts loading faster, and effectively reduces hardware costs; production and maintenance are simple, and development and design management are convenient.

The invention provides a micro-isolation and differential encryption method and system based on industrial protocol perception and a storage medium, and the method comprises the steps: firstly carrying out the static filtering of an original flow through a preset port, and obtaining a to-be-analyzed first communication message; analyzing a message behavior mode by using a time sequence feature analysis model, and extracting a semantic tag containing a function code, a data point address and a data value; if the data value exceeds the safety threshold value, real-time blocking and alarming are carried out; otherwise, generating a dynamic communication strategy based on the function code and the data point address; when the micro-isolation rule is triggered, dynamically limiting the access authority of the equipment; when the difference encryption rule is triggered, an encryption algorithm is selected according to the data sensitivity, and an algorithm acceleration module is called for execution. According to the method, micro-isolation is realized through protocol semantic analysis, and illegal function code injection is prevented; a differential encryption mechanism is adopted to reduce encryption overhead, and meanwhile, the real-time requirement of an industrial scene is met; in addition, encryption strength is dynamically adjusted in combination with channel quality, and operation reliability under extreme working conditions is guaranteed.

The embodiment of the invention provides a distribution network monitoring and controlling edge computing chip system and method based on multi-core heterogeneity, and belongs to the technical field of edge computing chips. The distribution network monitoring and controlling edge computing chip system based on multi-core heterogeneity comprises a main system and a subsystem, the main system comprises a plurality of processors and a power algorithm acceleration module; the subsystems comprise an MCU (Microprogrammed Control Unit) real-time subsystem, an Ethernet subsystem and an embedded security subsystem; the embedded security subsystem comprises a hardware algorithm module and an embedded security module; the main system is used for operating software applications and algorithm programs in the power distribution network; the MCU real-time subsystem is used for processing on-line tasks of electricity saving and voltage monitoring; the Ethernet subsystem is used for communicating with an external chip; and the embedded security subsystem is used for integrating an encryption algorithm. According to the method, the problem that tensor calculation kernels and floating point operation involved in part of specific power algorithms consume a large number of instruction periods during operation can be solved, and the stability of a distribution network system is facilitated.

The invention discloses a national cryptographic algorithm acceleration system supporting SM4-ZUC dual-core dynamic collaboration, and belongs to the technical field of information security and hardware acceleration. The system comprises an AXI read-write module, a configuration register module, an SM4 algorithm module and a ZUC algorithm module. The configuration register receives and distributes information such as a secret key, an initial vector and a mode through an APB interface; the AXI read-write module supports burst transmission and dynamic scheduling data read-write; the SM4 algorithm module supports three modes of GCM, CTR and ECB; and the ZUC algorithm module is compatible with ZUC-128 / 256. And the corresponding ZUC-128 / 256 and SM4 algorithms can be dynamically selected for operation by judging an encryption mode in the ZUC and SM4 algorithms. The system adopts a three-level assembly line architecture, space-time multiplexing of read-write data and encryption is realized, and throughput rate is improved.

The invention relates to a hardware acceleration calculation method and system based on a post quantum cryptography algorithm, and is applied to a chip. The method comprises the steps that hardware engines in a hardware acceleration engine array are adopted to execute post-quantum cryptographic algorithms of corresponding types, and the post-quantum cryptographic algorithms of the corresponding types comprise at least one of polynomial multiplication, multi-branch hash calculation, a tree structure and sparse polynomial operation; in the execution process, resources needed by the quantum cryptography algorithm after the hardware engines execute are dynamically adjusted based on the prediction mechanism and the fuzzy control logic, and the resources comprise at least one of the core number, the cache bandwidth, the voltage and the frequency. Namely, on one hand, a hardware engine is adopted to perform accelerated calculation on the post quantum cryptography algorithm, and on the other hand, resources required by calculation are dynamically adjusted during accelerated calculation, so that the resource utilization rate is increased, and calculation and energy efficiency regulation are optimized. Cooperative improvement of algorithm acceleration efficiency and performance can be realized.

The invention provides an FPGA (Field Programmable Gate Array)-based national secret algorithm acceleration device and electronic equipment, the device comprises a PCIE (Peripheral Component Interface Express) bus processing module, the PCIE bus processing module is used for completing data packaging and unpackaging work of each layer of a PCIE protocol, and the PCIE bus processing module further provides an AXI4 interface and supports AXIFULL and AXILITE protocols; the AXI bus processing module comprises an AXIFULL protocol processing module and an AXILITE protocol processing module; the storage module adopts a high-capacity full-dual-port BRAM (Border Random Access Memory) in the FPGA and is used for storing intermediate data and input and output data; the national cryptographic algorithm control module is responsible for managing and scheduling operation of three national cryptographic algorithm sub-modules SM2, SM3 and SM4 and processing data interaction between the sub-modules and the host; and the hardware acceleration unit comprises three independent hardware acceleration modules SM2, SM3 and SM4, each hardware acceleration module is responsible for a calculation task of a corresponding algorithm, and each hardware acceleration module comprises a control interface and a BRAM read-write interface for instruction and data interaction.

The invention provides a pinyin decoding input method, an embedded system and a storage medium. The method comprises the following steps: constructing a hierarchical code table index database; obtaining a pinyin character string input by a user, and determining a first index of the pinyin character string in the initial index layer according to the initial of the pinyin character string; calculating a Hash value of the pinyin character string by using a Hash algorithm, and obtaining a second index corresponding to the Hash value in a Hash table; searching in the pinyin data block according to the second index to obtain a pointer corresponding to the pinyin character string; and matching in the word data layer by using the pointer to obtain corresponding word data. According to the method, the memory pressure of the embedded system is reduced, the three-layer index structure of the hierarchical code table index database is utilized, and the optimized hash search algorithm is adopted to accelerate data access, so that high-precision matching and quick positioning are realized in an embedded environment.

The invention relates to the technical field of national cryptographic algorithm acceleration, and discloses a national cryptographic algorithm acceleration system based on a Numba just-in-time compiling technology. The numerical calculation mode reconstruction module is used for performing numerical calculation mode reconstruction on SM2 elliptic curve scalar multiplication, SM3 message extension round function, SM4 nonlinear transformation and ZUC flow generation logic contained in the national cryptographic algorithm core calculation module by utilizing an LLVM compiling chain of Numba, and converting an interpretively executed Python code into an optimized machine code adaptive to hardware; key function compiling acceleration is achieved through a (at) njit decorator, hot spot operation is dynamically recognized through compiling scheduling, and a differential instruction optimization strategy is loaded; the platform shows multiple technical advantages: on the development efficiency level, by presetting a standardized acceleration module library and an automatic compiling tool chain, the integration complexity of a national cryptographic algorithm is greatly reduced; in the aspect of operation performance, the compilation optimization depth is better than that of a general interpreter acceleration scheme; in the aspect of safety controllability, the mathematical theory basis of the national cryptographic algorithm is completely reserved, and hidden risks possibly introduced by black box type hardware acceleration are avoided.

The invention relates to a Miller-Rabin algorithm acceleration method and device based on software and hardware fusion. When the Miller-Rabin algorithm is executed, to-be-verified target data is loaded to the data splitting hardware unit, the data splitting hardware unit is used for performing data splitting on the target data, a decomposition array matched with the target data is generated after data splitting, modular exponentiation operation object data is generated based on the decomposition array, and the modular exponentiation operation object data is sent to the data splitting hardware unit. The modular exponentiation hardware unit is used for executing modular exponentiation on the modular exponentiation object data, the logic judgment unit is used for carrying out logic judgment on the first modular exponentiation result value and the second modular exponentiation result value, and the modular exponentiation object data is obtained based on the corresponding logic judgment states of the first modular exponentiation result value and the second modular exponentiation result value. And generating a data verification state corresponding to the target data. According to the method, the efficiency of large-batch prime number judgment by utilizing the Miller-Robin algorithm can be effectively improved, the computing power requirement for operating the Miller-Robin algorithm is reduced, and the prime number judgment and generation efficiency is improved.

The invention discloses a target scattering characteristic efficient solving method of a multilayer fast multi-pole collaborative principal component analysis compression algorithm. The method comprises the following steps: dividing a target model by using a hybrid tree, changing an impedance matrix into a laminated matrix by binary tree grouping, and dividing a target into a near field and a far field by octree grouping; a multi-layer fast multi-pole algorithm acceleration principal component analysis compression algorithm is adopted to compress the low-rank impedance matrix; performing nearest layer-by-layer inversion on the impedance matrix according to an SMW formula; and finally, current is obtained through matrix vector multiplication of a series of inverse matrixes and a right vector, and target scattering characteristics are solved. The method achieves the solving of the electromagnetic scattering characteristics of the complex target, and can improve the calculation efficiency of the analysis of the electromagnetic scattering characteristics of the complex target.

The utility model relates to the technical field of data processing equipment, in particular to decision fusion algorithm acceleration operation equipment. According to the decision fusion algorithm acceleration operation equipment provided by the utility model, the technical problem of poor heat dissipation performance of the decision fusion algorithm acceleration operation equipment in the prior art is solved. The utility model discloses decision fusion algorithm acceleration operation equipment, which comprises a box body, the data processing assembly is arranged in the box body; the heat dissipation assembly is connected into the box body in a sliding mode, and the data processing assembly is installed on the heat dissipation assembly; by arranging the air cooler, the air inlet hole and the air outlet hole, the data processing assembly is cooled in a forced heat dissipation mode, and therefore the heat dissipation efficiency of the equipment is effectively improved. And the air cooler blows air flow with lower temperature to the data processing assembly, and the air flow with lower temperature exchanges heat with the data processing assembly and then is discharged in time through the air outlet holes, so that the heat dissipation efficiency of the equipment is greatly improved.

The invention discloses a bit serial computing transmission structure for high-speed data processing in a chip interconnection system, and belongs to the technical field of semiconductor integrated circuits. The architecture mainly integrates two bit serial multiply-accumulate modules, a bit serial adder and a high-speed voltage mode logic (VML) physical interface, wherein the VML interface mainly comprises a driver, an equalizer, a comparator, a bias current source and an RS trigger. The structure realizes direct connection of calculation and data transmission without a parallel-serial conversion circuit or a serial-parallel conversion circuit, and has the potential of reducing delay and energy consumption. The extensible chip interconnection component may be the basis of a modularized algorithm accelerator in the future, and different accelerator hardware structures are formed by expanding or reconstructing the basic component, so that different algorithms are adapted, and the reconfigurability of the system is improved.

The present invention discloses a method for determining the optimal power flow of main-distribution coordination based on adaptive weighted Anderson acceleration, the method comprising: first setting the initial value of the boundary condition of the distribution network sub-problem and various iteration parameters; then the distribution network control center solves the main network boundary condition according to the distribution network boundary condition, and the main network control center updates the distribution network boundary condition according to the main network boundary condition; then judging whether the algorithm converges and terminates; finally checking whether the upper limit of the number of iterations is reached, if the upper limit of the number of iterations is reached, the algorithm terminates, if not, checking whether the upper limit of the number of inner iterations is reached, determining whether to perform algorithm acceleration or continue iteration, for the iteration that needs algorithm acceleration, correcting and updating the outer layer iteration result of this time by weighted Anderson acceleration, as the initial value of the next outer layer iteration, accelerating the update of the distribution network boundary condition. The present invention improves the convergence efficiency and convergence performance of the heterogeneous decomposition method, improves the stability of the algorithm, and has good engineering application prospects.

The invention relates to a biped robot nonlinear model predictive controller FPGA heterogeneous acceleration method, which comprises the following steps: establishing an NMPC model according to a biped robot dynamic model, iteratively solving a quadratic programming form of the NMPC model, and completing a single iteration process: solving by a primitive-dual interior point method and solving a symmetric linear equation set by a minres algorithm; the process of solving the solution of the linear equation set constructed by using the KKT condition based on the quadratic programming form through the primitive-dual interior point method is configured to be executed by a CPU; the process of solving the symmetric linear equation set by the minres algorithm is configured to be executed by the FPGA. According to different calculation characteristics of a solution operator in a biped robot NMPC model, a logic reusable minres algorithm in the solution process is deployed to an FPGA calculation platform, and nonlinear operation is deployed to a CPU for implementation, so that the calculation power characteristic of a heterogeneous chip is fully utilized. According to the method, robot dynamics modeling, an efficient optimization solution algorithm and appropriate computing power resource allocation are considered, and the acceleration effect and verification of the algorithm can be ensured.

The application provides an independent data isolation system based on hardware-level physical isolation, comprising: a special security processing unit which is a multi-core heterogeneous system-level chip, and integrated with the following through a hardware security bus: a national encryption algorithm acceleration core for realizing encryption and decryption and operation processing of national encryption algorithms; a general control core for executing task scheduling, inter-core communication and external interface protocol processing; a security storage core for generating a unique physical key and supporting quantum key injection; an isolation control core for controlling physical isolation of data flow through a hardware mutex and a bus tag controller; and a fuse self-destruction module connected with the special security processing unit and controlled by the isolation control core, for quickly destroying key data and paths. The application has the beneficial effects of optimizing data security isolation, key protection and emergency response, effectively improving the overall security of the system and resisting more complex attacks.

The invention belongs to the technical field of cryptographic algorithm hardware implementation, and particularly discloses a post quantum cryptographic algorithm acceleration method and device based on an ASIP architecture, and the method comprises the steps: obtaining a program code of a Kyber algorithm; continuously executing the microcode instruction of the Kyber algorithm until the Kyber algorithm is completely executed; executing the microcode instruction of the Kyber algorithm, wherein the microcode instruction to be executed is obtained; analyzing the microcode instruction to be executed to obtain instruction analysis information; acquiring data of a source operand address as source data; on the basis of the operation code, an operation object is determined in hardware resources, input of the operation object is configured on the basis of the source data, and the hardware resources comprise an ALU and a Hash and sampling module; and configuring the data of the target operand address based on the data output by the operation object. According to the method and the device, the operation efficiency of the Kyber algorithm can be improved through hardware acceleration.

The present invention discloses a hardware architecture and method for algorithm acceleration. The hardware architecture includes: a register array for storing control parameters, fixed parameters, and operation results; a controller for controlling the operation rules of an arithmetic unit, and for controlling the arithmetic unit to read values from the register array and values from an accessor; an arithmetic unit for performing corresponding multiplication, addition, subtraction, and mixed operations according to the operation rules given by the controller; and an accessor for storing operation data. In this way, by configuring the controller and the register array, multiplication-accumulation of different lengths, distances between feature points, and summation operations, etc. can be completed, accelerating various algorithms in fingerprint algorithm feature extraction and matching; by setting two SRAMs, the performance of the fingerprint algorithm can be improved without increasing the overall chip area. This design has flexible configuration, strong versatility, and small occupied area, and can accelerate different fingerprint algorithms.

The invention relates to the technical field of integrated circuit design, and particularly discloses a device and method for accelerating high-precision ADC data operation, and the device comprises a bus which comprises an address bus and a data bus; the hardware algorithm accelerator comprises an address mapping logic module, an input and output mapping module, a register module and an algorithm acceleration core function module; the address mapping logic module is used for splitting an address access request from an address bus into a read-write access command of the register module and a parameter and operation command of the algorithm acceleration core function module; the register module includes a configuration register, a plurality of operand registers, and a configuration register. According to the method and the device, the address access request from the address bus is divided into two parts, meanwhile, calculation input and output are selected through address mapping, a calculation result can be directly imported into a newly-initiated calculation input end, read-write of a processor to an operand register can be reduced, and the calculation efficiency is improved.

The invention provides a universal interface algorithm acceleration device and an acceleration method. The universal interface algorithm acceleration device comprises a configuration unit used for performing information configuration on a to-be-executed software task; the algorithm scheduling acceleration unit is used for reading a software task, performing data analysis on the software task to obtain configuration information and data required by an algorithm, and writing the configuration information and the data into the algorithm module; the SPIRNG unit is used for acquiring a random number from an external random source according to a task requirement and writing the random number into the algorithm module; after algorithm calculation is finished, the algorithm scheduling acceleration unit obtains an algorithm end mark and reads an algorithm result, the algorithm result is placed at a result output address specified by the configuration unit, an algorithm state is updated, and the updated algorithm state is transmitted to the configuration unit; the configuration unit schedules the updated task state and the related address of the acceleration unit according to the algorithm so as to execute the task. According to the method, extra time except algorithm calculation can be reduced, and the actual application efficiency of the algorithm is improved.

The invention discloses an RAFT consensus algorithm acceleration system, which belongs to the technical field of block chain algorithm acceleration and comprises a CPU (central processing unit), a bus bridging system, a network communication module, an RAFT algorithm acceleration module, a memory and a network interface. The CPU is used for completing control of an acceleration system, scheduling data to the RAFT algorithm acceleration module and converting message data conforming to a message frame format; the bus bridging system is formed by combining a plurality of buses and is used for carrying out protocol conversion on data according to different data frame formats; the network communication module is used for communicating with the RAFT algorithm acceleration module; the RAFT algorithm acceleration module is used for maintaining nodes, performing voting and election initiating operations through the network communication module, and completing RAFT consensus acceleration; the memory is composed of a high-speed memory array. The implementation of the RAFT consensus algorithm in the block chain is completed, the time delay is greatly reduced, and the effect of optimizing the performance is achieved.

The invention belongs to the field of chip design, and provides a system-on-chip, a heterogeneous computing acceleration platform and a data processing method in order to improve the computing speed problem of an existing artificial intelligence edge computing system-on-chip. Wherein the system on chip comprises an ARM processor core, a programmable logic area and an artificial intelligence engine; a deep learning processor is deployed on the artificial intelligence engine; at least one target deep learning model is loaded in the deep learning processor; the ARM processor core controls a target deep learning model in the deep learning processor to run by setting a driving program; at least one algorithm acceleration kernel is integrated in the programmable logic area; each algorithm acceleration kernel is independently designed according to a set function and then transplanted to the programmable logic area, and a data processing assembly line with independent functions is formed according to a preset requirement. Data pre-processing and post-processing of artificial intelligence reasoning can be deployed on the same chip to achieve hardware-level full-process acceleration.

The application provides a Hawk algorithm acceleration method based on GPU multi-thread parallelism. The Hawk algorithm acceleration method based on GPU multi-thread parallelism comprises the following steps: (1) thread resource division and task mapping; (2) kernel fusion and throughput peak detection; (3) NTT / iNTT parallelization reconstruction and memory access optimization; (4) FFT / iFFT structured parallelization optimization and butterfly operator fusion. The application realizes a coarse-grained parallel butterfly operator execution mode without complex address calculation, without shared memory synchronization, and without competition between threads, greatly improving the throughput efficiency on the GPU; meanwhile, the application unifies the parallel execution framework in the forward and inverse transformations of FFT / NTT, wherein the inverse transformation only needs to use the corresponding inverse rotation factor and perform simple normalization processing at the end to complete the overall recovery.

The present application relates to the field of depth camera recognition, and in particular to a method and system for obtaining depth values ​​based on a dynamic binarization algorithm, obtaining an 8-bit grayscale image corresponding to a reference image and a point to be tested, converting the reference image and the 8-bit grayscale image corresponding to the point to be tested into a 1-bit image through a local dynamic binarization model, and obtaining a corresponding 1-bit binarization value, obtaining matching cost values ​​of different disparities of the point to be tested through a matching cost model, selecting the minimum matching cost value as the preliminary disparity of the point to be tested; performing denoising and smoothing on the preliminary disparity to obtain the disparity of the point to be tested; and mapping the disparity of the point to be tested to the depth value of the point to be tested. The present application provides a method and system for obtaining depth values ​​based on a dynamic binarization algorithm, which can reduce the amount of calculation in the depth algorithm, thereby reducing the demand for the number of logic gates, and improving the area efficiency and power efficiency of the depth algorithm accelerator while providing a high-quality depth map.

The invention provides an encryption and decryption method, an SM4 algorithm accelerator and a BMC chip, and relates to the technical field of computers. The method is applied to a target SM4 algorithm accelerator, and comprises the following steps: randomly selecting at least one stage of target assembly line from multiple stages of assembly lines corresponding to an encryption and decryption module of the target SM4 algorithm accelerator; performing XOR operation on the round key corresponding to the target assembly line and at least one piece of data in target input corresponding to the target assembly line to obtain a first processing result; performing nonlinear transformation on the first processing result based on an S box in the target assembly line to obtain a second processing result; performing linear transformation on the second processing result to obtain a third processing result; performing XOR operation on the third processing result and data except at least one piece of data in the target input to obtain a fourth processing result; and obtaining target output corresponding to the target pipeline based on the fourth processing result and the at least one piece of data.

The invention discloses a game and optimization-based robot online motion planning method, which comprises the following steps of: establishing a game model of a robot and a threat target, and outputting a game action instruction: acquiring current parameters of the robot and the threat target; defining a discrete action set according to the current parameter, and setting a game grade rule; judging the game grade, determining the robot game grade, and predicting the future trajectory of the threat target; based on a reward function, combining action space reduction and MCTS algorithm accelerated search, and selecting the first action of the optimal action sequence as a game action instruction; and optimizing the motion path on line according to a game result. According to the embodiment, the game theory and the optimization method are introduced, the motion path of the robot is adjusted in real time in the dynamic environment, and the task execution capacity and safety of the robot in the complex and dangerous environment can be effectively improved. The method not only considers the moving target of the robot, but also considers the strategy and dynamic change of the threatening target in the environment, and has higher adaptability and robustness.

The application provides a micro-isolation and differential encryption method and system based on industrial protocol awareness, a storage medium, and first acquires a first communication message to be analyzed by performing static filtering on original traffic through a preset port; then analyzes the message behavior mode using a time sequence feature analysis model to extract semantic tags containing function codes, data point addresses and data values; if the data values exceed a safety threshold, real-time blocking and warning are performed; otherwise, a dynamic communication strategy is generated based on the function codes and data point addresses; when a micro-isolation rule is triggered, the access permission of the equipment is dynamically limited; when a differential encryption rule is triggered, an encryption algorithm is selected according to the data sensitivity, and an algorithm acceleration module is called to execute. The application realizes micro-isolation through protocol semantic analysis to prevent illegal function code injection; adopts a differential encryption mechanism to reduce encryption overhead while meeting the real-time requirements of industrial scenarios; in addition, the encryption strength is dynamically adjusted in combination with channel quality to ensure operation reliability under extreme working conditions.

The present disclosure belongs to the technical field of neural network storage, and relates to a Winograd-based correlation algorithm accelerator storage method, which comprises the following steps: S1, acquiring the size of a correlation result matrix block and a real-time graph matrix block, and acquiring the size of a correlation result matrix and a real-time graph tensor and the channel parallelism of an acceleration unit; S2, storing a reference graph tensor block from off-chip storage to a first area of a reference tensor; S3, storing a real-time graph tensor block from off-chip storage to a real-time tensor cache; S4, reading data from the first area in the reference graph tensor cache and writing the last two rows of the read data to the first two rows in the second area in the reference graph tensor cache; S5, reading a tensor block from the reference tensor cache and prewriting the tensor block to a reference tensor register group; S6, writing a tensor block from the real-time graph tensor cache to a real-time graph tensor graph register; S7, moving the front column data of the reference register group to the rear column, and reading data from the reference tensor cache to the front column of the register group; and S8, writing a tensor register group after processing and calculation between different register groups.