41 results about "Memory copy" patented technology

The invention discloses a data transmission optimization method and system in hybrid deployment of a real-time system and a non-real-time system based on Jailhouse, belongs to the technical field of data transmission, and solves the problems of low data transmission efficiency, high copy overhead, lack of universality of interfaces and the like in an existing system. Comprising the steps that a hybrid deployment platform including a real-time system and a non-real-time system is built on a multi-core processor platform, and the hybrid deployment platform runs in an isolation environment of a Jailhouse partition manager; building an abstract transmission interface layer as a unified channel for accessing a shared memory by a real-time system and a non-real-time system; establishing a plurality of shared memory channels in the abstract transmission interface layer and scheduling according to the priority of tasks; establishing a data transmission path, and compressing a memory copy operation into one time by adopting a memory mapping multiplexing technology and a DMA (Direct Memory Access) collaboration mechanism; and a cache consistency maintenance technology is adopted, so that the data consistency is ensured, and the optimization of data transmission is completed. The method is suitable for application scenes such as industrial automation, intelligent connected automobiles and edge calculation.

A computer-implemented system for routing artificial intelligence (AI) queries. The system utilizes a zero-copy data pipeline, which processes prompts in memory-mapped buffers to eliminate at least one memory copy operation, thereby reducing latency relative to conventional serialization pipelines. The system continuously verifies AI provider compliance by injecting synthetic prompts containing invisible, Ed25519-signed Unicode watermarks. Algorithmic bias is detected by generating counterfactual “digital twin” prompts and applying Fisher exact statistical testing.Routing decisions for multi-tier autonomous systems are governed by safety-level requirements (ASIL-D, ASIL-B, QM) and may be constrained by external routing directives received via a meta-identifier. A hash-chained manifest, cryptographically signed using Ed25519 and consumed by downstream gateways, is generated for each routing decision, with its Merkle root asynchronously anchored to a blockchain to create a tamper-evident audit trail for regulatory compliance.

The invention discloses an accelerator card resource sharing system, method and device and electronic equipment, and relates to the technical field of accelerator cards, the system comprises an address mapping module and a memory copying engine module, the address mapping module is used for receiving an access request of an accelerator card video memory of a source host, querying a mapping relation of virtual addresses in a dynamic mapping table and copying the virtual addresses to the source host; the memory copy engine module generates target label information for identifying a target data packet transmitted across hosts, the dynamic mapping table reflects a mapping relation between a source host virtual address and a target host accelerator card physical address, and the memory copy engine module copies the target data packet according to the transmission priority and sequence information of the target data packet contained in the target label information. And executing cross-host data transmission to ensure that the data is efficiently transmitted to an accelerator card video memory of a target host. According to the embodiment of the invention, the problems of relatively high delay and insufficient flexibility in coping with the complex demand of acceleration card cluster sharing in the prior art are effectively solved.

The invention relates to the technical field of artificial intelligence, and provides a fusion operator execution method, electronic equipment, a storage medium and a program product, and the method comprises the steps: determining a plurality of to-be-fused target operators; according to the tensors of the multiple target operators, a pseudo address mapping table is generated, and the pseudo address mapping table is used for recording the mapping relation between the actual memory addresses of the tensors and pseudo addresses; operator fusion is carried out on the multiple target operators, a fusion operator is obtained, and the memory address of the tensor of the fusion operator is a continuous pseudo address; and executing the fusion operator, converting the pseudo address into an actual memory address according to the pseudo address mapping table in the execution process, and accessing data of the tensor according to the actual memory address. According to the method, a large amount of extra memory copy overhead caused by physical movement and rearrangement of the original tensor in a traditional operator fusion scheme is avoided, and the computing resource utilization rate and the execution efficiency are remarkably improved.

An opportunistic approach is described to accelerate certain memory copy operations to be performed by a computing engine by executing instructions. An instruction for a memory copy operation can be identified that has a first data type with a smaller number of bits per data element than supported by the computing engine to perform the copy operation. The instruction can be replaced with another instruction that has a second data type with a higher number of bits per data element based on the alignment of the memory addresses for the copy operation and the total number of data elements to be copied. The second data type may not only accelerate the copy operation but also provide better utilization of the underlying hardware of the computing engine.

The invention discloses a memory copying method, a memory copying device, a chip and electronic equipment, and belongs to the technical field of computers. The memory copying method comprises the steps that after a direct memory access DMA request submitted by a user mode application program is received, a physical page corresponding to the DMA request is locked; determining a topological relation between the physical page and the DMA channel; determining a target DMA channel according to the topological relation and the idle state of the DMA channel; mapping the locked physical page to an addressing space of the target DMA channel to obtain a mapping relationship between an address of the locked physical page and an address in the addressing space; and copying the data in the locked physical page through the target DMA channel based on the mapping relationship. Through the topological relation between the physical pages and the DMA channels and the idle states of the DMA channels, the DMA channels in the DMA channel resource pool can be adaptively and dynamically allocated, and the data copying efficiency can be improved.

This invention discloses a data transmission method, device, storage medium, and computer program product, relating to the field of computer technology. The method includes: determining a time interval within which a data transmission request needs to wait for processing by a shared memory device; determining the memory copy processing time for directly executing the data transmission request between different hosts; if the memory copy processing time is greater than the maximum value of the time interval and the shared memory device does not exhibit any transmission anomalies, then data transmission is performed between different hosts via the shared memory device; if the memory copy processing time is less than the minimum value of the time interval or the shared memory device exhibits a transmission anomaly, then data transmission is performed between different hosts via a server. This invention adds redundant transmission paths when a shared memory device exhibits a transmission anomaly, ensuring data reachability while maintaining low-latency transmission, thereby improving the reliability and overall efficiency of data transmission between hosts.

The invention relates to an application starting method and device, equipment, a storage medium and a vehicle. According to the method and the device, the file access data is acquired according to the accessed file when the application program is subjected to cold start for the first time, and the file prefetching list is further generated according to the file access data, so that a cold start process does not need to be performed again in a subsequent application program start process; according to the application program starting method and device, starting can be achieved only by prefetching the corresponding file data according to the file prefetching list, actions such as memory copying in the cold starting process are omitted, time consumed in the application program starting process is effectively saved, and the starting speed of the application program is substantially optimized.

A physical host includes a memory, a first buffer, a second buffer, a third buffer and a processor. The first buffer stores a log regarding dirty pages. The second buffer stores a dirty bitmap, where the dirty bitmap is written into the second buffer according to the log read from the first buffer. The third buffer stores the dirty bitmap. The processor obtains the current memory address to be migrated and a destination memory address, and marks a page table corresponding to the memory address to be migrated as dirty pages and writes the log marked as the dirty pages into the first buffer when the memory address to be migrated is written. The processor includes a memory copy engine for reading the dirty bitmap from the third buffer, and copying the content corresponding to the dirty pages to the destination memory according to the dirty bitmap.

A direct memory access (DMA) controller issuing memory copy operations on behalf of a shader at a parallel processor stops issuing copy operations upon a context switch at the shader for a wave. The DMA controller or a trap handler associated with the shader saves the incomplete copy operations to a region of global memory, from which the incomplete operations are restored upon a context resume for the wave.

The application provides a kind of multi-hardware supported deep learning model compiling method and compiler, comprising: obtaining the computational graph of the deep learning model to be compiled and the target device information;The target device information is converted into hardware attribute intermediate form based on the preset hardware model, the linear operation intermediate form is obtained based on the basic operation of deep learning model, the tensor shape intermediate form is obtained based on the tensor of deep learning model;Based on the tensor and the tensor shape intermediate form, obtain the memory intermediate form, and use the heterogeneous memory transmission folding method to optimize memory copy behavior;Based on the obtained linear operation intermediate form, obtain the loop intermediate form, use the method of fusion, stacking and vectorization to optimize the loop in the loop intermediate form, and convert into vector intermediate form, obtain the heterogeneous device data operation rule intermediate form based on the preset calculation model;Based on the plurality of intermediate forms obtained in the foregoing, obtain the executable code that can be inferred on the target device.

The application discloses a data processing method and system in a remote procedure call, and the method comprises the following steps: one party of the remote procedure call acquires to-be-transmitted data, wherein the to-be-transmitted data comprises at least one field; the one party acquires serialized data and data in a predetermined field, wherein the serialized data is obtained by serializing data in other fields of the to-be-transmitted data, the other fields are fields of the to-be-transmitted data except the predetermined field, the predetermined field is a field satisfying a predetermined condition, and the data in the predetermined field has not been subjected to serialization processing; and the one party sends the serialized data and the data in the predetermined field to another party of the remote procedure call. The application solves the problem that the RPC cannot meet the requirements due to the large serialization processing overhead in the RPC process, thereby saving the memory copy overhead in the serialization processing and improving the processing efficiency of the RPC.

In some implementations, an emulation system may store a set of data to a first memory copy location of an emulated environment that is associated with a first virtual host system. The emulation system may copy the set of data from the first memory copy location to a shared memory location of the emulated environment. The emulation system may copy the set of data from the shared memory location to a second memory copy location of the emulated environment that is associated with a second virtual host system. The emulation system may load the set of data from the second memory copy location.

The invention discloses a data processing method and device, computer equipment, a storage medium and a program product, and relates to the technical field of computers. The method comprises the following steps: in response to a data writing request of a producer, writing to-be-written stream data provided by the producer into a preset data stream slice space according to a current writing address, and updating the current writing address according to the to-be-written stream data; and in response to a data reading request of a consumer, reading target stream data from the preset data stream slice space according to the current reading address, providing the target stream data to the consumer, and updating the current reading address according to the target stream data. A producer and a consumer intuitively operate the same memory space based on respective operation addresses, additional memory copying operation of data between a user level and a buffer area is not needed in the process, the problem that resources such as space and time are wasted due to frequent memory copying in an existing memory buffer algorithm is solved, and the memory copying efficiency is improved. And the read-write speed of the cache data is increased.

In some implementations, an emulation system may store a set of data to a first memory copy location of an emulated environment that is associated with a first virtual host system. The emulation system may copy the set of data from the first memory copy location to a shared memory location of the emulated environment. The emulation system may copy the set of data from the shared memory location to a second memory copy location of the emulated environment that is associated with a second virtual host system. The emulation system may load the set of data from the second memory copy location.

This invention discloses a method for accelerating numerical computation software based on CPU-GPU collaboration. The method divides the program into basic blocks and uses a code analysis module to predict the runtime information of these basic blocks, including whether they are computationally intensive tasks, whether they are easily parallelized, and whether the memory copy time of the computation task is less than the CPU execution time. Based on the analysis results, basic blocks that meet the above conditions are marked as GPU modules, and the rest are CPU modules. GPU modules are compiled into GPU code for execution on the fly. If CPU modules have hotspot code, they are compiled into machine code on the fly for execution; otherwise, they are interpreted. This method employs a CPU-GPU collaborative just-in-time compilation approach, fully utilizing CPU and GPU computing resources, achieving higher execution efficiency than CPU or GPU execution alone. It also leverages the advantages of just-in-time compilation of interpreted languages, significantly improving the performance of numerical computation software.

The embodiment of the invention relates to the technical field of communication, and discloses a data transmission method and system based on a shared buffer pool, and the data transmission method based on the shared buffer pool comprises the steps: constructing the shared buffer pool with a physical staggered mapping structure, and enabling inline data and an SGE descriptor to exist in the same physical memory area, a mode selection domain is set to store a transmission mode of application data, the transmission mode comprises an inline mode and an SGE mode, and a logical address domain is set to store a logical address, pointing to a shared buffer pool, of a work queue element, so that a physical address can be calculated by utilizing the logical address; the physical address is used for reading the application data in the shared buffer pool, memory copy delay caused by switching of different transmission modes can be eliminated, and then the utilization rate of memory resources is increased.

The present application relates to a kind of star-ground collaborative carbon sink monitoring methods based on multi-core heterogeneous acceleration, including acquisition ground multi-source time series data and satellite multispectral image form star-ground data;Star-ground data is preprocessed, and C-Frame tensor with self-description frame header is generated;Collaborative flow self-adaptive bridge C-FAB framework is established, for C-Frame tensor is directly mapped to edge ai equipment, avoid traditional multiple memory copy;DS-LUE model is established in edge ai equipment, and the carbon sink result of the calculation area is generated by DS-LUE model, by fusing satellite multispectral image and ground humidity, soil and vegetation sensing data, in low power consumption, high throughput edge computing environment, fast, accurate carbon sink estimation and dynamic monitoring are realized, and support complex remote sensing processing task in different computing resources collaborative operation, significantly improve the performance and adaptability of remote sensing data processing.

This invention discloses a virtualized log export method, apparatus, terminal, and storage medium, belonging to the field of logging. The method includes: allocating contiguous memory at the EL2 layer as a buffer and initializing a start timestamp; collecting data when an event occurs, determining the mask position, writing the event type and description to a bitmap, writing the relative duration to a preset position, and writing process and CPU information at a fixed length to generate a fixed-length binary event record; when aggregation conditions are met, aggregating the valid data in the buffer into a composite event information structure via memory copy to form a package to be exported; writing the structure to a memory-mapped window area accessible only by EL1, allowing EL1 to read without trapping into EL2; when the window changes from empty to non-empty, EL2 sends only one notification, allowing EL1 to continue reading without additional overhead. This reduces the overhead of cross-exception level notifications and traps, achieving efficient and secure structured log transmission.

Disclosed in the present invention are a CPU capable of quickly processing a memory copy instruction, and a method using same. The CPU comprises: an instruction decoder, a general-purpose register, a memory copy controller, a bus interface, a buffer, an adder, and a comparator. The memory copy controller comprises a state machine, and the state machine comprises an idle state, a read state, and a write state, wherein in the idle state, the memory copy controller waits to receive a valid memory copy instruction; in the read state, the memory copy controller reads data of a source address by means of the bus interface, and temporarily stores the data in the buffer; and in the write state, the memory copy controller writes the data, which is temporarily stored in the buffer, to a destination address by means of the bus interface. The adder is used for updating an address. The comparator is used for determining the end of copying. The present invention can maximize the utilization of a memory bandwidth to greatly improve the memory copy efficiency, can support an arbitrary alignment mode and support interruption, can reduce the power consumption of instruction fetching, and has a simple structure.

The application discloses a kind of hardware perception type vector quantization calculation fusion acceleration instruction parallel processing system and method.For the memory bandwidth bottleneck problem of asymmetric distance calculation in large-scale vector retrieval, the application is inside processor register, 8-bit quantization encoding is loaded, zero extension to 32-bit floating point precision, affine correction based on quantization offset and scale factor, and distance accumulation operation for query vector are fused into single instruction multiple data stream driven in-register execution pipeline.The method eliminates the intermediate memory copy and register overflow operation in the traditional scheme, improves the throughput capacity of vector retrieval and processor resource utilization under the premise of maintaining the calculation accuracy.

The invention provides a memory copying method and system, electronic equipment and a storage medium, and the memory copying method comprises the following steps: receiving a copying request initiated by a preset object by adopting an operating system service which is constructed in an operating system and is used for copying a memory, and carrying out memory copying processing according to the copying request. According to the method and the device, the memory copying service is provided through the operating system service architecture, the memory copying performance can be accelerated by fully utilizing various hardware capabilities of the system, the copying is optimized by utilizing the global view of the system service, and the like, so that the memory copying rate of preset objects such as an application program is accelerated, the copying processing efficiency is ensured, and the copying efficiency is improved. And the overall memory copying time overhead is reduced.

The invention discloses a GPU (Graphics Processing Unit) acceleration-based mask defect detection method and related equipment, and the method comprises the following steps: establishing a hardware link between a camera and a GPU through a PCIE (Peripheral Component Interface Express) bus architecture, and constructing a target memory environment of the camera matched with the GPU; image transmission is carried out on multi-channel image data, collected by the camera, of the to-be-detected mask plate based on the hardware link and the target memory environment, the multi-channel image data is transmitted to the GPU, and image transmission follows an asynchronous transmission mechanism; gPU data processing is carried out on the multi-channel image data through a GPU based on a CUDA flow technology, and a defect binary image is obtained; gPU data processing and image transmission are executed in parallel; carrying out data downloading on the defect binary image based on an asynchronous memory copying mechanism of a CUDA (Compute Unified Device Architecture), and downloading the defect binary image to a CPU (Central Processing Unit) connected with the GPU; data downloading and GPU data processing are executed in parallel; and performing defect feature extraction on the defect binary image through the CPU based on Blob analysis to obtain a defect identification result. Therefore, rapid and efficient mask defect detection can be realized.

The invention discloses a GPU direct access-based Lustre client persistent cache performance optimization method and system, relates to the technical field of high-performance computing storage, and discloses a GPU direct access-based Lustre client persistent cache performance optimization method and system which directly access a local SSD (Solid State Disk) and optimize a metadata management mechanism through a GPU. The CPU is prevented from serving as the bottleneck of data transfer, the copy operation of redundant memory is reduced, the problem of performance limitation caused by the fact that the GPU cannot directly access the storage device in the prior art is effectively solved, data transmission delay can be reduced, the system throughput is improved, CPU resource consumption is reduced, and the parallel processing capacity of the GPU is fully exerted.

The application provides a binary program-oriented data-oriented vulnerability searching method, and belongs to the technical field of computers, and comprises the following steps: inputting test data into a target binary program in a computer and running the target binary program; saving a memory snapshot when the target binary program runs to a vulnerability function where a memory error vulnerability is located; marking test data data of a buffer zone input into the computer in the memory snapshot as a pollution source; and executing the target binary program with a first instruction of the vulnerability function as a starting point. If any memory copy Gadget that copies data in the memory to other memory positions and any address write Gadget that writes data in the memory are found in the process of executing the target binary program, it is determined that the current memory error vulnerability is sufficient to be upgraded to a data-oriented vulnerability DOP for exploitation. The method can analyze data-oriented vulnerability availability of a binary program.

An apparatus, method, and computer program are described, the apparatus comprising a decode circuit configured to decode instructions, and a processing circuit configured to perform data processing in response to the instructions decoded by the decode circuit. In response to the decode circuit decoding a memory copy size determination instruction specifying as operands a source memory address, a destination memory address, and a total number of bytes to be copied from a source block of a memory location indicated by the source memory address to a destination block of a memory location indicated by the destination memory address, the processing circuit is configured to determine a memory copy size indication value indicative of a subset of the total number of bytes to be copied based on at least one of the source memory address and the destination memory address. A data transfer instruction is also described.

The present application discloses a processing system for high efficiency operation by using cache mirror data, which comprises a fetcher, at least one management processor and a cache memory. The fetcher fetches a plurality of data to make the cache memory copy at least one mirror data. When at least one data reading device outputs at least one reading request, the management processor analyzes the data position corresponding to the request and transmits the corresponding mirror data. When the data reading device outputs an editing request, the management processor analyzes the data position corresponding to the request and outputs a key and the corresponding mirror data to the data reading device for editing, and the management processor outputs a change signal to the cache memory to update the change content of the remaining corresponding mirror data to ensure the correctness of subsequent data processing and high operation rate.

The application discloses a GPU direct access-based Lustre client persistent cache performance optimization method and system, relates to the high-performance computing storage technical field, and discloses the GPU direct access-based Lustre client persistent cache performance optimization method and system, which avoids the bottleneck of CPU as a data transfer station, reduces redundant memory copy operations, effectively solves the performance limitation problem caused by the fact that a GPU cannot directly access a storage device in the prior art, can reduce data transmission delay, improve system throughput, reduce CPU resource consumption, and fully exert the parallel processing capacity of the GPU.

The application provides a data writing method and device, an electronic device and a storage medium, wherein the method applied to a block service end writes data to be written into a business write request of a storage system through acquisition; the data to be written is copied into a temporary memory to obtain a temporary memory copy located in the temporary memory; a writing operation of writing the temporary memory copy into all replica nodes is executed at a data client, and after returning writing completion information to the block service end in the case of acquiring a callback of a majority in all replica nodes, the business write request is responded according to the writing completion information, wherein the callback is generated by each replica node in the majority after being written into the temporary memory copy, and the writing completion information is used to indicate that the data to be written is completed to be written on disk. The application solves the problem that the business IO of multiple replicas is prone to causing a long tail of writing due to a single point failure in the related art.

A conflict-free parallel radix sorting algorithm, and devices and systems implementing this algorithm, schedules memory copies of data elements of a large dataset so that there is always a single copy to each target memory each cycle of operation for the system implementing the algorithm. The conflict-free parallel radix sorting algorithm eliminates memory copying conflicts in copying data elements from different source memories to the same target memory and in this way maintains maximum throughput for the copying of data elements from source memories to target memories, reducing the time required to sort the data elements of the large dataset.