17 results about "Victim cache" patented technology

An improved branch target buffer (BTB) structure is provided. An apparatus may include branch target buffers that store entries corresponding to branch instructions and corresponding targets of the branch instructions. The device may include a victim cache that stores branch target buffer entries that have been evicted from a branch target buffer of the branch target buffers. The apparatus may include branch prediction circuitry configured to access the victim cache in response to receiving a respective miss indication from each of the branch target buffers.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

This application relates to an instruction fetching method, apparatus, and computer device based on a reduced instruction set (RISC). The method includes: obtaining the address of the instruction to be executed; searching for the address of the instruction to be executed in a cache block group; if a first or second cache block is hit, reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed from the corresponding hit cache block; if a third or fourth cache block is hit, writing the instruction currently stored in the corresponding hit cache block into a free cache block in the first or second cache block; and reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed from the free cache block. The entire instruction fetching process, by adding a small-capacity static prediction cache and a victim cache, forms a four-cache group interconnected structure with the dual cache blocks that implement general read / write operations. This improves the cache hit rate and achieves fast instruction fetching even with limited instruction cache capacity.

The embodiment of the invention relates to victim cache supporting emptying write missed entries. A cache system includes a first sub-cache and a second sub-cache (700) in parallel with the first sub-cache, where the second sub-cache includes: a set of cache lines; a line type bit (708) configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write miss data; and an eviction controller (714) configured to flush the stored write miss data based on the line type bit (708).

System (700), comprising: one or more processors (10A-10N) configured to issue memory requests to access a memory system (702); and a cache (14) coupled to the one or more processors (10A-10N) and configured to cache data from the memory system (702) for access by the one or more processors (10A-10N), wherein: the cache (14) comprises a control circuit (34) configured to assign criticality values ​​to cache lines based on a plurality of factors at a time the cache lines are filled into the cache (14); the control circuit (34) is configured to, during the fill of a given cache line, represent the given cache line at a selected position in replacement data for the cache (14) based on the criticality value assigned to the given cache line; the control circuit (34) is configured to select a victim cache line to be evicted from the cache (14) based on the replacement data; and the control circuit (34) is configured to determine, according to a probability-based mode selection for a given cache eviction operation, whether to proceed according to a first victim selection mode or a second victim selection mode, wherein the first victim selection mode prevents the selection of cache lines with a critical status as victims and the second victim selection mode allows the selection of a cache line with a critical status as victims.

Furnishings, comprehensive: one or more processors (10A - 10N) configured to issue memory requests for accessing a memory system (18); and a cache switching logic (32) configured to cache data from the storage system (18) for access by the one or more processors (10A - 10N), wherein: the cache switching logic (32) includes a control switching logic (34) that is configured to: Assigning criticality values ​​to cache rows, where a given criticality value indicates that the corresponding cache row is not critical or has one of several criticality levels; and Adjusting the criticality value of a cache row in response to a criticality event; where the cache switching logic (32) to select a sacrificial cache line for replacement is configured to: Masking cache lines that have one or more higher criticality levels; and Selecting the victim cache row from unmasked cache rows based on access frequency data managed separately from criticality values ​​by the cache switching logic (32).

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically selecting a cache mode. One of the methods includes operating a system level cache (SLC) in a victim cache mode by implementing a portion of the SLC as a victim cache partition of a first cache. The method further includes monitoring a performance indicator of the victim cache partition. The first cache and the SLC are operated in a normal cache mode when the performance metric satisfies one or more handover criteria.

Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.

SOLUTION: A caching system including a first sub-cache and a second sub-cache (700) parallel to the first sub-cache, the second sub-cache including a set of cache lines, line type bits (708) configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller (714) configured to flush stored write-miss data based on the line type bits (708).SELECTED DRAWING: Figure 7

Methods, apparatus, systems and articles of manufacture are disclosed facilitate read-modify-write support in a coherent victim cache with parallel data paths. An example apparatus includes a random-access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random-access memory configured to obtain a read request indicating a first address to read via a snoop interface, an address encoder coupled to the random-access memory, the address encoder to, when the random-access memory indicates a hit of the read request, generate a second address corresponding to a victim cache based on the first address, and a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.

This application relates to row hammer attack mitigation using a victim cache. Row hammer attacks exploit unexpected and undesirable side effects of memory devices, where memory cells interact electrically with each other through leaky charge and may alter the contents of nearby memory lines not addressed in the original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to a cache line of the cache. The least recently used cache line of the cache is written to the victim cache.

A method, system, and apparatus for dynamically selecting a cache mode, including a computer program encoded on a computer storage medium. One method includes operating a system-level cache (SLC) in victim cache mode by implementing a portion of the SLC as a victim cache partition for the primary cache. The method further includes monitoring performance metrics of the victim cache partition. When the performance metrics meet one or more switching criteria, the primary cache and the SLC operate in normal cache mode.

An apparatus comprises a set associative cache, and cache replacement control circuitry to select, for a given set of the set associative cache, a victim cache entry to be replaced with a new cache entry. The victim cache entry is selected based on cache replacement selection values indicative of a relative priority for selection as the victim cache entry. In response to identifying a plurality of highest victim priority cache entries having equal cache replacement selection values indicative of equal highest priority to be selected as the victim cache entry, the cache replacement control circuitry is configured to select the victim cache entry based on a set-specific selection criterion which favours selection of a victim cache entry belonging to a preferred way for the given set, wherein the preferred way differs between at least two sets of the set associative cache.

Improved branch target buffer (BTB) structures are provided. A device can include branch target buffers storing entries corresponding to branch instructions and corresponding targets of the branch instructions. The device can include a victim cache storing a branch target buffer entry that has been evicted from a branch target buffer of the branch target buffers. The device can include branch prediction circuitry configured to access the victim cache responsive to receiving respective miss indications from each branch target buffer of the branch target buffers.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates. Multiple levels of criticality may be available for a given cache line and cache circuitry may adjust the criticality value of in response to a criticality event. One or more upper criticality levels may be masked when selecting a victim cache line for replacement.

Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.