9 results about "Victim cache" patented technology

An improved branch target buffer (BTB) structure is provided. An apparatus may include branch target buffers that store entries corresponding to branch instructions and corresponding targets of the branch instructions. The device may include a victim cache that stores branch target buffer entries that have been evicted from a branch target buffer of the branch target buffers. The apparatus may include branch prediction circuitry configured to access the victim cache in response to receiving a respective miss indication from each of the branch target buffers.

Furnishings, comprehensive: one or more processors (10A - 10N) configured to issue memory requests for accessing a memory system (18); and a cache switching logic (32) configured to cache data from the storage system (18) for access by the one or more processors (10A - 10N), wherein: the cache switching logic (32) includes a control switching logic (34) that is configured to: Assigning criticality values ​​to cache rows, where a given criticality value indicates that the corresponding cache row is not critical or has one of several criticality levels; and Adjusting the criticality value of a cache row in response to a criticality event; where the cache switching logic (32) to select a sacrificial cache line for replacement is configured to: Masking cache lines that have one or more higher criticality levels; and Selecting the victim cache row from unmasked cache rows based on access frequency data managed separately from criticality values ​​by the cache switching logic (32).

SOLUTION: A caching system including a first sub-cache and a second sub-cache (700) parallel to the first sub-cache, the second sub-cache including a set of cache lines, line type bits (708) configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller (714) configured to flush stored write-miss data based on the line type bits (708).SELECTED DRAWING: Figure 7

This application relates to row hammer attack mitigation using a victim cache. Row hammer attacks exploit unexpected and undesirable side effects of memory devices, where memory cells interact electrically with each other through leaky charge and may alter the contents of nearby memory lines not addressed in the original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to a cache line of the cache. The least recently used cache line of the cache is written to the victim cache.

A method, system, and apparatus for dynamically selecting a cache mode, including a computer program encoded on a computer storage medium. One method includes operating a system-level cache (SLC) in victim cache mode by implementing a portion of the SLC as a victim cache partition for the primary cache. The method further includes monitoring performance metrics of the victim cache partition. When the performance metrics meet one or more switching criteria, the primary cache and the SLC operate in normal cache mode.

An apparatus comprises a set associative cache, and cache replacement control circuitry to select, for a given set of the set associative cache, a victim cache entry to be replaced with a new cache entry. The victim cache entry is selected based on cache replacement selection values indicative of a relative priority for selection as the victim cache entry. In response to identifying a plurality of highest victim priority cache entries having equal cache replacement selection values indicative of equal highest priority to be selected as the victim cache entry, the cache replacement control circuitry is configured to select the victim cache entry based on a set-specific selection criterion which favours selection of a victim cache entry belonging to a preferred way for the given set, wherein the preferred way differs between at least two sets of the set associative cache.

Improved branch target buffer (BTB) structures are provided. A device can include branch target buffers storing entries corresponding to branch instructions and corresponding targets of the branch instructions. The device can include a victim cache storing a branch target buffer entry that has been evicted from a branch target buffer of the branch target buffers. The device can include branch prediction circuitry configured to access the victim cache responsive to receiving respective miss indications from each branch target buffer of the branch target buffers.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.