48 results about "Victim cache" patented technology

A method, non-transitory computer readable medium and storage server computing device that stores an identifier for a file system block evicted from a buffer cache in an entry in a table. The file system block is inserted into a victim cache hosted by an ephemeral block-level storage device by invoking a function provided by an application programming interface (API). The API exposes the ephemeral block-level storage device to a virtual storage appliance via an operating system of the storage server computing device. The entry in the table is updated to include location(s) on the ephemeral block-level storage device at which one or more portions of the file system block are stored, the location(s) returned in response to the function invocation. By this technology, performance of the virtual storage appliance is significantly improved, resulting in lower latency for client devices requesting data in a cloud storage environment.

Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.

Row hammer attacks takes advantage of unintended and undesirable side effects of memory devices in which memory cells interact electrically between themselves by leaking their charges and possibly changing the contents of nearby memory rows that were not addressed in an original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to cache lines of a cache. A least recently used cache line of the cache is written to the victim cache.

An improved branch target buffer (BTB) structure is provided. An apparatus may include branch target buffers that store entries corresponding to branch instructions and corresponding targets of the branch instructions. The device may include a victim cache that stores branch target buffer entries that have been evicted from a branch target buffer of the branch target buffers. The apparatus may include branch prediction circuitry configured to access the victim cache in response to receiving a respective miss indication from each of the branch target buffers.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.

This application relates to an instruction fetching method, apparatus, and computer device based on a reduced instruction set (RISC). The method includes: obtaining the address of the instruction to be executed; searching for the address of the instruction to be executed in a cache block group; if a first or second cache block is hit, reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed from the corresponding hit cache block; if a third or fourth cache block is hit, writing the instruction currently stored in the corresponding hit cache block into a free cache block in the first or second cache block; and reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed from the free cache block. The entire instruction fetching process, by adding a small-capacity static prediction cache and a victim cache, forms a four-cache group interconnected structure with the dual cache blocks that implement general read / write operations. This improves the cache hit rate and achieves fast instruction fetching even with limited instruction cache capacity.

The embodiment of the invention relates to victim cache supporting emptying write missed entries. A cache system includes a first sub-cache and a second sub-cache (700) in parallel with the first sub-cache, where the second sub-cache includes: a set of cache lines; a line type bit (708) configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write miss data; and an eviction controller (714) configured to flush the stored write miss data based on the line type bit (708).

A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

System (700), comprising: one or more processors (10A-10N) configured to issue memory requests to access a memory system (702); and a cache (14) coupled to the one or more processors (10A-10N) and configured to cache data from the memory system (702) for access by the one or more processors (10A-10N), wherein: the cache (14) comprises a control circuit (34) configured to assign criticality values ​​to cache lines based on a plurality of factors at a time the cache lines are filled into the cache (14); the control circuit (34) is configured to, during the fill of a given cache line, represent the given cache line at a selected position in replacement data for the cache (14) based on the criticality value assigned to the given cache line; the control circuit (34) is configured to select a victim cache line to be evicted from the cache (14) based on the replacement data; and the control circuit (34) is configured to determine, according to a probability-based mode selection for a given cache eviction operation, whether to proceed according to a first victim selection mode or a second victim selection mode, wherein the first victim selection mode prevents the selection of cache lines with a critical status as victims and the second victim selection mode allows the selection of a cache line with a critical status as victims.

Methods, apparatus, systems and articles of manufacture are disclosed facilitate read-modify-write support in a coherent victim cache with parallel data paths. An example apparatus includes a random-access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random-access memory configured to obtain a read request indicating a first address to read via a snoop interface, an address encoder coupled to the random-access memory, the address encoder to, when the random-access memory indicates a hit of the read request, generate a second address corresponding to a victim cache based on the first address, and a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

Row hammer attacks takes advantage of unintended and undesirable side effects of memory devices in which memory cells interact electrically between themselves by leaking their charges and possibly changing the contents of nearby memory rows that were not addressed in an original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to cache lines of a cache. A least recently used cache line of the cache is written to the victim cache.

Furnishings, comprehensive: one or more processors (10A - 10N) configured to issue memory requests for accessing a memory system (18); and a cache switching logic (32) configured to cache data from the storage system (18) for access by the one or more processors (10A - 10N), wherein: the cache switching logic (32) includes a control switching logic (34) that is configured to: Assigning criticality values ​​to cache rows, where a given criticality value indicates that the corresponding cache row is not critical or has one of several criticality levels; and Adjusting the criticality value of a cache row in response to a criticality event; where the cache switching logic (32) to select a sacrificial cache line for replacement is configured to: Masking cache lines that have one or more higher criticality levels; and Selecting the victim cache row from unmasked cache rows based on access frequency data managed separately from criticality values ​​by the cache switching logic (32).

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically selecting a cache mode. One of the methods includes operating a system level cache (SLC) in a victim cache mode by implementing a portion of the SLC as a victim cache partition of a first cache. The method further includes monitoring a performance indicator of the victim cache partition. The first cache and the SLC are operated in a normal cache mode when the performance metric satisfies one or more handover criteria.

Methods, apparatus, systems and articles of manufacture are disclosed for multi-banked victim cache with dual datapath. An example cache system includes a storage element that includes banks operable to store data, ports operable to receive memory operations in parallel, wherein each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective port of the ports and a respective bank of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.

Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

SOLUTION: A caching system including a first sub-cache and a second sub-cache (700) parallel to the first sub-cache, the second sub-cache including a set of cache lines, line type bits (708) configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller (714) configured to flush stored write-miss data based on the line type bits (708).SELECTED DRAWING: Figure 7

Methods, apparatus, systems and articles of manufacture are disclosed facilitate read-modify-write support in a coherent victim cache with parallel data paths. An example apparatus includes a random-access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random-access memory configured to obtain a read request indicating a first address to read via a snoop interface, an address encoder coupled to the random-access memory, the address encoder to, when the random-access memory indicates a hit of the read request, generate a second address corresponding to a victim cache based on the first address, and a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.

A cache system comprising a first sub-cache and a second sub-cache (700) in parallel with the first sub-cache, wherein the second sub-cache comprises: a set of cache lines; line type bits (708) configured to store an indication that a corresponding cache line in the set of cache lines is configured to store write miss data; and an eviction controller (714) configured to flush the stored write miss data based on the line type bits (708).

A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

The present disclosure provides a data management method for a computer system, the computer system comprising at least one processor and at least a first cache, a second cache, a victim buffer and a memory allocated to the at least one processor, the method comprising: selecting a victim cache line to be evicted from the first cache; finding a victim buffer position corresponding to the victim cache line from the victim buffer; copying data of the victim cache line to a data field of the victim buffer position; copying a back pointer associated with the victim cache line to a back pointer field of the victim buffer position; and reclaiming the victim space of the first cache using the victim buffer. The present disclosure also provides a multi-processor system and a computer-readable storage medium.

A caching system including a first sub-cache, and a second sub-cache coupled in parallel with the first sub-cache; wherein the second sub-cache includes line type bits configured to store an indication that a corresponding line of the second sub-cache is configured to store write-miss data.

This application relates to row hammer attack mitigation using a victim cache. Row hammer attacks exploit unexpected and undesirable side effects of memory devices, where memory cells interact electrically with each other through leaky charge and may alter the contents of nearby memory lines not addressed in the original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to a cache line of the cache. The least recently used cache line of the cache is written to the victim cache.

A method, system, and apparatus for dynamically selecting a cache mode, including a computer program encoded on a computer storage medium. One method includes operating a system-level cache (SLC) in victim cache mode by implementing a portion of the SLC as a victim cache partition for the primary cache. The method further includes monitoring performance metrics of the victim cache partition. When the performance metrics meet one or more switching criteria, the primary cache and the SLC operate in normal cache mode.

An apparatus comprises a set associative cache, and cache replacement control circuitry to select, for a given set of the set associative cache, a victim cache entry to be replaced with a new cache entry. The victim cache entry is selected based on cache replacement selection values indicative of a relative priority for selection as the victim cache entry. In response to identifying a plurality of highest victim priority cache entries having equal cache replacement selection values indicative of equal highest priority to be selected as the victim cache entry, the cache replacement control circuitry is configured to select the victim cache entry based on a set-specific selection criterion which favours selection of a victim cache entry belonging to a preferred way for the given set, wherein the preferred way differs between at least two sets of the set associative cache.

An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.

Improved branch target buffer (BTB) structures are provided. A device can include branch target buffers storing entries corresponding to branch instructions and corresponding targets of the branch instructions. The device can include a victim cache storing a branch target buffer entry that has been evicted from a branch target buffer of the branch target buffers. The device can include branch prediction circuitry configured to access the victim cache responsive to receiving respective miss indications from each branch target buffer of the branch target buffers.