142 results about "Row hammer" patented technology

The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may engage a counting mode in which activation counts for memory sub-banks are tracked. For example, a memory controller may engage a counting mode in which activation counts for memory rows of memory sub-banks are maintained. Under certain conditions, the memory controller may transition from the counting mode to a sampling mode to mitigate potential row hammer attacks. The memory controller may consider various conditions in determining whether to continue detecting and mitigating potential row hammer attacks in the sampling mode and / or transitioning back to the counting mode. By selectively transitioning between the different operating modes, the memory controller may reduce periods of time when the memory hardware is vulnerable to attacks.

A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.

The invention relates to the technical field of computers, in particular to a DRAM row hammering test method and device, electronic equipment and a chip, the method is executed in a DRAM controller in a hardware logic mode, and the method comprises the steps that a data writing request for a row to be tested is generated according to a preset data mode, the data writing request is converted into a writing command sequence, and the writing command sequence is sent to DRAM particles; generating an attack request for an attack line according to a preset attack mode, converting the attack request into a line activation and pre-charging command sequence, and sending the line activation and pre-charging command sequence to the DRAM particles; and reading data of the to-be-detected row in the DRAM particles, comparing the data with initially written data to detect whether bit flipping occurs, and determining the row subjected to bit flipping as a damaged row. According to the embodiment of the invention, the test efficiency and reliability can be effectively improved.

The invention relates to the technical field of semiconductors, and provides a memory and an operation method thereof, which are used for relieving harm caused by line hammering. The memory comprises a memory array and a control circuit. The control circuit is configured to enter a first mode in response to a command address signal and a mode control signal when a preset condition is met, execute an updating operation on a counting storage unit corresponding to an activated word line at a first moment, execute a pre-charging operation on the activated word line at a second moment, and take counting data as a counting value of row hammer refreshing; or, responding to the command address signal and the mode control signal when the preset condition is not met, entering a second mode, not executing the updating operation on the counting storage unit corresponding to the activated word line, and starting to execute the pre-charging operation on the activated word line at a second moment, and taking an activation count value of an activation word line in the dynamic lookup table as a count value of row hammer refreshing. In this way, balance is achieved between flexible configuration and reliability guarantee, and harm caused by hammering is relieved.

A memory device includes at least one bank including memory cells, and a register corresponding to the at least one bank. The bank includes a plurality of rows that are arranged in a row direction, and a plurality of count cells, each of which stores count data associated with the number of times of access of each of the plurality of rows. The register stores an address and count data, which are associated with at least one row among the plurality of rows.

A method for obtaining a row hammer refresh address, including: after a row hammer refresh signal arrives, obtaining a current sampling address, and determining whether a high address is locked in a current row hammer refresh cycle; in response to the high address being locked, determining whether a high address of the current sampling address is identical to the locked high address; in response to being identical, updating an access frequency of the locked high address, and updating access frequencies of low addresses with a low address of the current sampling address; and when a next row hammer refresh signal arrives, using a low address with a highest access frequency stored in the group of low registers as a low address of the row hammer refresh address, and using the locked high address as a high address of the row hammer refresh address.

An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can be configured to determine whether a quantity of row activations directed to a row of the memory devices exceeds a row hammer criterion. The controller can be configured to select, responsive to determining that the row hammer criterion is met, a row hammer mitigation response from a plurality of row hammer mitigation responses available for initiation. The controller can be configured to initiate the selected row hammer mitigation response.

A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

The invention relates to the technical field of computers, in particular to a DRAM (Dynamic Random Access Memory) line hammering defense method, device and system, a chip and electronic equipment. The method is applied to a DRAM (Dynamic Random Access Memory) controller and comprises the following steps: acquiring a row identifier of a row activation command for requesting a DRAM; when the row identifier does not exist in an entry container and the entry container is not full, storing the row identifier and a corresponding activation count in the entry container; under the condition that the row identifier does not exist in an entry container and the entry container is full, replacing one entry in the entry container with an entry attribute of a new row identifier based on an activation count and / or an access time sequence recorded in the entry container; and under the condition that any activation count in the entry container exceeds a row activation threshold value, determining the corresponding row as an attack row hammered by the row, and executing defense. According to the embodiment of the invention, chip area overhead and related power consumption can be effectively reduced.

The present application is directed to row hammer protection for a memory device. A memory device may identify a threshold for associated row accesses to a memory array (e.g., access commands or activations to the same row address or row address space). In a first operating mode, the memory device may execute a command received from a host device on the memory array. The memory device may determine that a metric of the received row access command satisfies the threshold for associated row access. The memory device may switch the memory array from the first operating mode to a second operating mode based on satisfying the threshold. The second operating mode may restrict access to at least one row of the memory, while the first mode may be less restrictive. Additionally or alternatively, the memory device may notify the host device that the metric has satisfied the threshold.

The present disclosure provides a refresh method and device, relating to the field of semiconductor technology. The method includes: obtaining an activation count value of a currently activated row address of a memory within a preset duration; if the activation count value belongs to any one of multiple count intervals that exceeds a row hammer threshold, determining whether a preset queue is full; wherein the queue is used to store row addresses that require a row hammer refresh operation; when the queue is not full, placing the row address in the queue, and determining a range of victim row addresses corresponding to the row address based on a target count interval to which the activation count value belongs, and refreshing the victim row address; when the queue is full, performing one of the preset operations, which includes adding 1 to the activation count value. The present disclosure can effectively ensure the stability of the memory.

Linear feedback shift registers (LFSRs) are described that are used to generate bounded random numbers (e.g., the range of random numbers is narrower than the range of random numbers generated by a conventional LFSR having the same width). In one embodiment, a bounded LFSR for generating n-bit values includes an m-bit LFSR that ranges over 2 m m random numbers and an n-m-bit LFSR that ranges over 2 n‑m n-m-1-k random numbers. The bounded LFSR further includes logic for skipping over k values in a repeatable sequence of the n-m-bit LFSR, e.g., the logic can be configured during design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on outputs of the m-bit LFSR and the n-m-bit LFSR. In one embodiment, the bounded random numbers generated by the bounded LFSR are used as random addresses in a row hammer mitigation system.

The invention relates to a storage system. The storage system includes: a normal storage area suitable for storing normal data; a secure storage area adapted to store secure data; a first row hammer detection circuit adapted to sample and count partial rows activated in the normal memory area to select a first row that needs to be refreshed; and a second row hammer detection circuit adapted to count all rows activated in the secure storage area to select a second row that needs to be refreshed.

Disclosed is a memory device including a count circuit suitable for: generating a plurality of group selection signals corresponding to a plurality of address groups by counting, in units of the address groups, a number of times that each of a plurality of address signals is inputted to the memory device, wherein each of the address groups corresponds to one or more address signals from the plurality of address signals, and selecting a target group from the address groups, the target group corresponding to a greatest one of the numbers for the respective address groups, and a sampling circuit suitable for randomly sampling a target address signal from the target group based on the plurality of group selection signals and the plurality of address signals.

Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.

Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

A semiconductor memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer handler configured to generate a refresh address when performing a refresh operation on the plurality rows of memory cells. The row hammer handler (RHH) includes a weight distributor configured to: receive a plurality of row addresses, assign a weight to each of the plurality of row addresses thus received, and to generate weight data corresponding to each of the plurality of row addresses. The RHH also includes an aggress address generator configured to determine an aggress address of a row of memory cells based on the weight data, and a refresh address generator configured to receive the aggress address and to generate the refresh address, which includes address information of a memory cell row adjacent the aggress address.

Row hammer attacks takes advantage of unintended and undesirable side effects of memory devices in which memory cells interact electrically between themselves by leaking their charges and possibly changing the contents of nearby memory rows that were not addressed in an original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to cache lines of a cache. A least recently used cache line of the cache is written to the victim cache.

The present application provides a refresh control circuit and memory, including: a refresh counter that counts pulses of a row activation window signal within the active level period of a refresh window signal and within the active level period of an enable signal, and outputs the count result; and performs a count reset in response to a period reset signal; a reset circuit for outputting a period reset signal when the count result currently output by the refresh counter reaches a preset number; and a control circuit for outputting a protection refresh window signal based on the count result currently output by the refresh counter; wherein, when the count result is within a preset range, the protection refresh window signal is at an active level. This solution can implement row hammer protection.

Disclosed is a memory system which includes a memory device that includes a memory cell array and a notification circuit, and a memory controller that transmits a refresh management (RFM) command to the memory device, based on a number of occurrences of bank activation of a bank included in the memory cell array reaching a threshold. The memory controller controls a transmission frequency of the RFM command, based on a notification obtained through the notification circuit. The notification includes at least one of a row hammer risk for rows included in the bank or temperature information including a temperature range of the memory device.

Methods for adjusting row hammer refresh rates and related memory devices and systems are disclosed. A method can include determining a number of valid commands associated with at least one bank of a memory device during a first time interval. The method can further include adjusting a row hammer refresh rate for the at least one bank for a second time interval based on the number of valid commands associated with the at least one bank during the first time interval.

A system to progressively generate responses configured to mitigate risk associated with row hammer attacks. Between two successive refreshing of memory cells in a memory device, increasing thresholds are used to detect row hammer attacks. For example, after a first alert of row hammer attacks is generated using a first lower threshold, a first operation associated with the first lower threshold is initiated to mitigate risk associated with row hammer attack; and a second higher threshold is used to detect row hammer attacks. After a second alert of row hammer attacks is generated using the second lower threshold, a second operation associated with the second lower threshold is initiated to mitigate risk associated with row hammer attack.

To provide a semiconductor memory in which row hammer refresh operation can be performed without deteriorating performance of normal refresh operation.SOLUTION: A semiconductor memory device includes a control unit 10 which performs control so as to perform normal refresh operation for simultaneously refreshing memory cells connected to each of a plurality of word lines in response to a refresh request, and performs control so as to perform row hammer refresh operation each time the normal refresh operation is performed at least once.SELECTED DRAWING: Figure 2

Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

Aspects disclosed include a memory system with interleaved row refresh to address row hammer degradation. The memory system includes a refresh control circuit and a memory block. The memory block includes a first plurality of memory cell rows and a second plurality of memory cell rows, wherein the first plurality of memory cell rows is spatially interleaved with the second plurality of memory cell rows. In response to receiving a first number of commands to open the first plurality of memory cell rows which exceed a first threshold, the refresh control circuit is configured to refresh the second plurality of memory cell rows. The memory system advantageously addresses the known problem of row hammering while not expending energy refreshing the first plurality of memory cell rows, in contrast to conventional approaches which refresh all the rows.

An apparatus can include a refresh control circuit having a plurality of timing circuits. The timing circuits can be used to control a steal rate, e.g., a rate of refresh slots dedicated to fixing victim word lines that are hammered by a row hammer. The timing circuits can be controlled to allow the steal rate to be independently adjusted for different victim word lines. Thus, different victim word lines can be refreshed at different rates, and the different rates can be independent of one another.

Systems, apparatuses, and methods related to a row hammer refresh operation are described herein. An example apparatus can include an array of memory cells of a memory device. The array of memory cells can include a plurality of dies and at least one of the plurality of dies is a row hammer die. The example apparatus can include a memory controller coupled to the array of memory cells. The memory controller can perform a number of operations on the array of memory cells. The memory controller can detect a quantity of accesses associated with the row hammer die and based on the number of operations performed. The memory controller can, in response to detection of a threshold quantity of accesses of a group of memory cells in the row hammer die, perform a refresh operation on a group of memory cells in an additional die of the plurality of dies.

A memory device can internally track row address activates for perfect row hammer tracking, incrementing an activate count for each row when an access command is received for a row. Instead of incrementing the count for each activate, the memory controller can indicate a number greater than one for the memory device to increment the count, and then indicate not to increment the count for subsequent accesses up to the number indicated. The memory controller can determine whether the row address of an activate command is one of N recent row addresses that received the access command. The memory controller can indicate an increment of zero if the row address is one of the N recent addresses, and indicate an increment of a number higher than one if the row address is not one of the N recent addresses.

Examples include techniques for a memory module per row activate counter. The techniques include detecting a row hammer or row disturb condition for a row address at a volatile memory device if an activate count to the row address matches a threshold count. The activate count is maintained by a controller for the memory module. Detection of the row hammer or row disturb condition can cause refresh management actions to mitigate the row hammer or row disturb condition.

A memory device includes a bank including memory cells. The bank includes rows arranged in a row direction, count cells, each storing row hammer count data associated with a number of times a corresponding row of the rows is accessed, and extended count cells, each storing information about one or more of extended row hammer count data associated with the number of times the corresponding row of the row is accessed or a number of times a row hammer refresh operation is executed on the corresponding row of rows.