207 results about "Row hammer" patented technology

Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may track activations of row addresses within a memory hardware (e.g., a DRAM device) and determine whether a pattern of activations is indicative of a row hammer attack. This is determined using a counting mode for corresponding memory sub-banks. Where a likely row hammer attack is detected, the memory controller may activate a sampling mode (rather than the counting mode) for a particular sub-bank to identify which of the row addresses should be refreshed on the memory hardware. The implementations described herein provide a low computational cost alternative to heavy-handed detection mechanisms that require access to significant computing resources to accurately detect and mitigate row hammer attacks.

The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may engage a counting mode in which activation counts for memory sub-banks are tracked. For example, a memory controller may engage a counting mode in which activation counts for memory rows of memory sub-banks are maintained. Under certain conditions, the memory controller may transition from the counting mode to a sampling mode to mitigate potential row hammer attacks. The memory controller may consider various conditions in determining whether to continue detecting and mitigating potential row hammer attacks in the sampling mode and / or transitioning back to the counting mode. By selectively transitioning between the different operating modes, the memory controller may reduce periods of time when the memory hardware is vulnerable to attacks.

Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.

An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.

The invention relates to the technical field of computers, in particular to a DRAM row hammering test method and device, electronic equipment and a chip, the method is executed in a DRAM controller in a hardware logic mode, and the method comprises the steps that a data writing request for a row to be tested is generated according to a preset data mode, the data writing request is converted into a writing command sequence, and the writing command sequence is sent to DRAM particles; generating an attack request for an attack line according to a preset attack mode, converting the attack request into a line activation and pre-charging command sequence, and sending the line activation and pre-charging command sequence to the DRAM particles; and reading data of the to-be-detected row in the DRAM particles, comparing the data with initially written data to detect whether bit flipping occurs, and determining the row subjected to bit flipping as a damaged row. According to the embodiment of the invention, the test efficiency and reliability can be effectively improved.

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an error check and scrub (ECS) circuit, a row hammer management circuit and a refresh control circuit. The ECC engine generates an error generation signal based on a result of an ECC decoding. The ECS circuit generates scrubbing addresses and outputs at least one of the scrubbing addresses as an error address based on the error generation signal. The row hammer management circuit stores an error flag with a first logic level in count cells, compares counted values with different reference number of times based on a logic level of the error flag and outputs a hammer address. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to the memory cell row corresponding to the hammer address.

Disclosed are methods, systems, and apparatuses for providing per-channel row hammer alerts, from a memory device to a host, without the use of a dedicated per-channel alert interface. When detecting a row hammer alert condition, the memory device may determine whether an existing interface (e.g., a severity interface used to transmit severity information) is available. The interface may be available outside of certain designated burst positions during a read burst. Once the interface is available, the memory device may transmit a row hammer alert indication to the host. The host may determine whether information received over the interface is associated with a row hammer alert or severity, depending on when the information was received (e.g., in what burst position during a read burst).

The invention relates to the technical field of semiconductors, and provides a memory and an operation method thereof, which are used for relieving harm caused by line hammering. The memory comprises a memory array and a control circuit. The control circuit is configured to enter a first mode in response to a command address signal and a mode control signal when a preset condition is met, execute an updating operation on a counting storage unit corresponding to an activated word line at a first moment, execute a pre-charging operation on the activated word line at a second moment, and take counting data as a counting value of row hammer refreshing; or, responding to the command address signal and the mode control signal when the preset condition is not met, entering a second mode, not executing the updating operation on the counting storage unit corresponding to the activated word line, and starting to execute the pre-charging operation on the activated word line at a second moment, and taking an activation count value of an activation word line in the dynamic lookup table as a count value of row hammer refreshing. In this way, balance is achieved between flexible configuration and reliability guarantee, and harm caused by hammering is relieved.

A memory device includes at least one bank including memory cells, and a register corresponding to the at least one bank. The bank includes a plurality of rows that are arranged in a row direction, and a plurality of count cells, each of which stores count data associated with the number of times of access of each of the plurality of rows. The register stores an address and count data, which are associated with at least one row among the plurality of rows.

Row hammer attacks takes advantage of unintended and undesirable side effects of memory devices in which memory cells interact electrically between themselves by leaking their charges and possibly changing the contents of nearby memory rows that were not addressed in an original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to cache lines of a cache. A least recently used cache line of the cache is written to the victim cache.

The invention relates to the field of semiconductor circuit design, in particular to a refresh control circuit and a memory, and the refresh control circuit comprises a counting identification circuit which is configured to generate and output a counting identification signal at an effective level based on a full-array refresh identification signal and a refresh activation signal when a same-array refresh identification signal is effective; the counting processing circuit is configured to receive the counting identification signal and count based on the counting identification signal to generate a counting result; and the first control circuit is configured to receive the counting result, generate and output an initial supplementary refresh indication signal of an effective level when the counting result is within a first preset range, and indicate the memory to execute supplementary refresh operation when the supplementary refresh indication signal is effective, so as to provide a Row Hammer protection control strategy during frequent switching of refresh modes. And therefore, vulnerabilities of Row Hammer protection of the memory can be prevented.

Methods, systems, and devices for row hammer mitigation reliability in stacked memory architectures are described. A spare counter may be implemented at a first interface block of a logic die to enable increased reliability and efficiency in row hammer mitigation. The first interface block may use a spare counter in case of an error associated with a counter at a memory array die. A second interface block of an array die may identify an error associated with a counter of a memory array and may transmit an indication of the error to the first interface block. The first interface block may receive the indication and may activate a spare counter to track access operations on (e.g., activations of) the row based on the indication. The first interface block may use the spare counter to evaluate whether to transmit refresh signaling to the second interface block for row hammer mitigation.

A memory apparatus, comprising: a command decoder, generating an external refresh command; a refresh skip divider, coupled to the command decoder, catching the external refresh command and outputting a divider signal; a row hammer circuit, generating a row hammer signal; and a refresh control circuit, coupled to the command decoder, the refresh skip divider and the row hammer circuit, wherein the refresh control circuit receives the external refresh command, the divider signal and the row hammer signal, and the refresh control circuit generates an internal refresh command according to the external refresh command, the divider signal and the row hammer signal.

A semiconductor memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer handler configured to generate a refresh address when performing a refresh operation on the plurality rows of memory cells. The row hammer handler (RHH) includes a weight distributor configured to: receive a plurality of row addresses, assign a weight to each of the plurality of row addresses thus received, and to generate weight data corresponding to each of the plurality of row addresses. The RHH also includes an aggress address generator configured to determine an aggress address of a row of memory cells based on the weight data, and a refresh address generator configured to receive the aggress address and to generate the refresh address, which includes address information of a memory cell row adjacent the aggress address.

A semiconductor memory device may include a memory cell array and a row hammer control block. The memory cell array may include word lines, bit lines crossed with the word lines and memory cells arranged between the word lines and the bit lines. The row hammer control block controls a voltage of a victim word line adjacent to a selected word line among the word lines, and includes a victim word line determination circuit and a victim voltage output circuit. The victim word line determination circuit receives address information of the selected word line as address information of an aggressor word line to determine at least one of the word lines adjacent to the aggressor word line. The victim voltage output circuit may temporarily output a victim voltage different from an off voltage, which is applied to non-selected word lines during a falling section of the aggressor word line.

A method for obtaining a row hammer refresh address, including: after a row hammer refresh signal arrives, obtaining a current sampling address, and determining whether a high address is locked in a current row hammer refresh cycle; in response to the high address being locked, determining whether a high address of the current sampling address is identical to the locked high address; in response to being identical, updating an access frequency of the locked high address, and updating access frequencies of low addresses with a low address of the current sampling address; and when a next row hammer refresh signal arrives, using a low address with a highest access frequency stored in the group of low registers as a low address of the row hammer refresh address, and using the locked high address as a high address of the row hammer refresh address.

A memory controller includes a command / address generation module; and a row-hammer tracking module configured to track a row-hammer address based on an active command and an address for a target bank and a target row indicated by the active command, the active command and the address being received from the command / address generation module, wherein the row-hammer tracking module includes: a plurality of storage devices each including fields corresponding to banks, each of the fields storing candidate addresses and access counting values for the candidate addresses; and at least one search controller configured to sequentially search, according to a clock, fields of the plurality of storage devices corresponding to the target bank when the active command is input, and search, during one clock, fields of the plurality of storage devices corresponding to different banks based on active commands indicating the different banks.

An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can be configured to determine whether a quantity of row activations directed to a row of the memory devices exceeds a row hammer criterion. The controller can be configured to select, responsive to determining that the row hammer criterion is met, a row hammer mitigation response from a plurality of row hammer mitigation responses available for initiation. The controller can be configured to initiate the selected row hammer mitigation response.

The invention relates to a refresh circuit and a refresh method. The refresh circuit comprises a refresh control circuit used for receiving first refresh commands and counting the first refresh commands; and generating a second refresh control signal based on the count value of the first refresh command; the refresh pulse generation circuit is used for receiving first refresh commands and generating a first refresh pulse based on each first refresh command; receiving a second refresh control signal, and generating at least one second refresh pulse based on the first refresh command and the second refresh control signal; and the refresh operation circuit is used for executing a first refresh operation once according to each first refresh pulse and executing a second refresh operation once according to each second refresh pulse. According to the method, extra refreshing operation is added in a conventional refreshing process so as to execute redundant line / line hammer refreshing; on the basis of meeting the time requirement of the conventional refreshing operation, the redundant row / row hammer address is refreshed.

A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

A memory device includes at least one bank including at least a first sub-bank and a second sub-bank disposed in a word line direction. The first sub-bank may include a normal data region connected to a plurality of first word lines and storing normal data, the second sub-bank may include a metadata region connected to a plurality of second word lines and storing metadata corresponding to the normal data, the plurality of first word lines may be matched with the plurality of second word lines to form a plurality of word line pairs, and the first sub-bank and the second sub-bank may share a row hammer region that stores the number of accesses to the plurality of word line pairs.

A memory device with internal row hammer mitigation is coupled to a memory controller. A memory controller or host may assist row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an additional refresh command, the memory device may perform a refresh for row hammer mitigation, rather than a refresh for standard data integrity. The memory controller may maintain a tracking of the number of activation commands sent to the memory device, and in response to a threshold number of activation commands, the memory controller sends additional refresh commands. With additional refresh commands, the memory device may refresh a potential victim row of the potential aggressor row rather than only rows that have not been accessed for a period of time.

The invention relates to the technical field of computers, in particular to a DRAM (Dynamic Random Access Memory) line hammering defense method, device and system, a chip and electronic equipment. The method is applied to a DRAM (Dynamic Random Access Memory) controller and comprises the following steps: acquiring a row identifier of a row activation command for requesting a DRAM; when the row identifier does not exist in an entry container and the entry container is not full, storing the row identifier and a corresponding activation count in the entry container; under the condition that the row identifier does not exist in an entry container and the entry container is full, replacing one entry in the entry container with an entry attribute of a new row identifier based on an activation count and / or an access time sequence recorded in the entry container; and under the condition that any activation count in the entry container exceeds a row activation threshold value, determining the corresponding row as an attack row hammered by the row, and executing defense. According to the embodiment of the invention, chip area overhead and related power consumption can be effectively reduced.

The present application is directed to row hammer protection for a memory device. A memory device may identify a threshold for associated row accesses to a memory array (e.g., access commands or activations to the same row address or row address space). In a first operating mode, the memory device may execute a command received from a host device on the memory array. The memory device may determine that a metric of the received row access command satisfies the threshold for associated row access. The memory device may switch the memory array from the first operating mode to a second operating mode based on satisfying the threshold. The second operating mode may restrict access to at least one row of the memory, while the first mode may be less restrictive. Additionally or alternatively, the memory device may notify the host device that the metric has satisfied the threshold.

A random access memory device includes memory cells associated with each row for storing metadata related to accesses to that row. Events that may cause row hammer may be tracked on a row-by-row basis by counter values in the metadata dedicated cells. The counter values are stored in a subset of rows of the metadata dedicated memory array. Multiple counter values (e.g., those associated with multiple victim and / or aggressor rows) may be read and / or written with a single activation of the metadata dedicated row. The metadata dedicated row stores the counter values for both the accessed data row and nearby data rows, the metadata counter value(s) associated with both the accessed data some nearby data rows may be updated using the single access to the metadata dedicated row.

The present disclosure provides a refresh method and device, relating to the field of semiconductor technology. The method includes: obtaining an activation count value of a currently activated row address of a memory within a preset duration; if the activation count value belongs to any one of multiple count intervals that exceeds a row hammer threshold, determining whether a preset queue is full; wherein the queue is used to store row addresses that require a row hammer refresh operation; when the queue is not full, placing the row address in the queue, and determining a range of victim row addresses corresponding to the row address based on a target count interval to which the activation count value belongs, and refreshing the victim row address; when the queue is full, performing one of the preset operations, which includes adding 1 to the activation count value. The present disclosure can effectively ensure the stability of the memory.

Linear feedback shift registers (LFSRs) are described that are used to generate bounded random numbers (e.g., the range of random numbers is narrower than the range of random numbers generated by a conventional LFSR having the same width). In one embodiment, a bounded LFSR for generating n-bit values includes an m-bit LFSR that ranges over 2 m m random numbers and an n-m-bit LFSR that ranges over 2 n‑m n-m-1-k random numbers. The bounded LFSR further includes logic for skipping over k values in a repeatable sequence of the n-m-bit LFSR, e.g., the logic can be configured during design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on outputs of the m-bit LFSR and the n-m-bit LFSR. In one embodiment, the bounded random numbers generated by the bounded LFSR are used as random addresses in a row hammer mitigation system.

The invention relates to a storage system. The storage system includes: a normal storage area suitable for storing normal data; a secure storage area adapted to store secure data; a first row hammer detection circuit adapted to sample and count partial rows activated in the normal memory area to select a first row that needs to be refreshed; and a second row hammer detection circuit adapted to count all rows activated in the secure storage area to select a second row that needs to be refreshed.