52 results about "Row hammer" patented technology

The invention relates to the technical field of computers, in particular to a DRAM row hammering test method and device, electronic equipment and a chip, the method is executed in a DRAM controller in a hardware logic mode, and the method comprises the steps that a data writing request for a row to be tested is generated according to a preset data mode, the data writing request is converted into a writing command sequence, and the writing command sequence is sent to DRAM particles; generating an attack request for an attack line according to a preset attack mode, converting the attack request into a line activation and pre-charging command sequence, and sending the line activation and pre-charging command sequence to the DRAM particles; and reading data of the to-be-detected row in the DRAM particles, comparing the data with initially written data to detect whether bit flipping occurs, and determining the row subjected to bit flipping as a damaged row. According to the embodiment of the invention, the test efficiency and reliability can be effectively improved.

The invention relates to the technical field of semiconductors, and provides a memory and an operation method thereof, which are used for relieving harm caused by line hammering. The memory comprises a memory array and a control circuit. The control circuit is configured to enter a first mode in response to a command address signal and a mode control signal when a preset condition is met, execute an updating operation on a counting storage unit corresponding to an activated word line at a first moment, execute a pre-charging operation on the activated word line at a second moment, and take counting data as a counting value of row hammer refreshing; or, responding to the command address signal and the mode control signal when the preset condition is not met, entering a second mode, not executing the updating operation on the counting storage unit corresponding to the activated word line, and starting to execute the pre-charging operation on the activated word line at a second moment, and taking an activation count value of an activation word line in the dynamic lookup table as a count value of row hammer refreshing. In this way, balance is achieved between flexible configuration and reliability guarantee, and harm caused by hammering is relieved.

The invention relates to the technical field of computers, in particular to a DRAM (Dynamic Random Access Memory) line hammering defense method, device and system, a chip and electronic equipment. The method is applied to a DRAM (Dynamic Random Access Memory) controller and comprises the following steps: acquiring a row identifier of a row activation command for requesting a DRAM; when the row identifier does not exist in an entry container and the entry container is not full, storing the row identifier and a corresponding activation count in the entry container; under the condition that the row identifier does not exist in an entry container and the entry container is full, replacing one entry in the entry container with an entry attribute of a new row identifier based on an activation count and / or an access time sequence recorded in the entry container; and under the condition that any activation count in the entry container exceeds a row activation threshold value, determining the corresponding row as an attack row hammered by the row, and executing defense. According to the embodiment of the invention, chip area overhead and related power consumption can be effectively reduced.

Linear feedback shift registers (LFSRs) are described that are used to generate bounded random numbers (e.g., the range of random numbers is narrower than the range of random numbers generated by a conventional LFSR having the same width). In one embodiment, a bounded LFSR for generating n-bit values includes an m-bit LFSR that ranges over 2 m m random numbers and an n-m-bit LFSR that ranges over 2 n‑m n-m-1-k random numbers. The bounded LFSR further includes logic for skipping over k values in a repeatable sequence of the n-m-bit LFSR, e.g., the logic can be configured during design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on outputs of the m-bit LFSR and the n-m-bit LFSR. In one embodiment, the bounded random numbers generated by the bounded LFSR are used as random addresses in a row hammer mitigation system.

Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.

Methods for adjusting row hammer refresh rates and related memory devices and systems are disclosed. A method can include determining a number of valid commands associated with at least one bank of a memory device during a first time interval. The method can further include adjusting a row hammer refresh rate for the at least one bank for a second time interval based on the number of valid commands associated with the at least one bank during the first time interval.

To provide a semiconductor memory in which row hammer refresh operation can be performed without deteriorating performance of normal refresh operation.SOLUTION: A semiconductor memory device includes a control unit 10 which performs control so as to perform normal refresh operation for simultaneously refreshing memory cells connected to each of a plurality of word lines in response to a refresh request, and performs control so as to perform row hammer refresh operation each time the normal refresh operation is performed at least once.SELECTED DRAWING: Figure 2

Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

An apparatus can include a refresh control circuit having a plurality of timing circuits. The timing circuits can be used to control a steal rate, e.g., a rate of refresh slots dedicated to fixing victim word lines that are hammered by a row hammer. The timing circuits can be controlled to allow the steal rate to be independently adjusted for different victim word lines. Thus, different victim word lines can be refreshed at different rates, and the different rates can be independent of one another.

In some aspects, an apparatus includes a processing system comprising one or more processors and one or more memories coupled to the one or more processors. The processing system is configured to transmit one or more memory access commands to volatile memory. The one or more memory access commands are associated with a first address. If the processing system is further configured to access a physical adjacent row mapping table to determine at least a second address based on detecting a row hammer state associated with the one or more memory access commands, the first address and the second address correspond to physically adjacent rows within the volatile memory. If the processing system is further configured to transmit one or more row refresh commands to the volatile memory based on the row hammer state, the one or more row refresh commands are associated with at least the second address.

This disclosure relates to the field of semiconductor technology, providing a memory and its operating method to mitigate the damage caused by row hammer attacks. The memory includes a memory array and a control circuit. The control circuit is configured to, upon meeting preset conditions, respond to a command address signal and a mode control signal to enter a first mode, whereby it begins updating the count memory cell corresponding to the active word line at a first moment, and begins pre-charging the active word line at a second moment, using the count data as the count value for row hammer refresh; or, upon not meeting preset conditions, respond to the command address signal and the mode control signal to enter a second mode, whereby it does not perform an update operation on the count memory cell corresponding to the active word line, and begins pre-charging the active word line at a second moment, using the activation count value of the active word line in a dynamic lookup table as the count value for row hammer refresh. This achieves a balance between flexible configuration and reliability assurance, mitigating the damage caused by row hammer attacks.

The present application relates to the technical field of semiconductor, especially to a semiconductor memory device and a forming method, the semiconductor memory device comprises a substrate; a plurality of active region structures defined on the substrate; a shallow trench isolation provided in the substrate, the shallow trench isolation surrounds the plurality of active region structures; a plurality of wire structures extending along a first direction in parallel to each other, the wire structure comprises a first region and a second region, the first region is located above the active region structure, and the second region is located above the shallow trench isolation; in a direction perpendicular to the substrate, the first region has a greater depth than the second region. In this way, the row hammer effect can be avoided.

In an embodiment, a system employs encryption on memory addresses generated by a source circuit that generates memory transactions (e.g., a processor such as a central processing unit (CPU), a graphics processing unit (GPU), various embedded processors or microcontrollers; or a peripheral device. The encrypted memory address corresponds to the row that is activated for the memory transaction, instead of the memory address generated by the source circuit.

Systems, methods, and devices are described for memory device security and row hammer mitigation. Control mechanisms can be implemented in a front-end and / or back-end of a memory subsystem to flush rows of the memory. A row activate command can be received at control circuitry of a memory subsystem with a row address and increment a first count of a row counter stored in a content addressable memory (CAM) of the memory subsystem corresponding to the row address. The control circuitry can determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count can be incremented each time the CAM has been full. When it is determined that the first count is greater than the RHT minus the second count, a flush command can be issued to the row address.

A memory device and an operating method thereof are disclosed. The memory device can include a memory bank including a plurality of memory blocks each divided into a normal area and a row hammer area; a command control circuit adapted to perform an access operation on the normal area in response to an activation command; an internal command generation circuit adapted to generate an internal command in response to a precharge command; a target address generation circuit adapted to save a count of combinations of logical levels of a received address in the row hammer area by performing an access operation on the row hammer area in response to the internal command, and set an address corresponding to the count as a target address when the count satisfies a preset condition; and a refresh control circuit adapted to control an intelligent refresh operation on the target address.

A semiconductor memory device comprising: a memory cell array including a target memory cell row; and a row hammer management circuit, comprising a hammer address queue, configured to: receive an active command associated with the target memory cell row; compare a target count data associated with the target memory cell row with a first reference number, wherein the target count data represents a number of times the target memory cell row have been accessed; store a target row address of the target memory cell row as one candidate hammer address among candidate hammer addresses in the hammer address queue based on the target count data being equal to or greater than the first reference number; generate a random target count data, the event signal representing a state of the hammer address queue; and store the random target count data in the target count cell.

Row hammer is mitigated by issuing, to a memory device, mitigation operation (MOP) commands in order to cause the refresh of rows at a specified vicinity of a suspected aggressor row. These mitigation operation commands are each associated with respective row addresses that indicate the suspected aggressor row and an indicator of which neighbor row in the vicinity of the suspected aggressor row is to be refreshed. The mitigation operation commands are issued in response to a fixed number of activate commands. The suspected aggressor row is selected by randomly choosing, with equal probability, one of the N previous activate commands to supply its associated row address as the suspected aggressor row address. The neighbor row may be selected randomly with a probability that diminishes inversely with the distance between the suspected aggressor row and the neighbor row.

The present disclosure relates to a structure of a semiconductor memory device capable of mitigating the row hammer effect that occurs by repeated access to word lines. A semiconductor memory device according to an embodiment of the present disclosure includes a substrate, an element isolation film formed to extend in a vertical direction in the substrate, and a first gate structure formed to extend in the vertical direction in the element isolation film, and a second gate structure formed to be spaced apart from the element isolation film in a horizontal direction and extend in the vertical direction in the substrate, wherein a hollow pocket is formed below the first gate structure in the element isolation film.

Methods, systems, and apparatuses for memory devices (e.g., DRAM) including one or more reserved rows for row-copy operations are described. Such a memory device may include a memory array having a set of rows, where one or more rows of the set are reserved for row-copy operations and hidden (un-addressable) from access commands directed to the memory array. The reserved rows may include a dummy row configured to provide a uniform processing conditions to the memory array. Additionally, or alternatively, the reserved rows may include a buffer row configured to provide a buffer zone in the memory array. In some embodiments, the memory device may perform the row-copy operations in response to detecting row hammering activities. The row-copy operations may mitigate the risks associated with the row hammering activities by routing the row hammering activities to the reserved rows.

This application relates to row hammer attack mitigation using a victim cache. Row hammer attacks exploit unexpected and undesirable side effects of memory devices, where memory cells interact electrically with each other through leaky charge and may alter the contents of nearby memory lines not addressed in the original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to a cache line of the cache. The least recently used cache line of the cache is written to the victim cache.

Devices, systems, and methods for row-based cache locking. The memory controller may include intruder detector circuitry that determines whether an address is an intruder address. The controller may include tracker circuitry that counts the number of times an address is identified as an intruder and determines, based on the count, whether the intruder address is a frequent intruder address. If the address is a frequent intruder address, then cache entries associated with the frequent intruder address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker that determines whether the frequent intruder address is a high-attack address. The address mapping associated with the high-attack address may be modified.

Managing row hammering in a DRAM device may include maintaining per-row activation command counts. A next aggressor row may be determined based on the counts. A victim queue may be maintained. A refresh operation may be directed to a row indicated by the victim queue when conditions include that the victim queue is not empty when the refresh command is received. The current aggressor row may be updated with the next aggressor row when conditions include that the victim queue is empty when the refresh command is received. Following updating the current aggressor row, the count of the next aggressor row may be updated. A victim row corresponding to the current aggressor row may be added to the victim queue if the victim queue is empty when the refresh command is received.

The present invention relates to a memory system. The memory system comprises a normal memory area adapted to store normal data, a secure memory area adapted to store secure data, a first row hammer detection circuit adapted to sample and count activated partial rows in the normal memory area to select a first row to be refreshed, and a second row hammer detection circuit adapted to count all activated rows in the secure memory area to select a second row to be refreshed.

Methods and apparatus for row hammer (RH) mitigation and recovery. A host comprising a memory controller is configured to interface with one or more DRAM devices, such as DRAM DIMMs. The memory controller includes host-side RH mitigation logic and the DRAM devices include DRAM-side RH mitigation logic that cooperates with the host-side RH mitigation logic to perform RH mitigation and / or recovery operations in response to detection of RH attacks. The memory controller and DRAM device are configured to support an RH polling mode under which the memory controller periodically polls for RH attack detection indicia on the DRAM device that is toggled when the DRAM device detects an RH attack. The memory controller and DRAM device may also be configured to support an RH ALERT_n mode under which the use of an ALERT_n signal and pin is used to provide an alert to the memory controller to initiate RH mitigation and / or recovery.

A refresh control method includes: generating a first random number; and preforming, in response to execution times of a regular refresh operation reaching the first random number after execution of a previous row hammer refresh operation, a new row hammer refresh operation.

A semiconductor memory, a refresh method and an electronic device are provided. The semiconductor memory includes a main storage area and a mark storage area, multiple storage rows are arranged in the main storage area, and multiple first flag bits are arranged in the mark storage area. Each storage row has a correspondence with one first flag bit, and the first flag bit is used for indicating whether the storage row is an aggressor row of a row hammer event.

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

The present application relates to apparatus, systems, and methods for row hammer detector circuit reset. A row hammer detector circuit includes a hash circuit configured to store a hash key and provide a first count value based on a hash between the hash key and a row address corresponding to a row of memory cells of a memory array. The row hammer detector circuit is configured to provide a match signal to cause a targeted refresh of a victim row adjacent to the row of memory cells in response to the count value exceeding a threshold. In response to an exit from a self-refresh mode, the hash circuit is configured to update the stored hash key with a new hash key.

The application discloses a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate; forming a first word line structure in the first direction in the substrate; etching the substrate downward to form columnar active regions, the depth of the columnar active regions being greater than the depth of the first word line structure; filling an isolation layer between the columnar active regions; etching the first word line structure and the isolation layer to form a first word line trench in the first direction, the first word line trench penetrating through the columnar active regions; forming a low dielectric constant layer, a first conductive layer and an insulating layer in the first word line trench, the first conductive layer being electrically connected with the first word line structure. Since the first word line structure does not exist in the isolation layer, the semiconductor structure is separated by the filled isolation layer and the low dielectric constant layer between adjacent memory cells, and it is difficult for electrons to migrate from one memory cell to the adjacent memory cell, so that the row hammering effect caused by the electron migration is weakened.