87 results about "Row hammer" patented technology

The invention relates to the technical field of computers, in particular to a DRAM row hammering test method and device, electronic equipment and a chip, the method is executed in a DRAM controller in a hardware logic mode, and the method comprises the steps that a data writing request for a row to be tested is generated according to a preset data mode, the data writing request is converted into a writing command sequence, and the writing command sequence is sent to DRAM particles; generating an attack request for an attack line according to a preset attack mode, converting the attack request into a line activation and pre-charging command sequence, and sending the line activation and pre-charging command sequence to the DRAM particles; and reading data of the to-be-detected row in the DRAM particles, comparing the data with initially written data to detect whether bit flipping occurs, and determining the row subjected to bit flipping as a damaged row. According to the embodiment of the invention, the test efficiency and reliability can be effectively improved.

The invention relates to the technical field of semiconductors, and provides a memory and an operation method thereof, which are used for relieving harm caused by line hammering. The memory comprises a memory array and a control circuit. The control circuit is configured to enter a first mode in response to a command address signal and a mode control signal when a preset condition is met, execute an updating operation on a counting storage unit corresponding to an activated word line at a first moment, execute a pre-charging operation on the activated word line at a second moment, and take counting data as a counting value of row hammer refreshing; or, responding to the command address signal and the mode control signal when the preset condition is not met, entering a second mode, not executing the updating operation on the counting storage unit corresponding to the activated word line, and starting to execute the pre-charging operation on the activated word line at a second moment, and taking an activation count value of an activation word line in the dynamic lookup table as a count value of row hammer refreshing. In this way, balance is achieved between flexible configuration and reliability guarantee, and harm caused by hammering is relieved.

The invention relates to the technical field of computers, in particular to a DRAM (Dynamic Random Access Memory) line hammering defense method, device and system, a chip and electronic equipment. The method is applied to a DRAM (Dynamic Random Access Memory) controller and comprises the following steps: acquiring a row identifier of a row activation command for requesting a DRAM; when the row identifier does not exist in an entry container and the entry container is not full, storing the row identifier and a corresponding activation count in the entry container; under the condition that the row identifier does not exist in an entry container and the entry container is full, replacing one entry in the entry container with an entry attribute of a new row identifier based on an activation count and / or an access time sequence recorded in the entry container; and under the condition that any activation count in the entry container exceeds a row activation threshold value, determining the corresponding row as an attack row hammered by the row, and executing defense. According to the embodiment of the invention, chip area overhead and related power consumption can be effectively reduced.

The present disclosure provides a refresh method and device, relating to the field of semiconductor technology. The method includes: obtaining an activation count value of a currently activated row address of a memory within a preset duration; if the activation count value belongs to any one of multiple count intervals that exceeds a row hammer threshold, determining whether a preset queue is full; wherein the queue is used to store row addresses that require a row hammer refresh operation; when the queue is not full, placing the row address in the queue, and determining a range of victim row addresses corresponding to the row address based on a target count interval to which the activation count value belongs, and refreshing the victim row address; when the queue is full, performing one of the preset operations, which includes adding 1 to the activation count value. The present disclosure can effectively ensure the stability of the memory.

Linear feedback shift registers (LFSRs) are described that are used to generate bounded random numbers (e.g., the range of random numbers is narrower than the range of random numbers generated by a conventional LFSR having the same width). In one embodiment, a bounded LFSR for generating n-bit values includes an m-bit LFSR that ranges over 2 m m random numbers and an n-m-bit LFSR that ranges over 2 n‑m n-m-1-k random numbers. The bounded LFSR further includes logic for skipping over k values in a repeatable sequence of the n-m-bit LFSR, e.g., the logic can be configured during design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on outputs of the m-bit LFSR and the n-m-bit LFSR. In one embodiment, the bounded random numbers generated by the bounded LFSR are used as random addresses in a row hammer mitigation system.

Disclosed is a memory device including a count circuit suitable for: generating a plurality of group selection signals corresponding to a plurality of address groups by counting, in units of the address groups, a number of times that each of a plurality of address signals is inputted to the memory device, wherein each of the address groups corresponds to one or more address signals from the plurality of address signals, and selecting a target group from the address groups, the target group corresponding to a greatest one of the numbers for the respective address groups, and a sampling circuit suitable for randomly sampling a target address signal from the target group based on the plurality of group selection signals and the plurality of address signals.

Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.

Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

Methods for adjusting row hammer refresh rates and related memory devices and systems are disclosed. A method can include determining a number of valid commands associated with at least one bank of a memory device during a first time interval. The method can further include adjusting a row hammer refresh rate for the at least one bank for a second time interval based on the number of valid commands associated with the at least one bank during the first time interval.

To provide a semiconductor memory in which row hammer refresh operation can be performed without deteriorating performance of normal refresh operation.SOLUTION: A semiconductor memory device includes a control unit 10 which performs control so as to perform normal refresh operation for simultaneously refreshing memory cells connected to each of a plurality of word lines in response to a refresh request, and performs control so as to perform row hammer refresh operation each time the normal refresh operation is performed at least once.SELECTED DRAWING: Figure 2

Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

Aspects disclosed include a memory system with interleaved row refresh to address row hammer degradation. The memory system includes a refresh control circuit and a memory block. The memory block includes a first plurality of memory cell rows and a second plurality of memory cell rows, wherein the first plurality of memory cell rows is spatially interleaved with the second plurality of memory cell rows. In response to receiving a first number of commands to open the first plurality of memory cell rows which exceed a first threshold, the refresh control circuit is configured to refresh the second plurality of memory cell rows. The memory system advantageously addresses the known problem of row hammering while not expending energy refreshing the first plurality of memory cell rows, in contrast to conventional approaches which refresh all the rows.

An apparatus can include a refresh control circuit having a plurality of timing circuits. The timing circuits can be used to control a steal rate, e.g., a rate of refresh slots dedicated to fixing victim word lines that are hammered by a row hammer. The timing circuits can be controlled to allow the steal rate to be independently adjusted for different victim word lines. Thus, different victim word lines can be refreshed at different rates, and the different rates can be independent of one another.

A memory device can internally track row address activates for perfect row hammer tracking, incrementing an activate count for each row when an access command is received for a row. Instead of incrementing the count for each activate, the memory controller can indicate a number greater than one for the memory device to increment the count, and then indicate not to increment the count for subsequent accesses up to the number indicated. The memory controller can determine whether the row address of an activate command is one of N recent row addresses that received the access command. The memory controller can indicate an increment of zero if the row address is one of the N recent addresses, and indicate an increment of a number higher than one if the row address is not one of the N recent addresses.

Examples include techniques for a memory module per row activate counter. The techniques include detecting a row hammer or row disturb condition for a row address at a volatile memory device if an activate count to the row address matches a threshold count. The activate count is maintained by a controller for the memory module. Detection of the row hammer or row disturb condition can cause refresh management actions to mitigate the row hammer or row disturb condition.

The application provides a refresh circuit, a refresh method, a memory and a storage system. The refresh circuit comprises: a counting unit configured to count an external pulse signal received and reset a counting value in response to a row hammer refresh command; a random unit configured to generate a first random number before the counting unit outputs the counting value; and a first generation unit connected to the counting unit and the random unit, configured to obtain the counting value generated by the counting unit and a plurality of first random numbers generated by the plurality of random units, wherein the first random numbers generated by different random units are different; the first generation unit is further configured to output a sampling pulse when the counting value is equal to any first random number; a second generation unit connected to the first generation unit, configured to obtain a corresponding access address when the sampling pulse is received, and generate a row hammer address based on at least one obtained access address; and a refresh unit configured to refresh at least one row address adjacent to the row hammer address in response to a next row hammer refresh command.

A semiconductor device includes a redundancy control signal generation circuit configured to generate a redundancy control signal by determining whether a row address for an active operation has been repaired through a soft post package repair operation and determining whether a row hammer phenomenon has occurred with respect to the row address. The semiconductor device also includes a first selection address generation circuit configured to generate a first selection address for driving a sub word line or a redundancy word line from one of a repair address and a first internal address, based on the redundancy control signal. The semiconductor device further includes a second selection address generation circuit configured to generate a second selection address for driving the sub word line or the redundancy word line from one of a fixed address and a second internal address, based on the redundancy control signal.

In some aspects, an apparatus includes a processing system comprising one or more processors and one or more memories coupled to the one or more processors. The processing system is configured to transmit one or more memory access commands to volatile memory. The one or more memory access commands are associated with a first address. If the processing system is further configured to access a physical adjacent row mapping table to determine at least a second address based on detecting a row hammer state associated with the one or more memory access commands, the first address and the second address correspond to physically adjacent rows within the volatile memory. If the processing system is further configured to transmit one or more row refresh commands to the volatile memory based on the row hammer state, the one or more row refresh commands are associated with at least the second address.

Managing row hammers in a DRAM device may include maintaining a per-row activation command count. A next aggressor row may be determined based on the count. A victim queue may be maintained. When the condition includes that the victim queue is not empty when the refresh command is received, the refresh operation may be directed to a row indicated by the victim queue. When the condition includes that the victim queue is empty when the refresh command is received, the current aggressor row may be updated with the next aggressor row. After updating the current aggressor row, the count of the next aggressor row may be updated. If the victim queue is empty when the refresh command is received, a victim row corresponding to the current aggressor row may be added to the victim queue.

This disclosure relates to the field of semiconductor technology, providing a memory and its operating method to mitigate the damage caused by row hammer attacks. The memory includes a memory array and a control circuit. The control circuit is configured to, upon meeting preset conditions, respond to a command address signal and a mode control signal to enter a first mode, whereby it begins updating the count memory cell corresponding to the active word line at a first moment, and begins pre-charging the active word line at a second moment, using the count data as the count value for row hammer refresh; or, upon not meeting preset conditions, respond to the command address signal and the mode control signal to enter a second mode, whereby it does not perform an update operation on the count memory cell corresponding to the active word line, and begins pre-charging the active word line at a second moment, using the activation count value of the active word line in a dynamic lookup table as the count value for row hammer refresh. This achieves a balance between flexible configuration and reliability assurance, mitigating the damage caused by row hammer attacks.

A hybrid tracker system and method are disclosed for RH mitigation, which combines the best of both SRAM and DRAM to enable low-cost mitigation of RH at ultra-low thresholds. The system consists of two structures. First, an SRAM-based structure is provided that tracks aggregated counts at the granularity of a group of rows and is sufficient for the vast majority of rows, which receive only a few activations. Second, a per-row tracker stored in the DRAM-array is provided which can track an arbitrary number of rows; however, to limit performance overheads, this tracker is used only for the small number of rows that exceed the tracking capability of the SRAM-based structure.

The present application relates to the technical field of semiconductor, especially to a semiconductor memory device and a forming method, the semiconductor memory device comprises a substrate; a plurality of active region structures defined on the substrate; a shallow trench isolation provided in the substrate, the shallow trench isolation surrounds the plurality of active region structures; a plurality of wire structures extending along a first direction in parallel to each other, the wire structure comprises a first region and a second region, the first region is located above the active region structure, and the second region is located above the shallow trench isolation; in a direction perpendicular to the substrate, the first region has a greater depth than the second region. In this way, the row hammer effect can be avoided.

A memory device includes: a memory cell array connected to a plurality of word lines; and a row hammer protector including processing circuitry configured to activate a count for each of the plurality of word lines based on an adjacent word line activation count for each of the plurality of word lines during a first bank refresh period, an additional refresh operation is probabilistically performed for each of the plurality of word lines within a second bank refresh period following the first bank refresh period.

In an embodiment, a system employs encryption on memory addresses generated by a source circuit that generates memory transactions (e.g., a processor such as a central processing unit (CPU), a graphics processing unit (GPU), various embedded processors or microcontrollers; or a peripheral device. The encrypted memory address corresponds to the row that is activated for the memory transaction, instead of the memory address generated by the source circuit.

The invention relates to row hammer protection for memory devices. A memory device may identify a threshold for related row accesses of a memory array (e.g., access commands or activations for the same row address or row address space). In a first mode of operation, the memory device may execute commands received from a host device on the memory array. The memory device may determine that a metric for the received row access command satisfies the threshold for a related row access. The memory device may switch the memory array from the first mode of operation to a second mode of operation based on the threshold being satisfied. The second mode of operation may constrain access to at least one row of the memory, while the first mode may have a lower constraint. Additionally or alternatively, the memory device may notify the host device that the metric has met the threshold.

Systems, methods, and devices are described for memory device security and row hammer mitigation. Control mechanisms can be implemented in a front-end and / or back-end of a memory subsystem to flush rows of the memory. A row activate command can be received at control circuitry of a memory subsystem with a row address and increment a first count of a row counter stored in a content addressable memory (CAM) of the memory subsystem corresponding to the row address. The control circuitry can determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count can be incremented each time the CAM has been full. When it is determined that the first count is greater than the RHT minus the second count, a flush command can be issued to the row address.

A memory device and an operating method thereof are disclosed. The memory device can include a memory bank including a plurality of memory blocks each divided into a normal area and a row hammer area; a command control circuit adapted to perform an access operation on the normal area in response to an activation command; an internal command generation circuit adapted to generate an internal command in response to a precharge command; a target address generation circuit adapted to save a count of combinations of logical levels of a received address in the row hammer area by performing an access operation on the row hammer area in response to the internal command, and set an address corresponding to the count as a target address when the count satisfies a preset condition; and a refresh control circuit adapted to control an intelligent refresh operation on the target address.

A semiconductor memory device comprising: a memory cell array including a target memory cell row; and a row hammer management circuit, comprising a hammer address queue, configured to: receive an active command associated with the target memory cell row; compare a target count data associated with the target memory cell row with a first reference number, wherein the target count data represents a number of times the target memory cell row have been accessed; store a target row address of the target memory cell row as one candidate hammer address among candidate hammer addresses in the hammer address queue based on the target count data being equal to or greater than the first reference number; generate a random target count data, the event signal representing a state of the hammer address queue; and store the random target count data in the target count cell.

Row hammer is mitigated by issuing, to a memory device, mitigation operation (MOP) commands in order to cause the refresh of rows at a specified vicinity of a suspected aggressor row. These mitigation operation commands are each associated with respective row addresses that indicate the suspected aggressor row and an indicator of which neighbor row in the vicinity of the suspected aggressor row is to be refreshed. The mitigation operation commands are issued in response to a fixed number of activate commands. The suspected aggressor row is selected by randomly choosing, with equal probability, one of the N previous activate commands to supply its associated row address as the suspected aggressor row address. The neighbor row may be selected randomly with a probability that diminishes inversely with the distance between the suspected aggressor row and the neighbor row.