19 results about "Row hammer" patented technology

Linear feedback shift registers (LFSRs) are described that are used to generate bounded random numbers (e.g., the range of random numbers is narrower than the range of random numbers generated by a conventional LFSR having the same width). In one embodiment, a bounded LFSR for generating n-bit values includes an m-bit LFSR that ranges over 2 m m random numbers and an n-m-bit LFSR that ranges over 2 n‑m n-m-1-k random numbers. The bounded LFSR further includes logic for skipping over k values in a repeatable sequence of the n-m-bit LFSR, e.g., the logic can be configured during design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on outputs of the m-bit LFSR and the n-m-bit LFSR. In one embodiment, the bounded random numbers generated by the bounded LFSR are used as random addresses in a row hammer mitigation system.

Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

An apparatus can include a refresh control circuit having a plurality of timing circuits. The timing circuits can be used to control a steal rate, e.g., a rate of refresh slots dedicated to fixing victim word lines that are hammered by a row hammer. The timing circuits can be controlled to allow the steal rate to be independently adjusted for different victim word lines. Thus, different victim word lines can be refreshed at different rates, and the different rates can be independent of one another.

In some aspects, an apparatus includes a processing system comprising one or more processors and one or more memories coupled to the one or more processors. The processing system is configured to transmit one or more memory access commands to volatile memory. The one or more memory access commands are associated with a first address. If the processing system is further configured to access a physical adjacent row mapping table to determine at least a second address based on detecting a row hammer state associated with the one or more memory access commands, the first address and the second address correspond to physically adjacent rows within the volatile memory. If the processing system is further configured to transmit one or more row refresh commands to the volatile memory based on the row hammer state, the one or more row refresh commands are associated with at least the second address.

This disclosure relates to the field of semiconductor technology, providing a memory and its operating method to mitigate the damage caused by row hammer attacks. The memory includes a memory array and a control circuit. The control circuit is configured to, upon meeting preset conditions, respond to a command address signal and a mode control signal to enter a first mode, whereby it begins updating the count memory cell corresponding to the active word line at a first moment, and begins pre-charging the active word line at a second moment, using the count data as the count value for row hammer refresh; or, upon not meeting preset conditions, respond to the command address signal and the mode control signal to enter a second mode, whereby it does not perform an update operation on the count memory cell corresponding to the active word line, and begins pre-charging the active word line at a second moment, using the activation count value of the active word line in a dynamic lookup table as the count value for row hammer refresh. This achieves a balance between flexible configuration and reliability assurance, mitigating the damage caused by row hammer attacks.

Systems, methods, and devices are described for memory device security and row hammer mitigation. Control mechanisms can be implemented in a front-end and / or back-end of a memory subsystem to flush rows of the memory. A row activate command can be received at control circuitry of a memory subsystem with a row address and increment a first count of a row counter stored in a content addressable memory (CAM) of the memory subsystem corresponding to the row address. The control circuitry can determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count can be incremented each time the CAM has been full. When it is determined that the first count is greater than the RHT minus the second count, a flush command can be issued to the row address.

Row hammer is mitigated by issuing, to a memory device, mitigation operation (MOP) commands in order to cause the refresh of rows at a specified vicinity of a suspected aggressor row. These mitigation operation commands are each associated with respective row addresses that indicate the suspected aggressor row and an indicator of which neighbor row in the vicinity of the suspected aggressor row is to be refreshed. The mitigation operation commands are issued in response to a fixed number of activate commands. The suspected aggressor row is selected by randomly choosing, with equal probability, one of the N previous activate commands to supply its associated row address as the suspected aggressor row address. The neighbor row may be selected randomly with a probability that diminishes inversely with the distance between the suspected aggressor row and the neighbor row.

This application relates to row hammer attack mitigation using a victim cache. Row hammer attacks exploit unexpected and undesirable side effects of memory devices, where memory cells interact electrically with each other through leaky charge and may alter the contents of nearby memory lines not addressed in the original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to a cache line of the cache. The least recently used cache line of the cache is written to the victim cache.

A refresh control method includes: generating a first random number; and preforming, in response to execution times of a regular refresh operation reaching the first random number after execution of a previous row hammer refresh operation, a new row hammer refresh operation.

The application discloses a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate; forming a first word line structure in the first direction in the substrate; etching the substrate downward to form columnar active regions, the depth of the columnar active regions being greater than the depth of the first word line structure; filling an isolation layer between the columnar active regions; etching the first word line structure and the isolation layer to form a first word line trench in the first direction, the first word line trench penetrating through the columnar active regions; forming a low dielectric constant layer, a first conductive layer and an insulating layer in the first word line trench, the first conductive layer being electrically connected with the first word line structure. Since the first word line structure does not exist in the isolation layer, the semiconductor structure is separated by the filled isolation layer and the low dielectric constant layer between adjacent memory cells, and it is difficult for electrons to migrate from one memory cell to the adjacent memory cell, so that the row hammering effect caused by the electron migration is weakened.

An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

A method and apparatus for mitigating row hammer attacks is provided. A row hammer alert is generated by a component of a memory architecture controlling operation of a memory device. The component may be a memory controller, coherency logic, or data fabric. The component obtains a physical address of an aggressor row that caused the alert and obtains an identifier of an execution context corresponding to the physical address. The component generates an error message for a processing device, the error message including the identifier of the execution context. The processing device retrieves the error message when performing a context switch. The processing device then generates an event received by the operating system. The operating system then takes action to reduce row hammer by the execution context, such as ending, restarting, or throttling the execution context.

Methods, apparatuses, and systems related to detecting and mitigating waterfall attacks are described. A memory device may include a waterfall attack mitigation circuit that is configured to detect, based on the ratio of read commands to write command received by the memory device, whether the memory device is the target of a waterfall attack. Upon detecting that the memory device is the target of a waterfall attack, the waterfall attack mitigation circuit can initiate certain mitigation actions, such as adjusting a threshold used to perform row hammer-related refreshes.

The present disclosure relates to devices and methods for control of refresh operations. In some examples, a memory device can perform refresh operations in response to internal and / or external commands. Internal refresh commands can include an auto-refresh command and a row hammer (e.g., targeted) refresh command. External commands can include a refresh management command. In some examples, the external command can cause a refresh operation to occur after a number of activate commands. The memory device can monitor row addresses associated with the activate commands. In some examples, if none of the row addresses associated with the activate commands are generated at a high frequency, the memory device can skip a refresh operation indicated by a refresh management command. In some examples, a row address can be determined to be an aggressor row address if a received row address matches a previously received row address.

A device configured to communicate with a host includes a volatile memory including a plurality of memory cell rows; and a memory controller configured to detect, based on input row addresses accessed by the host, a pattern size of a row hammer attack pattern and a row distribution of row hammer addresses in the row hammer attack pattern; to determine, according to a type of the row distribution, whether to perform refresh management, the type of the row distribution including a uniform type or non-uniform type; and for every L access corresponding to the pattern size, to provide, to the volatile memory, a refresh management command according to the refresh management and a target row address corresponding to a target memory cell row from among the plurality of memory cell rows, in which L is an integer greater than or equal to 1.

Methods, systems, and devices for per row hammer tracking array structure are described. A memory system may determine a quantity of columns of a memory array that have respective writeback times that satisfy a threshold duration for storing a row access count. The memory device may activate a first row of the memory array, the first row corresponding to a first row address. The memory device may activate a redundant column to perform a first access operation on a set of data bits associated with a first column address corresponding to a first column of the memory array. Then, the memory device may activate the first column of the memory array to perform a second access operation on a set of counter bits of a counter circuit that includes a count value corresponding to a quantity of accesses at the first row.

A system and method for performing a low overhead refresh management of a memory device. The method includes receiving, by a controller from a dynamic random access memory (DRAM) device via a feedback interface, a signal indicative of an occurrence of a row hammer event. The method includes determining, by the controller based on the signal, whether to schedule a refresh event. The method includes sending, by the controller responsive to determining whether to schedule the refresh event, a first command to the DRAM device to execute a refresh operation.