Dram and method for accessing a dram

a dram and access method technology, applied in the field of dram and access method, can solve the problems of increasing the refresh rate of a dram, low number of accesses, and relatively low performance of a dram, and achieve the effects of increasing the refresh rate of a dram, low dram performance, and a hammer

Active Publication Date: 2018-07-10
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0018]In some comparative approaches, a row hammer effect may be alleviated or eliminated by limiting number of accesses on a word line of a DRAM in a given period. For example, the number of accesses of the word line is limited to less than 300,000 accesses in a given period. As a result, the word line is not subject to a row hammer effect. However, a relatively low number of accesses may be accompanied by a relatively low performance of the DRAM.
[0019]Alternatively, in some comparative approaches, a row hammer effect may be alleviated or eliminated by increasing a refresh rate of a DRAM. In further detail, to refresh memory cells of the DRAM, in a refresh operation, a data will be read from the memory cells and subsequently written back to the memory cells, so as to avoid losing the data. When the refresh rate is relatively high, the refresh operation is performed a relatively large number of times in a period, which ensures that a data in the present timing is the same as that in the previous timing. That is, it is ensured that the data is not subject to flip. As a result, an ability to resist a row hammer effect is relatively good. However, the DRAM will consume more power when the refresh rate is relatively high.

Problems solved by technology

However, a relatively low number of accesses may be accompanied by a relatively low performance of the DRAM.
However, the DRAM will consume more power when the refresh rate is relatively high.

Method used

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Embodiment Construction

[0036]Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.

[0037]It shall be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component...

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Abstract

The present disclosure provides a method. The method includes copying a data stored in memory cells associated with a normal word line subject to a row hammer effect into memory cells associated with a hot word line before a condition is satisfied, wherein the condition includes an access frequency of the normal word line reaching a threshold frequency; accessing, based on a logical address, the normal word line before the condition is satisfied; accessing, based on the logical address, the hot word line associated with the copied data only if the condition is satisfied; and accessing the data no longer from the normal word line only if the condition is satisfied.

Description

TECHNICAL FIELD[0001]The present disclosure relates to a dynamic random access memory (DRAM), and more particularly, to a DRAM and method for accessing a DRAM.DISCUSSION OF THE BACKGROUND[0002]Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor. A simplest DRAM cell comprises a single N-type metal-oxide-semiconductor (NMOS) transistor and a single capacitor. If charges are stored in the capacitor, the cell is said to store a logic HIGH, depending on the convention used. If no charge is present, the cell is said to store a logic LOW. Because the charges in the capacitor dissipate over time, DRAM systems require additional refreshing circuitries to periodically refresh the charges stored in the capacitors. Since a capacitor can store only a very limited amount of charges, in order to quickly distinguish the difference between a logic 1 and a logic 0, two bit lines (BLs) are typically used for each bit, wherein the ...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G11C11/24G06F12/02G11C11/408G06F12/06
CPCG06F12/0207G06F12/0607G11C11/408G06F12/0246G11C11/406G11C11/4076G11C2207/2236G06F12/0292G06F2212/1032
Inventor LEE, CHUNG-HSUNLIU, HSIEN-WEN
Owner NAN YA TECH
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