91results about How to "Reduce performance" patented technology

Measuring a property of a layer in multilayered structure

An apparatus measures a property of a layer (such as the sheet resistance of a conductive layer or thermal conductivity of a dielectric layer that is located underneath the conductive layer) by performing the following method: (1) focusing the heating beam on the heated a region (also called “heated region”) of the conductive layer (2) modulating the power of the heating beam at a predetermined frequency that is selected to be sufficiently low to ensure that at least a majority (preferably all) of the generated heat transfers out of the heated region by diffusion, and (3) measuring the power of another beam that is (a) reflected by the heated region, and (b) modulated in phase with modulation of the heating beam. The measurement in act (3) can be used directly as a measure of the resistance (per unit length) of a conductive line formed by patterning the conductive layer. Acts (1)-(3) can be repeated during fabrication of a semiconductor wafer, at each of a number of regions on a conductive line, and any change in measurement indicates a corresponding change in resistance of the line. When the measurement changes by more than a predetermined amount (e.g. by 10%), a process parameter that controls the fabrication process is changed to return the measurement to normal in the next wafer. Moreover, the thermal conductivity of the dielectric layer can be measured, or monitored for changes beyond a predetermined limit during a scan across the wafer, if resistance is known.

Multi-pair gigabit ethernet transceiver

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
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