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167results about How to "Reduce storage capacity" patented technology

Image processing circuit, image display apparatus, and image processing method

Aspects of the invention can provide an image processing circuit for gray scale correction, an image display apparatus, and an image processing method that allow reduction in the storage capacity needed for storing correction characteristics data without increasing clock rate in relation to interpolation processing of correction characteristics. A exemplary image processing circuit according to the invention can be applied, for example, to color correction or gamma correction of color image data. Gray scale correction characteristics data for a number of gray scale levels that is less than the number of gray scale levels of input image data can be stored in first and second lookup table storing units. Considering a gray scale value of a pixel that is being considered for gray scale correction processing as an input gray scale value, the first and second lookup-table storing units are referred to, obtaining an output gray scale value corresponding to the input gray scale value and an output gray scale value corresponding to an adjacent input gray scale value. An adjacent gray scale value refers to a gray scale value that is higher by one or lower by one than another input gray scale value. Then, output gray scale values between these two adjacent output gray scale values can be calculated by linear interpolation, obtaining output values for all input gray scale values. Subsequently, gray scale correction can be performed for each pixel of input image data, outputting corrected image data.
Owner:BOE TECH GRP CO LTD

High frequency power amplifier circuit and radio communication system

There is provided a high frequency power amplifier circuit capable of enhancing detection accuracy of an output level, necessary for feedback control of the high frequency power amplifier circuit, and capable of executing output power control with higher precision, With the high frequency power amplifier circuit, the detection of the output level, necessary for feedback control of the high frequency power amplifier circuit is executed by use of a current detection method, and in an electronic device comprising a differential amplifier for comparing an output power detection signal with an output level designation signal and for generating a signal for controlling a gain of the high frequency power amplifier circuit according to a potential difference between the two signals, a power source voltage with variation less than that for the power source voltage of the high frequency power amplifier circuit is used as the operational power source voltage of the output power detection circuit. Further, there is provided a capacitor across which an AC component is taken out from the output side of a power amplification transistor in the final amplification stage of the high frequency power amplifier circuit to be thereby impressed to the interior of the output power detection circuit.
Owner:RENESAS TECH CORP

Method and device for reducing the processing time of data in communication networks

InactiveUS6948108B1Efficient data processingReduce memory space requirementsError prevention/detection by using return channelTransmission systemsGeneral Packet Radio ServiceData stream
The invention relates to a method and a device for improving the processing time of received data in packet oriented applications during a transmission via communication networks, in particular via an IP network and a mobile communication network such as the Global System for Mobile Communication (GSM), Universal Mobile Telecommunication System (UMTS) or General Packet Radio Service (GPRS). The received data packets of the second protocol layer, for instance, the RLP frames, are combined to form data packets of the first protocol layer, for instance to PPP frames, directly by the receiver in the second protocol layer. The completely and correctly combined data packets are then released to the first protocol layer. During the release of the data packets to the first protocol layer, a difference is made between two modes. The intra-flow mode is a mode, wherein all completely generated data packets are released, i.e. independent from whether the data packets belong to the same or to two different data flows. In contrast thereto, a difference is made in view of the inter-flow mode. In said mode only the completely generated data packets belonging to different data flows are released to the first protocol layer.
Owner:TELEFON AB LM ERICSSON (PUBL)
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