Method of manufacturing buried word lines and isolating structures thereof

A technology of embedded word lines and isolation structures, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as increased resistance, small component size, and impact on component performance, and achieve the effect of reducing interference

Active Publication Date: 2015-11-25
WINBOND ELECTRONICS CORP
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Problems solved by technology

[0006] However, because the size of the element itself is very small, it is likely to be caused by a small offset in the photolithography process. figure 2 the result of
exist figure 2 In , because the buried word line 106 is slightly shifted to the right, the area A2 of the contact region 112 becomes significantly smaller, which leads to an increase in the resistance value here and affects the performance of the device itself

Method used

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  • Method of manufacturing buried word lines and isolating structures thereof
  • Method of manufacturing buried word lines and isolating structures thereof
  • Method of manufacturing buried word lines and isolating structures thereof

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Embodiment Construction

[0051] In order that the concept of the invention may be more fully appreciated, reference is made herein to the accompanying drawings, in which embodiments of the invention are shown. However, the invention may also be practiced in many different forms and should not be construed as limited to the embodiments set forth below. Rather, the embodiments are provided only so that the present disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0052] In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

[0053] Figure 3A to Figure 3J It is a cross-sectional view of the manufacturing process of a buried word line and its isolation structure according to an embodiment of the present invention.

[0054] Please refer to Figure 3A A multi-layer structure 308 composed of a first nitride layer 302 , an oxide layer 304 and a second nitride layer 306 is formed on ...

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Abstract

A method of manufacturing buried word lines and isolating structures thereof comprises the following steps of forming a plurality of buried word lines inside a substrate, wherein the top of each buried word line is lower than the surface of the substrate; forming a mask structural layer inside a groove on each buried word line, making the mask structural layer protrude by removing a part of the structure so that side walls of the mask structural layer form distance pieces and a plurality of self-aligned grooves are further formed; removing substrate parts under the grooves in an etching way with the distance pieces and the mask structural layers as the etching masks so as to form a plurality of isolating structure grooves; and further forming isolating structures inside the isolating structure grooves. By means of the manufacturing method, interference (Row Hammer) among word lines can be effectively alleviated. Furthermore, the area of a contact zone inside an active region can be kept.

Description

technical field [0001] The invention relates to a method for manufacturing a buried word line and its isolation structure, and in particular to a method for manufacturing a self-aligned buried word line isolation structure. Background technique [0002] In order to increase the integration of DRAM to speed up the operation speed of components, and to meet the needs of consumers for miniaturized electronic devices, a buried word line DRAM (buried wordline DRAM) has been developed in recent years to meet the above-mentioned needs. [0003] However, as the density of memory increases, the pitch of word lines and the isolation structure of memory arrays will continue to shrink, resulting in various adverse effects. For example, cell-to-cell leakage between memories, interference between word lines (also known as RowHammer), read and write time failure (tWR failure), retention failure (retention failure), bit line coupling failure (BitLine coupling failure), etc. [0004] There...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762H01L21/768
Inventor 朴哲秀欧阳自明
Owner WINBOND ELECTRONICS CORP
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