Smart refresh device

Abstract

A smart refresh device includes an address control block configured to determine whether a specific row address is a row hammer address, and invert a first row hammer address and perform an addition / subtraction of an address; a repair control block configured to determine whether the row hammer address is a repaired address and output a stored repair address as a second repair control signal; a repair address storage block configured to store an output address of the address control block and output a stored address as a latch address; a fuse block configured to output a repair signal representing information on a repair address to the repair control block, and output a decoding signal according to the latch address; and an operator configured to add and subtract the decoding signal according to an addition signal and a subtraction signal.

Description

CROSS-REFERENCES TO RELATED APPLICATION[0001]The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2014-0127063, filed on Sep. 23, 2014, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.BACKGROUND[0002]1. Technical Field[0003]Various embodiments generally relate to a smart refresh device, and more particularly, to a technology for detecting a repair address and performing smart refresh, thereby improving a refresh characteristic.[0004]2. Related Art[0005]In general, a semiconductor memory device includes a number of memory cells. As processing technologies have been developed and thus the degree of integration is augmented, the number of memory cells gradually increases. If a fail occurs in even any one among memory cells, a corresponding semiconductor memory device misoperates. Therefore, since the semiconductor memory device including a failed cell cannot perform a desired operation, it ...

AI Technical Summary

Benefits of technology

The patent describes a device that can refresh and repair computer memory. The device includes an address control block that determines if a specific memory address is a hammer address, which can cause damage to the memory. If the address is a hammer address, the device stores a repair address and outputs it as a control signal for a second refresh cycle. The device also includes a repair address storage block that stores the output address of the address control block when the first refresh cycle is activated. The device can output the stored address as the latch address for the second refresh cycle. The device also includes a fuse block that outputs a repair signal to the address control block and a decoding block that outputs a repair signal based on the latch address. The device also includes an operator that can either add or subtract the repair signals based on the activation of a second repair control signal. The technical effect of this device is to enhance the reliability and longevity of computer memory by improving its refresh and repair capabilities.

Problems solved by technology

If a fail occurs in even any one among memory cells, a corresponding semiconductor memory device misoperates.

In this regard, as the coupling effect between adjacent word lines increases as described above, a phenomenon occurs, in which the data of a memory cell coupled with a word line adjacent to a frequently activated word line is damaged.

Due to the word line disturbance, a phenomenon occurs in which the data of a memory cell is damaged before the memory cell is refreshed.

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