127 results about "Address control" patented technology

The invention discloses a configurable number-theory transformation parallel computing acceleration method and device for a post quantum cryptographic algorithm, and relates to the technical field of cryptographic algorithms. The number theory transformation is a calculation bottleneck in lattice-based post-quantum cryptography and PQC; a hardware accelerator specially designed for number theory transformation (NTT) is an effective solution for improving the execution speed. At present, a mainstream design neglects the influence of the scale of a calculation array, so that the design of an NTT calculation circuit is poor in flexibility and low in memory utilization rate, and a two-dimensional reconfigurable number theory transformation acceleration circuit is provided; the method is applied to a key generation stage, an encryption stage and a decryption stage of the post-quantum cryptographic algorithm. The NTT reconfigurable computing circuit provided by the invention can keep the utilization rate of hardware resources, and is suitable for mobile terminal equipment with limited resources; the NTT circuit adopts a low-complexity memory mapping scheme, so that the address control logic is greatly simplified, and the hardware overhead is reduced.

Methods and systems for performing current sense compensation for one or more power stages in a multiphase voltage regulator are described. A controller can be connected to a plurality of power stages through a communication interface. The controller can generate a data packet including a command to obtain temperature information and an address that identifies a specific power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages using the communication interface. The controller can receive temperature information of the specific power stage from the specific power stage through the communication interface. The controller can compensate a sensed current of the specific power stage based on the received temperature information of the specific power stage.

The invention relates to the technical field of computer hardware testing, and discloses a testing method and device of storage equipment, electronic equipment and a storage medium, and the testing method comprises the steps that a write address control strategy is generated, and the write address control strategy is used for representing the write sequence of different addresses in the storage equipment; obtaining test data; and sequentially writing the test data into corresponding positions of the storage equipment according to a sequence defined by the write-in address control strategy. The technical problem of low reliability of the writing effect of the test storage device is solved, and the technical effect of improving the test accuracy of the storage device is achieved.

The invention relates to a thermal power generating unit space-time coupling control method based on a double-gating LSTM network, and the method comprises the steps: collecting the real-time data of a thermal power generating unit, including a target control variable and a plurality of coupling variables; real-time data of the thermal power generating unit are input into the double-gating LSTM network, and temperature curves and control parameters of a plurality of steps in the future are obtained through prediction; the double-gating LSTM network splits a forgetting gate of an LSTM into a short-term forgetting gate and a long-term forgetting gate, a short-term gating channel is started when the double-gating LSTM network is in a conventional working condition, and a long-term gating channel is started when the time delay exceeds a set time delay threshold value; generating a thermodynamic sensitivity weight matrix based on the thermodynamic sensitivity weight model, and driving the LSTM network to perform back propagation rolling optimization of parameters; and based on the output of the double-gate-control LSTM network, a secondary air door opening instruction of the fuel valve is generated through a model prediction controller. Compared with the prior art, the problem of control instability under complex working conditions such as deep peak regulation and coal type switching can be effectively solved.

The invention discloses a solid state disk-based data transmission method and device, a medium and a product, and relates to the field of solid state disks. According to the method, a data layout description header is obtained from a host memory in a direct memory access mode according to a target memory initial address; analyzing the data layout description header through a flash translation layer of the solid state disk, identifying each data segment entry, and extracting length information and life cycle attribute tags of corresponding data segments from each data segment entry; based on the life cycle attribute tag, planning a corresponding physical flash memory page for each data segment as a target write address of the data segment; and based on the target write-in address, controlling the solid state disk to execute DMA operation segment by segment according to the sequence of data segment entries in the data layout description head until the write-in of the total data length is completed. By implementing the technical scheme provided by the invention, the data storage efficiency of the solid state disk is improved.

This disclosure provides a method and apparatus for planning Equivalent Multipath (ECMP) load balancing. The method includes: a control device establishing a remote login connection with a device to be configured and setting up Equivalent Multipath (ECMP) to reach the destination device; sequentially traversing each hash algorithm in a hash algorithm list; controlling the device to be configured to switch to the currently traversed hash algorithm via the remote login connection, sending it a hash factor type, a set of candidate source IP addresses, and the IP address of the destination device; controlling the device to be configured to initiate the construction of multiple data packets based on the hash factor type, each with a candidate source IP address and a destination device IP address; causing the device to be configured to calculate and record the transmission ratio of each member path of ECMP associated with each candidate source IP address; and obtaining this ratio via the remote login connection to select service IP addresses for the device to be configured and load balance the data packets sent to the destination device based on the member paths selected by the hash algorithm from ECMP.

A bidirectional address allocation method and system are used for allocating independent addresses to N units awaiting address allocation of at least one module awaiting address allocation. A first serial data port of a controller, two serial data ports of each of the N units awaiting address allocation, and a second serial data port of the controller are sequentially connected in series. In the module awaiting address allocation, a direction starting from a unit awaiting address allocation connected to the first serial data port of the controller is a forward direction, and a direction from a unit awaiting address allocation connected to the second serial data port of the controller is a reverse direction. The method includes: performing forward address allocation; determining whether address allocation for the N units awaiting address allocation is completed; changing an input / output direction; and performing reverse address allocation.

The invention discloses a method for upgrading vehicle-mounted software in a rail transit vehicle and a related device, and relates to the technical field of rail transit. The method comprises the following steps: presetting a corresponding relationship among a compartment number, a vehicle-mounted equipment number and a vehicle-mounted equipment communication address; a corresponding relation among a compartment number, a vehicle-mounted equipment number and a storage address is preset. If the multiple pieces of vehicle-mounted equipment need to be uniformly updated, target vehicle-mounted equipment numbers corresponding to the multiple to-be-updated target compartment numbers respectively can be obtained; searching a target vehicle-mounted equipment communication address corresponding to the target compartment number and the target vehicle-mounted equipment number from the corresponding relation; searching a target storage address corresponding to the target compartment number and the target vehicle-mounted equipment number from the corresponding relationship; and controlling to display a vehicle-mounted software list corresponding to the target storage address. The user can determine a target version number from the vehicle-mounted software list; therefore, the purpose of uniformly sending the vehicle-mounted software corresponding to the target version number in the target storage address to the communication address of the target vehicle-mounted equipment is achieved.

The invention provides a security protection method for IPv6 network attacks, and relates to the technical field of Internet security. The method comprises the steps that a backbone network topology structure is built, the backbone network topology structure comprises an access layer router and a core layer router, and the access layer router and the core layer router are communicated in advance; a BGP4 + routing protocol is deployed based on the backbone network topology structure, and the BGP4 + routing protocol is used for enabling routers in the whole network in the backbone network topology structure to achieve BGP4 + routing reachability; an address control routing strategy is configured based on the backbone network topology structure, and the address control routing strategy is configured to be capable of notifying a forbidden target address to the whole network through a BGP4 + routing protocol; and in response to matching of the attack traffic with the target address in the access layer router, blocking the attack traffic to complete security protection. The invention further provides a security protection device for the IPv6 network attack, electronic equipment and a medium.

The invention discloses a scheduling-driven high-level comprehensive array division method, which comprises the following steps of: creating an associated access instruction set for arrays in algorithm design, and analyzing an address calculation expression of each access instruction; on the basis of the control data flow diagram designed by the algorithm, instruction scheduling is executed according to an instruction topological sequence and circuit performance requirements, for an array access instruction, a schedulable interval of the array access instruction is calculated, control steps in the interval are traversed, and incremental address conflicts introduced by each scheduling mode are determined; aiming at each scheduling mode of the array access instruction, a minimum overhead array division scheme capable of solving all address conflicts is searched, and the overhead of the division scheme comprehensively considers the number of storage modules after division, address control logic complexity and time delay; the address conflicts comprise the incremental address conflicts and the stock address conflicts. The method has the advantages that compared with an existing array division scheme, calculation scheduling and array division are organically combined, the cost of array division is reduced, and the scheduling performance is improved.

This invention relates to the field of peripheral control technology, specifically to a multi-chip addressing control method, electronic devices, storage media, and program products. The method includes: receiving a control request and generating a command packet containing a source address, a target address, and command data; splitting the command packet and sending it to different target chips under a synchronous control request, and sending the command packet according to the target address under an asynchronous control request; forwarding the command to the master control chip when the slave chip lacks execution capability; executing the command packet when both the master and slave chips receive the same command data; receiving a response packet and determining the responding chip based on the source address, and outputting the control result. This invention enables directional control, collaborative execution, and response differentiation in multi-chip peripherals.

Embodiments of the present application disclose a data access method, a data access system and a storage medium. After receiving a migration interrupt request sent by a target processing unit, a central processing unit of a processing unit cluster according to a virtual address of target data in the migration interrupt request controls the target processing unit to acquire an address mapping relationship of the target data, and controls a source processing unit to migrate the target data to the target processing unit, and then controls the target processing unit to update the address mapping relationship of the target data after the target data is migrated, so that the target processing unit reads the target data from the memory according to the updated address mapping relationship. In the embodiments of the present application, the target processing unit can access data in the source processing unit according to the received address mapping relationship without waiting for the data migration to be completed, so that the data access delay can be effectively reduced, and the data processing efficiency is improved.

In some implementations, a controller may detect a failure associated with data obtained, using a first physical address, from a current physical location of a non-volatile memory device. The controller may determine, based on detecting the failure, a virtual block number based on the first physical address. The controller may determine that the virtual block number identifies a garbage collection block. The controller may determine a virtual wordline of the garbage collection block. The controller may obtain, from the virtual wordline, a data log that identifies a second physical address for a previous physical location of the data. The controller may obtain, using the second physical address, the data from the previous physical location.

The application relates to a logic truth table acquisition method and device, electronic equipment and a storage medium, and belongs to the technical field of integrated circuits. The logic truth table acquisition method comprises the following steps: finding a register array from a netlist, wherein the register array comprises a plurality of registers; finding an enabling signal for controlling each register from the netlist; changing the value of an address control signal, and obtaining a logic truth table based on each enabling signal under different address control signals, wherein the logic truth table comprises the corresponding relationship between each enabling signal and the address control signal, and is used for determining the register corresponding to each enabling signal. The method can automatically find the enabling signal related to the register array from the netlist, change the value of the address control signal, obtain the logic truth table based on each enabling signal under different address control signals, and improve the problems of low efficiency and easy errors in manually acquiring the logic truth table of the register array.

This disclosure provides a controller, address management method, and system for a phase-change memory (PCM). The method includes: determining the address mapping mode of the PCM; if it is a static mapping mode, mapping a first source address to a first destination address based on a preset mapping table; if it is a dynamic mapping mode, matching a corresponding address mapping rule according to a dynamic scenario, and mapping a second source address to a second destination address based on the address mapping rule; if it is a hybrid mapping mode, mapping a third source address to a third destination address based on a preset mapping table, controlling the PCM to perform read operations based on the third destination address; and matching a corresponding address mapping rule according to a dynamic scenario, mapping a fourth source address to a fourth destination address based on the address mapping rule, and controlling the PCM to perform write operations based on the fourth destination address. This application can reduce the read latency of the PCM, improve the write performance and media lifetime of the PCM, and achieve a balance between read and write performance.

Embodiments provide a memory device whose chip size is not limited by the size of a peripheral circuit. A memory device of an embodiment has: a first chip; and a second chip disposed on the first chip and attached so as to be in contact with the first chip. The first chip includes: a first peripheral circuit disposed on a first semiconductor substrate; a first memory cell array disposed above the first peripheral circuit; and a first electrode disposed above the first memory cell array. The second chip includes: a second electrode in contact with the first electrode; a second memory cell array disposed above the second electrode; a second peripheral circuit disposed above the second memory cell array; a second semiconductor substrate disposed above the second peripheral circuit; and a pad disposed above the second peripheral circuit and capable of receiving a command and an address from a memory controller. The first peripheral circuit controls either one or both of the first memory cell array or the second memory cell array based on a command and an address input from the pad, and the second peripheral circuit controls the other one or both of the first memory cell array or the second memory cell array based on a command and an address input from the pad.

The invention discloses a multipath signal acquisition system and method based on adaptive channel switching. The multipath signal acquisition system comprises a multiplexer, a microcontroller, a power supply and an upper computer, an input port of the multiplexer is connected with each path of sampling signals, and a common output port of the multiplexer is connected to an AD input I / O port of the microcontroller; an address control I / O port of the microcontroller is connected to an address line of the multiplexer, and an enable control I / O port of the microcontroller is connected to an enable end of the multiplexer; a serial port of the microcontroller is connected to an upper computer; a GPIO (General Purpose Input / Output) of the microcontroller controls an address line and an enabling end of the multiplexer; n input channels of the multiplexer are connected with n paths of signals, and the output of the multiplexer is connected to an ADC input pin of the microcontroller; by adaptively adjusting the waiting time after each channel of the multiplexer is switched, the signal is ensured to be stable after the channels are switched. According to the invention, the signal can be ensured to be stable after channel switching, the sampling accuracy is improved, the waiting time can be reduced, and the sampling efficiency is improved.

A slice manager module selects two network nodes out of network nodes belonging to the network slice and determines the two network nodes as the pair. The slice manager module determines an IP address relating to the network slice for each of the network nodes of the pair. An SDN controller determines, as a part or all of a communication route of the network slice, a communication route between the determined IP addresses. The SDN controller re-determines the communication route between the IP addresses in response to a fact that communication quality of the determined communication route satisfies a predetermined condition.

A magnetic disk device capable of improving data recording performance is provided. The magnetic disk device includes: a magnetic disk; a magnetic head; a power supply unit that supplies power to the magnetic head; a control unit that controls reading and writing data from the magnetic disk and, when writing data, suppresses the magnetic field range of the write head based on the offset of the write head; and an address storage unit that stores the address of the magnetic disk where data was written with the magnetic field range suppressed. The control unit reads data from the magnetic disk using the read head at a predetermined timing based on the address stored in the address storage unit, and writes the read data to the magnetic disk using the write head without suppressing the magnetic field range.

The present application provides a cache memory applied to three-dimensional graphics depth testing, including: a Cache control unit, a secondary Cache RAM storage body, a primary high-speed Cache, a data positioning unit, and a dynamic allocation unit; wherein, the Cache control unit allocates storage addresses and controls Cache Lines; the secondary Cache RAM storage body stores secondary Cache Lines; the primary high-speed Cache caches primary Cache Lines; the data positioning unit determines the position of depth data in a Cache Line; the dynamic allocation unit dynamically allocates testing tasks. By combining two levels of caches with different rates, the response speed of the Cache is increased, the read / write latency is reduced, and the throughput is increased. It is ensured that when the Cache is hit, only one depth data read request is sent, and multiple associated depth data can be returned simultaneously within one clock cycle.

Disclosed is a nonvolatile memory device which includes a first plane that includes a plurality of memory blocks, a second plane that includes a plurality of memory blocks, an address replacing circuit that receives a first input address from an external controller, the first input address corresponding to a first memory block of the plurality of memory blocks of the first plane from an external controller and outputs a replaced address based on the first input address and bad block information, and an address decoder that controls word lines connected with a second memory block based on the replaced address, the word lines corresponding to the replaced address from among the plurality of memory blocks of the second plane. The first memory block of the first plane is a bad block.

A nonvolatile memory (NVM) device includes a plurality of memory blocks and a control logic receiving a specific command and an address. The control logic may perform a cell count-based dynamic read (CDR) operation on memory cells connected to one of wordlines of a selected block, among the plurality of memory blocks, in response to the address. The control logic includes a cell count comparator circuit configured to compare: (1) a first cell count value for a highest state among a plurality of states with at least one reference value according to the CDR operation and (2) a second cell count value for an erase state among the plurality of states with the at least one reference value. Additionally, the control logic includes a read level selector configured to select a read level according to a result of the comparison of the cell count comparator circuit.

The application provides a multifunctional test chip and method based on a PXI architecture, and relates to the technical field of test chips; the chip comprises a bus interface, a functional module group and an address controller; the bus interface interacts with an upper computer through a PXI bus; the functional module group comprises pulse sending, detection, analog quantity acquisition / output, serial communication, a storage controller and a temperature acquisition module, and can realize pulse signal transceiving, analog quantity processing, serial communication, data storage and temperature acquisition; the address controller divides an address space into eight subspaces, and precise control is realized. The control method comprises the steps of initializing an interface circuit, executing pulse sending and detection, analog quantity output and acquisition, EEPROM operation, UART communication and temperature acquisition and the like. The application integrates special modules, replaces traditional FPGA design, improves performance and reliability, reduces resource waste, reduces cost, shortens the development cycle, and is suitable for complex test scenes such as spaceflight measurement and control.

A system, method and storage medium for configuring and operating a plurality of serial devices in an emergency response vehicle. The system may include a plurality of peripheral devices, each configured to receive and store an address, a controller configured to transmit addressable commands to each of the devices, at least two of the devices having a first device type wherein the addresses of each of the devices are selectable by a user. The method may include selecting a plurality of peripheral devices, each configured to receive and store an address, with at least two of the devices have a same device type, connecting each of the devices to a computer executing configuration software, detecting each of the devices, receiving an address for at least one of the devices, and storing the address in a storage medium.

The invention provides a distributed account book encryption method and system based on a block chain. The method comprises the following steps: generating a key identifier hash value containing a key version and a timestamp for each node, constructing a Merkel tree based on the key identifier hash value of each node, calculating a root hash of the Merkel tree, and writing the root hash into a block chain; for each node, dynamically selecting an encryption algorithm in combination with a data sensitivity level, a node computing power and a node delay threshold value, performing security verification on the selected encryption algorithm according to root hash, and outputting a final target encryption algorithm; in response to triggering data conversion, controlling the lightweight node to transmit to-be-converted first plaintext data and an algorithm type identifier matched with a target encryption algorithm to a TEE module according to the lightweight node and a TEE interface address corresponding to the lightweight node; and controlling the TEE module to encrypt the first plaintext data into ciphertext data or decrypt the first plaintext data into second plaintext data according to the conversion requirement, and generating zero-knowledge proof at the same time.

A command address control circuit includes a command decoding circuit, an error decision circuit, and a shifting circuit. The command decoding circuit detects a type of command address signal set in synchronization with a reference clock signal. The error decision circuit detects whether an error is present in the command address signal set, and generates a block signal based on the type of command address signal set and the results of the detection of an error. The shifting circuit outputs the command address signal set as an internal command address signal set based on the reference clock signal and the block signal.

The invention provides a broadcast paging method and system based on a network service, and the method comprises the steps: obtaining an IP address of a broadcast system host, and transmitting the IP address to a background network service, so as to enable the background network service to obtain a first protocol array; if so, enabling a background network service to obtain first terminal sound box data; acquiring and analyzing a first telegraph text based on the first telegraph text and a preset telegraph text protocol, acquiring a real-time state of a first terminal sound box, and if a preset first state is satisfied, sending a reply telegraph text to a background network service to extract a plug flow address of the first terminal sound box; and controlling the background network service to obtain the real-time audio, and sending the real-time audio to the first terminal sound box stream pushing address, so that the sound box receives and plays the real-time audio, and real-time conversation from the webpage to the terminal sound box is realized. According to the broadcast paging method based on the network service provided by the invention, paging can be realized without depending on special hardware equipment or installing specific software, and the terminal sound box can be directly selected only through a webpage to complete real-time paging and calling.

This application discloses a matrix operation processor and data processing method for quantum-resistant cryptographic algorithms, belonging to the field of quantum-resistant cryptography. The matrix operation processor includes a control module and an operation module. The control module is configured to receive an operation request containing a target matrix, allocate a storage address, control a matrix generator to generate and store data to the corresponding address; in response to a trigger signal indicating that a row of data in the target matrix has been generated, it reads the data from the corresponding address and sends it to the operation module, and controls the matrix generator to generate the next row of data in the target matrix; the operation module includes multiple parallel multiply-accumulate units, configured to perform multiplication and accumulation operations on the data sent by the control module according to the operation rules corresponding to the linear transformation operation type between the target matrix and the first matrix; the number of multiply-accumulate units is determined by the bit width of a single data read. Applying this application aims to improve the efficiency of matrix operations.

According to examples, an apparatus may include a processor that may calculate a normalized threat intelligence score (TIS) for an autonomous system (AS) based on a sum of threat intelligence (TI) signals associated with Internet protocol (IP) addresses controlled by the AS and a count of the IP addresses controlled by the AS. The processor may also determine, based on the normalized TIS for the AS, a probability that activities associated with the IP addresses controlled by the AS are likely to be malicious. The processor may further output the determined probability that the activities associated with the IP addresses controlled by the AS are likely to be malicious.

The invention relates to an asynchronous first-in first-out device and a chip. The asynchronous first-in first-out device is characterized in that a write control module obtains a current write vector in a one-hot binary format by querying a null vector data structure, generates a current write address according to the current write vector, controls a memory to write data to be written into the current write address, and transmits the current write vector to a read control module in a delayed manner; the read control module updates an occupied vector data structure according to the current write vector transmitted in a delayed manner; the read control module queries the occupied vector data structure to obtain a current sequential read vector in a one-hot binary format, generates a current sequential read address according to the current sequential read vector, and controls the memory to read read data according to the current sequential read address; the read interface module sends the read data and the current sequential read address to downstream external equipment together, and the downstream external equipment can perform backward reading subsequently by using the current sequential read address; by means of the asynchronous FIFO device, the asynchronous function and the read-back function of the FIFO device can be achieved, and the area of the asynchronous FIFO device is reduced.