93 results about "Address control" patented technology

The invention discloses a configurable number-theory transformation parallel computing acceleration method and device for a post quantum cryptographic algorithm, and relates to the technical field of cryptographic algorithms. The number theory transformation is a calculation bottleneck in lattice-based post-quantum cryptography and PQC; a hardware accelerator specially designed for number theory transformation (NTT) is an effective solution for improving the execution speed. At present, a mainstream design neglects the influence of the scale of a calculation array, so that the design of an NTT calculation circuit is poor in flexibility and low in memory utilization rate, and a two-dimensional reconfigurable number theory transformation acceleration circuit is provided; the method is applied to a key generation stage, an encryption stage and a decryption stage of the post-quantum cryptographic algorithm. The NTT reconfigurable computing circuit provided by the invention can keep the utilization rate of hardware resources, and is suitable for mobile terminal equipment with limited resources; the NTT circuit adopts a low-complexity memory mapping scheme, so that the address control logic is greatly simplified, and the hardware overhead is reduced.

The invention discloses a solid state disk-based data transmission method and device, a medium and a product, and relates to the field of solid state disks. According to the method, a data layout description header is obtained from a host memory in a direct memory access mode according to a target memory initial address; analyzing the data layout description header through a flash translation layer of the solid state disk, identifying each data segment entry, and extracting length information and life cycle attribute tags of corresponding data segments from each data segment entry; based on the life cycle attribute tag, planning a corresponding physical flash memory page for each data segment as a target write address of the data segment; and based on the target write-in address, controlling the solid state disk to execute DMA operation segment by segment according to the sequence of data segment entries in the data layout description head until the write-in of the total data length is completed. By implementing the technical scheme provided by the invention, the data storage efficiency of the solid state disk is improved.

This disclosure provides a method and apparatus for planning Equivalent Multipath (ECMP) load balancing. The method includes: a control device establishing a remote login connection with a device to be configured and setting up Equivalent Multipath (ECMP) to reach the destination device; sequentially traversing each hash algorithm in a hash algorithm list; controlling the device to be configured to switch to the currently traversed hash algorithm via the remote login connection, sending it a hash factor type, a set of candidate source IP addresses, and the IP address of the destination device; controlling the device to be configured to initiate the construction of multiple data packets based on the hash factor type, each with a candidate source IP address and a destination device IP address; causing the device to be configured to calculate and record the transmission ratio of each member path of ECMP associated with each candidate source IP address; and obtaining this ratio via the remote login connection to select service IP addresses for the device to be configured and load balance the data packets sent to the destination device based on the member paths selected by the hash algorithm from ECMP.

A bidirectional address allocation method and system are used for allocating independent addresses to N units awaiting address allocation of at least one module awaiting address allocation. A first serial data port of a controller, two serial data ports of each of the N units awaiting address allocation, and a second serial data port of the controller are sequentially connected in series. In the module awaiting address allocation, a direction starting from a unit awaiting address allocation connected to the first serial data port of the controller is a forward direction, and a direction from a unit awaiting address allocation connected to the second serial data port of the controller is a reverse direction. The method includes: performing forward address allocation; determining whether address allocation for the N units awaiting address allocation is completed; changing an input / output direction; and performing reverse address allocation.

The invention provides a security protection method for IPv6 network attacks, and relates to the technical field of Internet security. The method comprises the steps that a backbone network topology structure is built, the backbone network topology structure comprises an access layer router and a core layer router, and the access layer router and the core layer router are communicated in advance; a BGP4 + routing protocol is deployed based on the backbone network topology structure, and the BGP4 + routing protocol is used for enabling routers in the whole network in the backbone network topology structure to achieve BGP4 + routing reachability; an address control routing strategy is configured based on the backbone network topology structure, and the address control routing strategy is configured to be capable of notifying a forbidden target address to the whole network through a BGP4 + routing protocol; and in response to matching of the attack traffic with the target address in the access layer router, blocking the attack traffic to complete security protection. The invention further provides a security protection device for the IPv6 network attack, electronic equipment and a medium.

The invention discloses a scheduling-driven high-level comprehensive array division method, which comprises the following steps of: creating an associated access instruction set for arrays in algorithm design, and analyzing an address calculation expression of each access instruction; on the basis of the control data flow diagram designed by the algorithm, instruction scheduling is executed according to an instruction topological sequence and circuit performance requirements, for an array access instruction, a schedulable interval of the array access instruction is calculated, control steps in the interval are traversed, and incremental address conflicts introduced by each scheduling mode are determined; aiming at each scheduling mode of the array access instruction, a minimum overhead array division scheme capable of solving all address conflicts is searched, and the overhead of the division scheme comprehensively considers the number of storage modules after division, address control logic complexity and time delay; the address conflicts comprise the incremental address conflicts and the stock address conflicts. The method has the advantages that compared with an existing array division scheme, calculation scheduling and array division are organically combined, the cost of array division is reduced, and the scheduling performance is improved.

This invention relates to the field of peripheral control technology, specifically to a multi-chip addressing control method, electronic devices, storage media, and program products. The method includes: receiving a control request and generating a command packet containing a source address, a target address, and command data; splitting the command packet and sending it to different target chips under a synchronous control request, and sending the command packet according to the target address under an asynchronous control request; forwarding the command to the master control chip when the slave chip lacks execution capability; executing the command packet when both the master and slave chips receive the same command data; receiving a response packet and determining the responding chip based on the source address, and outputting the control result. This invention enables directional control, collaborative execution, and response differentiation in multi-chip peripherals.

Embodiments of the present application disclose a data access method, a data access system and a storage medium. After receiving a migration interrupt request sent by a target processing unit, a central processing unit of a processing unit cluster according to a virtual address of target data in the migration interrupt request controls the target processing unit to acquire an address mapping relationship of the target data, and controls a source processing unit to migrate the target data to the target processing unit, and then controls the target processing unit to update the address mapping relationship of the target data after the target data is migrated, so that the target processing unit reads the target data from the memory according to the updated address mapping relationship. In the embodiments of the present application, the target processing unit can access data in the source processing unit according to the received address mapping relationship without waiting for the data migration to be completed, so that the data access delay can be effectively reduced, and the data processing efficiency is improved.

In some implementations, a controller may detect a failure associated with data obtained, using a first physical address, from a current physical location of a non-volatile memory device. The controller may determine, based on detecting the failure, a virtual block number based on the first physical address. The controller may determine that the virtual block number identifies a garbage collection block. The controller may determine a virtual wordline of the garbage collection block. The controller may obtain, from the virtual wordline, a data log that identifies a second physical address for a previous physical location of the data. The controller may obtain, using the second physical address, the data from the previous physical location.

The application relates to a logic truth table acquisition method and device, electronic equipment and a storage medium, and belongs to the technical field of integrated circuits. The logic truth table acquisition method comprises the following steps: finding a register array from a netlist, wherein the register array comprises a plurality of registers; finding an enabling signal for controlling each register from the netlist; changing the value of an address control signal, and obtaining a logic truth table based on each enabling signal under different address control signals, wherein the logic truth table comprises the corresponding relationship between each enabling signal and the address control signal, and is used for determining the register corresponding to each enabling signal. The method can automatically find the enabling signal related to the register array from the netlist, change the value of the address control signal, obtain the logic truth table based on each enabling signal under different address control signals, and improve the problems of low efficiency and easy errors in manually acquiring the logic truth table of the register array.

This disclosure provides a controller, address management method, and system for a phase-change memory (PCM). The method includes: determining the address mapping mode of the PCM; if it is a static mapping mode, mapping a first source address to a first destination address based on a preset mapping table; if it is a dynamic mapping mode, matching a corresponding address mapping rule according to a dynamic scenario, and mapping a second source address to a second destination address based on the address mapping rule; if it is a hybrid mapping mode, mapping a third source address to a third destination address based on a preset mapping table, controlling the PCM to perform read operations based on the third destination address; and matching a corresponding address mapping rule according to a dynamic scenario, mapping a fourth source address to a fourth destination address based on the address mapping rule, and controlling the PCM to perform write operations based on the fourth destination address. This application can reduce the read latency of the PCM, improve the write performance and media lifetime of the PCM, and achieve a balance between read and write performance.

Embodiments provide a memory device whose chip size is not limited by the size of a peripheral circuit. A memory device of an embodiment has: a first chip; and a second chip disposed on the first chip and attached so as to be in contact with the first chip. The first chip includes: a first peripheral circuit disposed on a first semiconductor substrate; a first memory cell array disposed above the first peripheral circuit; and a first electrode disposed above the first memory cell array. The second chip includes: a second electrode in contact with the first electrode; a second memory cell array disposed above the second electrode; a second peripheral circuit disposed above the second memory cell array; a second semiconductor substrate disposed above the second peripheral circuit; and a pad disposed above the second peripheral circuit and capable of receiving a command and an address from a memory controller. The first peripheral circuit controls either one or both of the first memory cell array or the second memory cell array based on a command and an address input from the pad, and the second peripheral circuit controls the other one or both of the first memory cell array or the second memory cell array based on a command and an address input from the pad.

The invention discloses a multipath signal acquisition system and method based on adaptive channel switching. The multipath signal acquisition system comprises a multiplexer, a microcontroller, a power supply and an upper computer, an input port of the multiplexer is connected with each path of sampling signals, and a common output port of the multiplexer is connected to an AD input I / O port of the microcontroller; an address control I / O port of the microcontroller is connected to an address line of the multiplexer, and an enable control I / O port of the microcontroller is connected to an enable end of the multiplexer; a serial port of the microcontroller is connected to an upper computer; a GPIO (General Purpose Input / Output) of the microcontroller controls an address line and an enabling end of the multiplexer; n input channels of the multiplexer are connected with n paths of signals, and the output of the multiplexer is connected to an ADC input pin of the microcontroller; by adaptively adjusting the waiting time after each channel of the multiplexer is switched, the signal is ensured to be stable after the channels are switched. According to the invention, the signal can be ensured to be stable after channel switching, the sampling accuracy is improved, the waiting time can be reduced, and the sampling efficiency is improved.

A slice manager module selects two network nodes out of network nodes belonging to the network slice and determines the two network nodes as the pair. The slice manager module determines an IP address relating to the network slice for each of the network nodes of the pair. An SDN controller determines, as a part or all of a communication route of the network slice, a communication route between the determined IP addresses. The SDN controller re-determines the communication route between the IP addresses in response to a fact that communication quality of the determined communication route satisfies a predetermined condition.

A nonvolatile memory (NVM) device includes a plurality of memory blocks and a control logic receiving a specific command and an address. The control logic may perform a cell count-based dynamic read (CDR) operation on memory cells connected to one of wordlines of a selected block, among the plurality of memory blocks, in response to the address. The control logic includes a cell count comparator circuit configured to compare: (1) a first cell count value for a highest state among a plurality of states with at least one reference value according to the CDR operation and (2) a second cell count value for an erase state among the plurality of states with the at least one reference value. Additionally, the control logic includes a read level selector configured to select a read level according to a result of the comparison of the cell count comparator circuit.

The application provides a multifunctional test chip and method based on a PXI architecture, and relates to the technical field of test chips; the chip comprises a bus interface, a functional module group and an address controller; the bus interface interacts with an upper computer through a PXI bus; the functional module group comprises pulse sending, detection, analog quantity acquisition / output, serial communication, a storage controller and a temperature acquisition module, and can realize pulse signal transceiving, analog quantity processing, serial communication, data storage and temperature acquisition; the address controller divides an address space into eight subspaces, and precise control is realized. The control method comprises the steps of initializing an interface circuit, executing pulse sending and detection, analog quantity output and acquisition, EEPROM operation, UART communication and temperature acquisition and the like. The application integrates special modules, replaces traditional FPGA design, improves performance and reliability, reduces resource waste, reduces cost, shortens the development cycle, and is suitable for complex test scenes such as spaceflight measurement and control.

A system, method and storage medium for configuring and operating a plurality of serial devices in an emergency response vehicle. The system may include a plurality of peripheral devices, each configured to receive and store an address, a controller configured to transmit addressable commands to each of the devices, at least two of the devices having a first device type wherein the addresses of each of the devices are selectable by a user. The method may include selecting a plurality of peripheral devices, each configured to receive and store an address, with at least two of the devices have a same device type, connecting each of the devices to a computer executing configuration software, detecting each of the devices, receiving an address for at least one of the devices, and storing the address in a storage medium.

The invention provides a distributed account book encryption method and system based on a block chain. The method comprises the following steps: generating a key identifier hash value containing a key version and a timestamp for each node, constructing a Merkel tree based on the key identifier hash value of each node, calculating a root hash of the Merkel tree, and writing the root hash into a block chain; for each node, dynamically selecting an encryption algorithm in combination with a data sensitivity level, a node computing power and a node delay threshold value, performing security verification on the selected encryption algorithm according to root hash, and outputting a final target encryption algorithm; in response to triggering data conversion, controlling the lightweight node to transmit to-be-converted first plaintext data and an algorithm type identifier matched with a target encryption algorithm to a TEE module according to the lightweight node and a TEE interface address corresponding to the lightweight node; and controlling the TEE module to encrypt the first plaintext data into ciphertext data or decrypt the first plaintext data into second plaintext data according to the conversion requirement, and generating zero-knowledge proof at the same time.

The invention provides a broadcast paging method and system based on a network service, and the method comprises the steps: obtaining an IP address of a broadcast system host, and transmitting the IP address to a background network service, so as to enable the background network service to obtain a first protocol array; if so, enabling a background network service to obtain first terminal sound box data; acquiring and analyzing a first telegraph text based on the first telegraph text and a preset telegraph text protocol, acquiring a real-time state of a first terminal sound box, and if a preset first state is satisfied, sending a reply telegraph text to a background network service to extract a plug flow address of the first terminal sound box; and controlling the background network service to obtain the real-time audio, and sending the real-time audio to the first terminal sound box stream pushing address, so that the sound box receives and plays the real-time audio, and real-time conversation from the webpage to the terminal sound box is realized. According to the broadcast paging method based on the network service provided by the invention, paging can be realized without depending on special hardware equipment or installing specific software, and the terminal sound box can be directly selected only through a webpage to complete real-time paging and calling.

This application discloses a matrix operation processor and data processing method for quantum-resistant cryptographic algorithms, belonging to the field of quantum-resistant cryptography. The matrix operation processor includes a control module and an operation module. The control module is configured to receive an operation request containing a target matrix, allocate a storage address, control a matrix generator to generate and store data to the corresponding address; in response to a trigger signal indicating that a row of data in the target matrix has been generated, it reads the data from the corresponding address and sends it to the operation module, and controls the matrix generator to generate the next row of data in the target matrix; the operation module includes multiple parallel multiply-accumulate units, configured to perform multiplication and accumulation operations on the data sent by the control module according to the operation rules corresponding to the linear transformation operation type between the target matrix and the first matrix; the number of multiply-accumulate units is determined by the bit width of a single data read. Applying this application aims to improve the efficiency of matrix operations.

The invention relates to an asynchronous first-in first-out device and a chip. The asynchronous first-in first-out device is characterized in that a write control module obtains a current write vector in a one-hot binary format by querying a null vector data structure, generates a current write address according to the current write vector, controls a memory to write data to be written into the current write address, and transmits the current write vector to a read control module in a delayed manner; the read control module updates an occupied vector data structure according to the current write vector transmitted in a delayed manner; the read control module queries the occupied vector data structure to obtain a current sequential read vector in a one-hot binary format, generates a current sequential read address according to the current sequential read vector, and controls the memory to read read data according to the current sequential read address; the read interface module sends the read data and the current sequential read address to downstream external equipment together, and the downstream external equipment can perform backward reading subsequently by using the current sequential read address; by means of the asynchronous FIFO device, the asynchronous function and the read-back function of the FIFO device can be achieved, and the area of the asynchronous FIFO device is reduced.

The present application relates to the field of wind turbine address control technology, and discloses a wind turbine address writing method and a wind turbine address writing system, wherein the wind turbine address writing method comprises: the first wind turbine among n wind turbines receives the initial address information and the first write instruction sent by the host computer; the i-th wind turbine among the n wind turbines performs the following steps, wherein i is sequentially taken from 1 to n: in response to the i-th write instruction sent by the i-1-th wind turbine, the i-th address information is set to the local address number of the i-th wind turbine, wherein the i-th address information is generated for the i-1-th wind turbine or the i-th wind turbine according to the i-1-th address information, the 0th wind turbine is taken as the host computer, and the 0th address information is taken as the initial address information; if i does not get n, then the i+1th write instruction is generated, and the i+1th write instruction is sent to the i+1th wind turbine; if i gets n, the address writing of the wind turbine group is completed. In the above manner, the present application improves the convenience and accuracy of addressing multiple FFUs.

This application discloses a static random access memory (SRAM) repair circuit including a row redundancy array module, a built-in self-test (BIST) module, a repair address mapping module, and a repair address control module. The BIST module is configured to detect failed cells and output failing addresses. The repair address mapping module is configured to register each of the failing addresses and provide a first enable signal. The repair address mapping module controls turning on and turning off of the repair function through the first enable signal and obtains address mapping through the failing address. The repair address control module is configured to control strobing and turning off of each of the redundancy memory rows of the row redundancy array module through a second enable signal and a repair row selection signal when the repair function is turned on.

Techniques are disclosed relating to access control for threads executed by a computer processor. Processor circuitry may include an execution pipeline, a base register and a limit register. The base register and the limit register may define a range of virtual addresses for a thread executed by the execution pipeline. Control circuitry may access a translation table that stores translation entries that map a virtual address space to a physical address space, wherein a given entry includes a thread-private state indication. for a virtual address provided by the thread at a first permission level, the control circuitry may: determine that the thread-private state indication of a corresponding entry of the translation table is set and in response to the determination, provide a translation of the virtual address only if the virtual address falls within the range of virtual addresses.

The invention relates to a first-in first-out device, a control method thereof and a chip. The first-in first-out device comprises a read interface module, a control module and a memory, the control module obtains a current sequential read address according to values of a plurality of bits in the occupation vector data structure, controls the memory to read read data from a corresponding storage address according to the current sequential read address, and updates the occupation vector data structure after reading the read data; the occupancy vector data structure comprises a plurality of bits in one-to-one correspondence with a plurality of storage addresses of the memory, and each bit indicates whether the corresponding storage address can be sequentially read or not; the read interface module sends the read data and the current sequential read address to downstream equipment; and the read interface module also receives a read-back enable signal and a read-back address input by the downstream equipment, reads corresponding read-back data from the memory according to the read-back enable signal and the read-back address, and sends the read-back data to the downstream equipment. According to the method and the device, the backward reading of the historical data of the first-in first-out device can be realized, and the hardware cost and the area of the first-in first-out device are reduced.

The invention discloses a controllable multi-channel optomagnetic addressing guide system and a method thereof, and belongs to the technical field of precise control and advanced manufacturing. The system comprises a matrix, and a magnetic function unit, a light control unit, a magnetic field control unit and a main control unit which are distributed in the matrix. The main control unit scans one or more light tracks in a substrate by controlling the light control unit, cooperates with a magnetic field generated by the magnetic field control unit, and realizes parallel guidance and addressing control of the multiple groups of magnetic functional units by utilizing the combined action of a photothermal effect and the magnetic field. By changing parameters such as laser wavelength, the system can selectively activate and sort specific functional units. The method overcomes the defect that multiple targets cannot be independently, parallelly and accurately guided in the prior art, has strong addressing capability, high parallelism and flexible controllability, and can be widely applied to the fields of targeted drug delivery, microcosmic assembly, tissue engineering, reconfigurable flexible electronics and the like.

Systems and methods for dynamically providing a postal address. The method includes receiving non-standard postal address information for the user, determining whether the non-standard postal address information corresponds to an electronic identification of the user that is provided as the postal address of parcel or letter to be delivered to the user, in response to a determination that the non-standard postal address information corresponds to the electronic identification of the user, associating the non-standard postal address information with the electronic identification of the user, generating the postal address based on the non-standard postal address information and controlling at least one operation for shipping and delivery, communication and identification of the user based on the postal address.

The embodiment of the invention discloses a network controller, electronic equipment, a computer network system and a remote access method, relates to the technical field of integrated computers, and can effectively simplify the access operation of a processor on a remote memory. The network controller comprises a semantic conversion module which is configured to convert a memory access request into a network access request under network semantics under the condition that a processor initiates the memory access request to a first memory address; wherein the first memory address is an address within a first address range in physical memory addresses of first equipment; and the control module is electrically connected with the semantic conversion module and is configured to send the network access request to the second equipment, so that the memory access request acts on a memory buffer area corresponding to a second memory address of the second equipment through the network access request, and the memory buffer area corresponds to the second memory address of the second equipment. The second memory address is located in the second address range. The method is suitable for remote memory access.

Systems and methods for dynamically providing a postal address. The method includes receiving non-standard postal address information for the user, determining whether the non-standard postal address information corresponds to an electronic identification of the user that is provided as the postal address of parcel or letter to be delivered to the user, in response to a determination that the non-standard postal address information corresponds to the electronic identification of the user, associating the non-standard postal address information with the electronic identification of the user, generating the postal address based on the non-standard postal address information and controlling at least one operation for shipping and delivery, communication and identification of the user based on the postal address.

A lighting device can be assigned to a light group by a controller. The controller can read a plurality of addresses associated with a plurality of lighting devices. The controller can send a set of addresses of the plurality of addresses to a computing device. Responsive to receiving a first instruction from the computing device that identifies a first address of the set of addresses, the controller can cause a first lighting device of the plurality of lighting devices to emit a first light. Responsive to receiving a second instruction from the computing device, the controller can assign the first lighting device to a first light group.