178 results about "Address control" patented technology

A nonvolatile memory device includes a plurality of latch groups, an address controller, an encoder, and a buffer. The address controller controls an input address and an output address to indicate one of the plurality of latch groups. The encoder receives sector data from a latch group corresponding to the output address among the plurality of latch groups and also compresses the received sector data. The buffer stores the compressed sector data. Among the plurality of latch groups, the compressed sector data stored in the buffer is overwritten in a latch group corresponding to the input address.

The invention discloses a configurable number-theory transformation parallel computing acceleration method and device for a post quantum cryptographic algorithm, and relates to the technical field of cryptographic algorithms. The number theory transformation is a calculation bottleneck in lattice-based post-quantum cryptography and PQC; a hardware accelerator specially designed for number theory transformation (NTT) is an effective solution for improving the execution speed. At present, a mainstream design neglects the influence of the scale of a calculation array, so that the design of an NTT calculation circuit is poor in flexibility and low in memory utilization rate, and a two-dimensional reconfigurable number theory transformation acceleration circuit is provided; the method is applied to a key generation stage, an encryption stage and a decryption stage of the post-quantum cryptographic algorithm. The NTT reconfigurable computing circuit provided by the invention can keep the utilization rate of hardware resources, and is suitable for mobile terminal equipment with limited resources; the NTT circuit adopts a low-complexity memory mapping scheme, so that the address control logic is greatly simplified, and the hardware overhead is reduced.

Provided in the present application are a memory pre-loading processing method, and a device and a storage medium. The method comprises: a virtual machine manager collecting a plurality of pieces of historical page fault information that are generated by a target application program in a client; on the basis of a plurality of client virtual addresses that are included in the plurality of pieces of historical page fault information, determining a target client virtual address to be accessed when a page fault occurs in the target application program next time; on the basis of the target client virtual address and a storage address of a target client system page table corresponding to the target application program, determining a target host machine virtual address corresponding to the target client virtual address; and controlling a host machine operating system to allocate a target host machine physical address corresponding to the target host machine virtual address, and loading data, which corresponds to the target host machine virtual address, into the target host machine physical address. By means of loading, into a memory in advance, data corresponding to a target client virtual address in which a page fault may occur in the future, an access delay duration caused by the page fault is shortened.

The invention provides a memory preloading processing method and device and a storage medium, and the method comprises the steps that a virtual machine manager collects a plurality of pieces of historical missing page exception information generated by a target application program in a client, and stores the historical missing page exception information according to a plurality of client virtual addresses contained in the historical missing page exception information; determining a target client virtual address to be accessed when the target application program is subjected to page missing exception next time; determining a target host machine virtual address corresponding to the target client virtual address according to the target client virtual address and a storage address of a target client system page table corresponding to the target application program; and controlling the host machine operating system to distribute a target host machine physical address corresponding to the target host machine virtual address, and loading data corresponding to the target host machine virtual address into the target host machine physical address. And the data corresponding to the target client virtual address which may cause the page missing abnormity in the future is loaded into the memory in advance, so that the access delay duration caused by the page missing abnormity is reduced.

Methods and systems for performing current sense compensation for one or more power stages in a multiphase voltage regulator are described. A controller can be connected to a plurality of power stages through a communication interface. The controller can generate a data packet including a command to obtain temperature information and an address that identifies a specific power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages using the communication interface. The controller can receive temperature information of the specific power stage from the specific power stage through the communication interface. The controller can compensate a sensed current of the specific power stage based on the received temperature information of the specific power stage.

The embodiment of the invention provides a digital driving waveform generation device and method of a galvanometer and projection equipment, and relates to the technical field of laser projection. The device comprises a subframe delay module, a clock control module, an address control module and an amplitude storage module, the sub-frame delay module is used for delaying the sub-frame signal and transmitting the delayed sub-frame signal to the address control module; the clock control module is used for providing a control clock for generating a digital driving waveform for the address control module; the amplitude storage module is used for storing a plurality of amplitudes of the digital driving waveform according to a preset storage sequence; and the address control module is used for reading the amplitudes of a preset segment number from the amplitude storage module according to a preset galvanometer type when the rising edge or the falling edge of the delay subframe signal arrives, and outputting the amplitudes in sequence according to a reading sequence to generate a digital driving waveform. The embodiment of the invention is used for generating the digital driving waveform, so that the galvanometer moves to an accurate position required by image display.

The invention relates to the technical field of computer hardware testing, and discloses a testing method and device of storage equipment, electronic equipment and a storage medium, and the testing method comprises the steps that a write address control strategy is generated, and the write address control strategy is used for representing the write sequence of different addresses in the storage equipment; obtaining test data; and sequentially writing the test data into corresponding positions of the storage equipment according to a sequence defined by the write-in address control strategy. The technical problem of low reliability of the writing effect of the test storage device is solved, and the technical effect of improving the test accuracy of the storage device is achieved.

The embodiment of the invention provides an automatic addressing method, device and system for a hydraulic support, electronic equipment and a readable storage medium. The automatic addressing method for the hydraulic support comprises the steps that at least one electro-hydraulic controller is determined as a first controller; determining an address parameter of the first controller as a first addressing address; controlling the Bluetooth module corresponding to the first addressing address to send a detection signal, and receiving a feedback signal returned by the Bluetooth module corresponding to the at least one electro-hydraulic controller; determining a second addressing address according to the detection signal, the feedback signal and the first addressing address; determining an addressing instruction frame corresponding to the second addressing address; and transmitting the addressing instruction frame to the electro-hydraulic controller corresponding to the second addressing address through the controller local area network bus, determining a standard response frame, and determining a second controller corresponding to the standard response frame. According to the scheme, electro-hydraulic control automatic addressing is achieved, and the coal mine fully-mechanized coal mining automation control level and production efficiency are improved.

The invention relates to a thermal power generating unit space-time coupling control method based on a double-gating LSTM network, and the method comprises the steps: collecting the real-time data of a thermal power generating unit, including a target control variable and a plurality of coupling variables; real-time data of the thermal power generating unit are input into the double-gating LSTM network, and temperature curves and control parameters of a plurality of steps in the future are obtained through prediction; the double-gating LSTM network splits a forgetting gate of an LSTM into a short-term forgetting gate and a long-term forgetting gate, a short-term gating channel is started when the double-gating LSTM network is in a conventional working condition, and a long-term gating channel is started when the time delay exceeds a set time delay threshold value; generating a thermodynamic sensitivity weight matrix based on the thermodynamic sensitivity weight model, and driving the LSTM network to perform back propagation rolling optimization of parameters; and based on the output of the double-gate-control LSTM network, a secondary air door opening instruction of the fuel valve is generated through a model prediction controller. Compared with the prior art, the problem of control instability under complex working conditions such as deep peak regulation and coal type switching can be effectively solved.

The invention relates to the technical field of wireless information transmission, and provides a reconfigurable high-precision multipath time delay simulation method and device. Group time delay and relative time delay are graded for three times, fine time delay with the time delay amount within a decimal range is realized by using a reduced farrow filter structure, the precision can reach 0.1 ns, coarse time delay with the time delay amount being integral multiple of a system clock is realized by using ram resources, and large-range time delay of signals is realized by using ping-pong operation through a dislocation address control technology. And finally, large-range and high-precision multipath time delay simulation is realized.

Physical and logical components of a long line loiter control system address control of a long line loiter maneuver conducted beneath a carrier, such as a fixed-wing aircraft. Control may comprise identifying, predicting, and reacting to estimated states and predicted states of the carrier, a suspended load control system, and a long line. Identifying, predicting, and reacting to estimated states and predicted states may comprise determining characteristics of state conditions over time as well as response time between state conditions. Reacting may comprise controlling a hoist of the carrier, controlling thrusters of the suspended load control system, and or controlling or issuing flight control instructions to the carrier so as not to increase the response time and or to avoid a hazard.

The invention discloses a solid state disk-based data transmission method and device, a medium and a product, and relates to the field of solid state disks. According to the method, a data layout description header is obtained from a host memory in a direct memory access mode according to a target memory initial address; analyzing the data layout description header through a flash translation layer of the solid state disk, identifying each data segment entry, and extracting length information and life cycle attribute tags of corresponding data segments from each data segment entry; based on the life cycle attribute tag, planning a corresponding physical flash memory page for each data segment as a target write address of the data segment; and based on the target write-in address, controlling the solid state disk to execute DMA operation segment by segment according to the sequence of data segment entries in the data layout description head until the write-in of the total data length is completed. By implementing the technical scheme provided by the invention, the data storage efficiency of the solid state disk is improved.

The invention provides a multi-machine parallel connection constant pressure water supply control method and system based on communication control. The method comprises the steps that whether the system has no fault and does not meet the shutdown condition or not is judged; if not, adopting an abnormal state processing mechanism; if yes, the host adopts PID control based on feedback pressure; judging whether the pipe network pressure is smaller than target pressure; if yes, the host runs to the maximum frequency, and the pump adding condition is judged; if not, the host runs to the pump reduction detection frequency, and the pump reduction condition is judged; when the pump adding condition or the pump reducing condition is met, the host determines the station address of the started or stopped slave pump according to an automatic rotation control algorithm; starting or stopping of the corresponding slave pump is controlled according to the station address of the slave pump; the running time of each slave machine is ensured to be uniform through an automatic rotation control algorithm, and the situation that part of slave pumps do not run for a long time is avoided; a processing mechanism for various abnormal conditions is realized according to the pipe network pressure, and the frequency converter and the motor are prevented from operating at low speed for a long time to influence the safety of equipment.

This disclosure provides a method and apparatus for planning Equivalent Multipath (ECMP) load balancing. The method includes: a control device establishing a remote login connection with a device to be configured and setting up Equivalent Multipath (ECMP) to reach the destination device; sequentially traversing each hash algorithm in a hash algorithm list; controlling the device to be configured to switch to the currently traversed hash algorithm via the remote login connection, sending it a hash factor type, a set of candidate source IP addresses, and the IP address of the destination device; controlling the device to be configured to initiate the construction of multiple data packets based on the hash factor type, each with a candidate source IP address and a destination device IP address; causing the device to be configured to calculate and record the transmission ratio of each member path of ECMP associated with each candidate source IP address; and obtaining this ratio via the remote login connection to select service IP addresses for the device to be configured and load balance the data packets sent to the destination device based on the member paths selected by the hash algorithm from ECMP.

A bidirectional address allocation method and system are used for allocating independent addresses to N units awaiting address allocation of at least one module awaiting address allocation. A first serial data port of a controller, two serial data ports of each of the N units awaiting address allocation, and a second serial data port of the controller are sequentially connected in series. In the module awaiting address allocation, a direction starting from a unit awaiting address allocation connected to the first serial data port of the controller is a forward direction, and a direction from a unit awaiting address allocation connected to the second serial data port of the controller is a reverse direction. The method includes: performing forward address allocation; determining whether address allocation for the N units awaiting address allocation is completed; changing an input / output direction; and performing reverse address allocation.

Embodiments of the present disclosure provide a control circuit, a control method, and a memory. The control circuit includes: a flag signal generation module, configured to generate a command / address inversion flag signal based on a command / address control signal and an initial inversion flag signal; an input processing module, configured to generate a first intermediate command / address signal based on the command / address control signal and an initial command / address signal; and a logic decoding module, configured to: receive the first intermediate command / address signal and the command / address inversion flag signal, and generate a power down mode entry signal or a power down mode exit signal based on the command / address inversion flag signal and the first intermediate command / address signal.

The invention discloses a method for upgrading vehicle-mounted software in a rail transit vehicle and a related device, and relates to the technical field of rail transit. The method comprises the following steps: presetting a corresponding relationship among a compartment number, a vehicle-mounted equipment number and a vehicle-mounted equipment communication address; a corresponding relation among a compartment number, a vehicle-mounted equipment number and a storage address is preset. If the multiple pieces of vehicle-mounted equipment need to be uniformly updated, target vehicle-mounted equipment numbers corresponding to the multiple to-be-updated target compartment numbers respectively can be obtained; searching a target vehicle-mounted equipment communication address corresponding to the target compartment number and the target vehicle-mounted equipment number from the corresponding relation; searching a target storage address corresponding to the target compartment number and the target vehicle-mounted equipment number from the corresponding relationship; and controlling to display a vehicle-mounted software list corresponding to the target storage address. The user can determine a target version number from the vehicle-mounted software list; therefore, the purpose of uniformly sending the vehicle-mounted software corresponding to the target version number in the target storage address to the communication address of the target vehicle-mounted equipment is achieved.

The invention provides a security protection method for IPv6 network attacks, and relates to the technical field of Internet security. The method comprises the steps that a backbone network topology structure is built, the backbone network topology structure comprises an access layer router and a core layer router, and the access layer router and the core layer router are communicated in advance; a BGP4 + routing protocol is deployed based on the backbone network topology structure, and the BGP4 + routing protocol is used for enabling routers in the whole network in the backbone network topology structure to achieve BGP4 + routing reachability; an address control routing strategy is configured based on the backbone network topology structure, and the address control routing strategy is configured to be capable of notifying a forbidden target address to the whole network through a BGP4 + routing protocol; and in response to matching of the attack traffic with the target address in the access layer router, blocking the attack traffic to complete security protection. The invention further provides a security protection device for the IPv6 network attack, electronic equipment and a medium.

The invention relates to a multi-device fusion control reversed loader forward movement control method. The method comprises the steps that a controller is installed on each device; manually configuring an equipment type and an equipment address; a parameter management module in the controller automatically stores equipment type and address information; the method comprises the following steps of: configuring an action process of each device into a JSON format file according to an actual forward process of a coal mine site; uploading the JSON file to each equipment controller and an end gateway, and receiving and storing the JSON file by a storage module; the starting mode comprises a single-frame starting mode and a machine-following linkage mode; after the end gateway receives the starting signal, the forward function parameters are obtained from the database, and it is determined that corresponding equipment in the current stage needs to participate in the forward technological process; the gateway sends an action instruction to corresponding equipment through a GRPC protocol, and after each equipment controller receives the action instruction, corresponding automatic actions are added into an action executor, and the corresponding actions are executed according to a flow sequence configured by the automatic actions; and the end gateway establishes heartbeat connection with each equipment controller.

The invention discloses a scheduling-driven high-level comprehensive array division method, which comprises the following steps of: creating an associated access instruction set for arrays in algorithm design, and analyzing an address calculation expression of each access instruction; on the basis of the control data flow diagram designed by the algorithm, instruction scheduling is executed according to an instruction topological sequence and circuit performance requirements, for an array access instruction, a schedulable interval of the array access instruction is calculated, control steps in the interval are traversed, and incremental address conflicts introduced by each scheduling mode are determined; aiming at each scheduling mode of the array access instruction, a minimum overhead array division scheme capable of solving all address conflicts is searched, and the overhead of the division scheme comprehensively considers the number of storage modules after division, address control logic complexity and time delay; the address conflicts comprise the incremental address conflicts and the stock address conflicts. The method has the advantages that compared with an existing array division scheme, calculation scheduling and array division are organically combined, the cost of array division is reduced, and the scheduling performance is improved.

This invention relates to the field of peripheral control technology, specifically to a multi-chip addressing control method, electronic devices, storage media, and program products. The method includes: receiving a control request and generating a command packet containing a source address, a target address, and command data; splitting the command packet and sending it to different target chips under a synchronous control request, and sending the command packet according to the target address under an asynchronous control request; forwarding the command to the master control chip when the slave chip lacks execution capability; executing the command packet when both the master and slave chips receive the same command data; receiving a response packet and determining the responding chip based on the source address, and outputting the control result. This invention enables directional control, collaborative execution, and response differentiation in multi-chip peripherals.

The embodiment of the invention provides a method for realizing computing node virtualization based on OpenStack and a cloud platform, and the method comprises the steps: installing a nova-complex service on a first computing node, and configuring an interface address corresponding to a Libvirt connection address of the nova-complex according to the virtualization type of the first computing node; the control node dispatches a second computing node for the to-be-created virtual machine and sends a request for creating the virtual machine to a nova-complex service of the second computing node, and the second computing node is a first computing node meeting the virtualization type of the to-be-created virtual machine; and creating the virtual machine to be created through a Libvirt interface which is connected with the Libvirt connection address of the nova-component of the second computing node by the nova-component service of the second computing node. According to the technical scheme, the computing node meeting the requirement is scheduled according to the virtualization type of the virtual machine, the scheduled computing node creates the virtual machine through the interface connected with the Libvirt connection address of the nova-complex configured according to the virtualization type of the computing node, and therefore creation of the type1 virtual machine is achieved through OpenStack.

Embodiments of the present application disclose a data access method, a data access system and a storage medium. After receiving a migration interrupt request sent by a target processing unit, a central processing unit of a processing unit cluster according to a virtual address of target data in the migration interrupt request controls the target processing unit to acquire an address mapping relationship of the target data, and controls a source processing unit to migrate the target data to the target processing unit, and then controls the target processing unit to update the address mapping relationship of the target data after the target data is migrated, so that the target processing unit reads the target data from the memory according to the updated address mapping relationship. In the embodiments of the present application, the target processing unit can access data in the source processing unit according to the received address mapping relationship without waiting for the data migration to be completed, so that the data access delay can be effectively reduced, and the data processing efficiency is improved.

In some implementations, a controller may detect a failure associated with data obtained, using a first physical address, from a current physical location of a non-volatile memory device. The controller may determine, based on detecting the failure, a virtual block number based on the first physical address. The controller may determine that the virtual block number identifies a garbage collection block. The controller may determine a virtual wordline of the garbage collection block. The controller may obtain, from the virtual wordline, a data log that identifies a second physical address for a previous physical location of the data. The controller may obtain, using the second physical address, the data from the previous physical location.

The application relates to a logic truth table acquisition method and device, electronic equipment and a storage medium, and belongs to the technical field of integrated circuits. The logic truth table acquisition method comprises the following steps: finding a register array from a netlist, wherein the register array comprises a plurality of registers; finding an enabling signal for controlling each register from the netlist; changing the value of an address control signal, and obtaining a logic truth table based on each enabling signal under different address control signals, wherein the logic truth table comprises the corresponding relationship between each enabling signal and the address control signal, and is used for determining the register corresponding to each enabling signal. The method can automatically find the enabling signal related to the register array from the netlist, change the value of the address control signal, obtain the logic truth table based on each enabling signal under different address control signals, and improve the problems of low efficiency and easy errors in manually acquiring the logic truth table of the register array.

Provided are a communication route determination system and a communication route determination method which are capable of preventing deterioration of communication quality of a communication route set between a pair of network nodes belonging to a network slice from causing deterioration of communication quality of the entire network slice. A slice manager module (82) selects two network nodes out of network nodes belonging to the network slice and determines the two network nodes as the pair. The slice manager module (82) determines an IP address relating to the network slice for each of the network nodes of the pair. An SDN controller (60) determines, as a part or all of a communication route of the network slice, a communication route between the determined IP addresses. The SDN controller (60) re-determines the communication route between the IP addresses in response to a fact that communication quality of the determined communication route satisfies a predetermined condition.

This disclosure provides a controller, address management method, and system for a phase-change memory (PCM). The method includes: determining the address mapping mode of the PCM; if it is a static mapping mode, mapping a first source address to a first destination address based on a preset mapping table; if it is a dynamic mapping mode, matching a corresponding address mapping rule according to a dynamic scenario, and mapping a second source address to a second destination address based on the address mapping rule; if it is a hybrid mapping mode, mapping a third source address to a third destination address based on a preset mapping table, controlling the PCM to perform read operations based on the third destination address; and matching a corresponding address mapping rule according to a dynamic scenario, mapping a fourth source address to a fourth destination address based on the address mapping rule, and controlling the PCM to perform write operations based on the fourth destination address. This application can reduce the read latency of the PCM, improve the write performance and media lifetime of the PCM, and achieve a balance between read and write performance.

Embodiments provide a memory device whose chip size is not limited by the size of a peripheral circuit. A memory device of an embodiment has: a first chip; and a second chip disposed on the first chip and attached so as to be in contact with the first chip. The first chip includes: a first peripheral circuit disposed on a first semiconductor substrate; a first memory cell array disposed above the first peripheral circuit; and a first electrode disposed above the first memory cell array. The second chip includes: a second electrode in contact with the first electrode; a second memory cell array disposed above the second electrode; a second peripheral circuit disposed above the second memory cell array; a second semiconductor substrate disposed above the second peripheral circuit; and a pad disposed above the second peripheral circuit and capable of receiving a command and an address from a memory controller. The first peripheral circuit controls either one or both of the first memory cell array or the second memory cell array based on a command and an address input from the pad, and the second peripheral circuit controls the other one or both of the first memory cell array or the second memory cell array based on a command and an address input from the pad.

Provided are a control circuit, a control method, and a memory. The control circuit includes: a flag signal generation circuit, configured to generate a command / address inversion flag signal based on a command / address control signal and an initial inversion flag signal; an input processing circuit, configured to generate a first intermediate command / address signal based on the command / address control signal and an initial command / address signal; and a logic decoding circuit, configured to: receive the first intermediate command / address signal and the command / address inversion flag signal, and generate a power down mode entry signal or a power down mode exit signal based on the command / address inversion flag signal and the first intermediate command / address signal.

The invention discloses a multipath signal acquisition system and method based on adaptive channel switching. The multipath signal acquisition system comprises a multiplexer, a microcontroller, a power supply and an upper computer, an input port of the multiplexer is connected with each path of sampling signals, and a common output port of the multiplexer is connected to an AD input I / O port of the microcontroller; an address control I / O port of the microcontroller is connected to an address line of the multiplexer, and an enable control I / O port of the microcontroller is connected to an enable end of the multiplexer; a serial port of the microcontroller is connected to an upper computer; a GPIO (General Purpose Input / Output) of the microcontroller controls an address line and an enabling end of the multiplexer; n input channels of the multiplexer are connected with n paths of signals, and the output of the multiplexer is connected to an ADC input pin of the microcontroller; by adaptively adjusting the waiting time after each channel of the multiplexer is switched, the signal is ensured to be stable after the channels are switched. According to the invention, the signal can be ensured to be stable after channel switching, the sampling accuracy is improved, the waiting time can be reduced, and the sampling efficiency is improved.