59 results about "Address control" patented technology

The invention discloses a solid state disk-based data transmission method and device, a medium and a product, and relates to the field of solid state disks. According to the method, a data layout description header is obtained from a host memory in a direct memory access mode according to a target memory initial address; analyzing the data layout description header through a flash translation layer of the solid state disk, identifying each data segment entry, and extracting length information and life cycle attribute tags of corresponding data segments from each data segment entry; based on the life cycle attribute tag, planning a corresponding physical flash memory page for each data segment as a target write address of the data segment; and based on the target write-in address, controlling the solid state disk to execute DMA operation segment by segment according to the sequence of data segment entries in the data layout description head until the write-in of the total data length is completed. By implementing the technical scheme provided by the invention, the data storage efficiency of the solid state disk is improved.

A bidirectional address allocation method and system are used for allocating independent addresses to N units awaiting address allocation of at least one module awaiting address allocation. A first serial data port of a controller, two serial data ports of each of the N units awaiting address allocation, and a second serial data port of the controller are sequentially connected in series. In the module awaiting address allocation, a direction starting from a unit awaiting address allocation connected to the first serial data port of the controller is a forward direction, and a direction from a unit awaiting address allocation connected to the second serial data port of the controller is a reverse direction. The method includes: performing forward address allocation; determining whether address allocation for the N units awaiting address allocation is completed; changing an input / output direction; and performing reverse address allocation.

This invention relates to the field of peripheral control technology, specifically to a multi-chip addressing control method, electronic devices, storage media, and program products. The method includes: receiving a control request and generating a command packet containing a source address, a target address, and command data; splitting the command packet and sending it to different target chips under a synchronous control request, and sending the command packet according to the target address under an asynchronous control request; forwarding the command to the master control chip when the slave chip lacks execution capability; executing the command packet when both the master and slave chips receive the same command data; receiving a response packet and determining the responding chip based on the source address, and outputting the control result. This invention enables directional control, collaborative execution, and response differentiation in multi-chip peripherals.

Embodiments of the present application disclose a data access method, a data access system and a storage medium. After receiving a migration interrupt request sent by a target processing unit, a central processing unit of a processing unit cluster according to a virtual address of target data in the migration interrupt request controls the target processing unit to acquire an address mapping relationship of the target data, and controls a source processing unit to migrate the target data to the target processing unit, and then controls the target processing unit to update the address mapping relationship of the target data after the target data is migrated, so that the target processing unit reads the target data from the memory according to the updated address mapping relationship. In the embodiments of the present application, the target processing unit can access data in the source processing unit according to the received address mapping relationship without waiting for the data migration to be completed, so that the data access delay can be effectively reduced, and the data processing efficiency is improved.

In some implementations, a controller may detect a failure associated with data obtained, using a first physical address, from a current physical location of a non-volatile memory device. The controller may determine, based on detecting the failure, a virtual block number based on the first physical address. The controller may determine that the virtual block number identifies a garbage collection block. The controller may determine a virtual wordline of the garbage collection block. The controller may obtain, from the virtual wordline, a data log that identifies a second physical address for a previous physical location of the data. The controller may obtain, using the second physical address, the data from the previous physical location.

This disclosure provides a controller, address management method, and system for a phase-change memory (PCM). The method includes: determining the address mapping mode of the PCM; if it is a static mapping mode, mapping a first source address to a first destination address based on a preset mapping table; if it is a dynamic mapping mode, matching a corresponding address mapping rule according to a dynamic scenario, and mapping a second source address to a second destination address based on the address mapping rule; if it is a hybrid mapping mode, mapping a third source address to a third destination address based on a preset mapping table, controlling the PCM to perform read operations based on the third destination address; and matching a corresponding address mapping rule according to a dynamic scenario, mapping a fourth source address to a fourth destination address based on the address mapping rule, and controlling the PCM to perform write operations based on the fourth destination address. This application can reduce the read latency of the PCM, improve the write performance and media lifetime of the PCM, and achieve a balance between read and write performance.

The invention discloses a multipath signal acquisition system and method based on adaptive channel switching. The multipath signal acquisition system comprises a multiplexer, a microcontroller, a power supply and an upper computer, an input port of the multiplexer is connected with each path of sampling signals, and a common output port of the multiplexer is connected to an AD input I / O port of the microcontroller; an address control I / O port of the microcontroller is connected to an address line of the multiplexer, and an enable control I / O port of the microcontroller is connected to an enable end of the multiplexer; a serial port of the microcontroller is connected to an upper computer; a GPIO (General Purpose Input / Output) of the microcontroller controls an address line and an enabling end of the multiplexer; n input channels of the multiplexer are connected with n paths of signals, and the output of the multiplexer is connected to an ADC input pin of the microcontroller; by adaptively adjusting the waiting time after each channel of the multiplexer is switched, the signal is ensured to be stable after the channels are switched. According to the invention, the signal can be ensured to be stable after channel switching, the sampling accuracy is improved, the waiting time can be reduced, and the sampling efficiency is improved.

A nonvolatile memory (NVM) device includes a plurality of memory blocks and a control logic receiving a specific command and an address. The control logic may perform a cell count-based dynamic read (CDR) operation on memory cells connected to one of wordlines of a selected block, among the plurality of memory blocks, in response to the address. The control logic includes a cell count comparator circuit configured to compare: (1) a first cell count value for a highest state among a plurality of states with at least one reference value according to the CDR operation and (2) a second cell count value for an erase state among the plurality of states with the at least one reference value. Additionally, the control logic includes a read level selector configured to select a read level according to a result of the comparison of the cell count comparator circuit.

The application provides a multifunctional test chip and method based on a PXI architecture, and relates to the technical field of test chips; the chip comprises a bus interface, a functional module group and an address controller; the bus interface interacts with an upper computer through a PXI bus; the functional module group comprises pulse sending, detection, analog quantity acquisition / output, serial communication, a storage controller and a temperature acquisition module, and can realize pulse signal transceiving, analog quantity processing, serial communication, data storage and temperature acquisition; the address controller divides an address space into eight subspaces, and precise control is realized. The control method comprises the steps of initializing an interface circuit, executing pulse sending and detection, analog quantity output and acquisition, EEPROM operation, UART communication and temperature acquisition and the like. The application integrates special modules, replaces traditional FPGA design, improves performance and reliability, reduces resource waste, reduces cost, shortens the development cycle, and is suitable for complex test scenes such as spaceflight measurement and control.

The invention provides a broadcast paging method and system based on a network service, and the method comprises the steps: obtaining an IP address of a broadcast system host, and transmitting the IP address to a background network service, so as to enable the background network service to obtain a first protocol array; if so, enabling a background network service to obtain first terminal sound box data; acquiring and analyzing a first telegraph text based on the first telegraph text and a preset telegraph text protocol, acquiring a real-time state of a first terminal sound box, and if a preset first state is satisfied, sending a reply telegraph text to a background network service to extract a plug flow address of the first terminal sound box; and controlling the background network service to obtain the real-time audio, and sending the real-time audio to the first terminal sound box stream pushing address, so that the sound box receives and plays the real-time audio, and real-time conversation from the webpage to the terminal sound box is realized. According to the broadcast paging method based on the network service provided by the invention, paging can be realized without depending on special hardware equipment or installing specific software, and the terminal sound box can be directly selected only through a webpage to complete real-time paging and calling.

This application discloses a matrix operation processor and data processing method for quantum-resistant cryptographic algorithms, belonging to the field of quantum-resistant cryptography. The matrix operation processor includes a control module and an operation module. The control module is configured to receive an operation request containing a target matrix, allocate a storage address, control a matrix generator to generate and store data to the corresponding address; in response to a trigger signal indicating that a row of data in the target matrix has been generated, it reads the data from the corresponding address and sends it to the operation module, and controls the matrix generator to generate the next row of data in the target matrix; the operation module includes multiple parallel multiply-accumulate units, configured to perform multiplication and accumulation operations on the data sent by the control module according to the operation rules corresponding to the linear transformation operation type between the target matrix and the first matrix; the number of multiply-accumulate units is determined by the bit width of a single data read. Applying this application aims to improve the efficiency of matrix operations.

Techniques are disclosed relating to access control for threads executed by a computer processor. Processor circuitry may include an execution pipeline, a base register and a limit register. The base register and the limit register may define a range of virtual addresses for a thread executed by the execution pipeline. Control circuitry may access a translation table that stores translation entries that map a virtual address space to a physical address space, wherein a given entry includes a thread-private state indication. for a virtual address provided by the thread at a first permission level, the control circuitry may: determine that the thread-private state indication of a corresponding entry of the translation table is set and in response to the determination, provide a translation of the virtual address only if the virtual address falls within the range of virtual addresses.

The invention relates to a first-in first-out device, a control method thereof and a chip. The first-in first-out device comprises a read interface module, a control module and a memory, the control module obtains a current sequential read address according to values of a plurality of bits in the occupation vector data structure, controls the memory to read read data from a corresponding storage address according to the current sequential read address, and updates the occupation vector data structure after reading the read data; the occupancy vector data structure comprises a plurality of bits in one-to-one correspondence with a plurality of storage addresses of the memory, and each bit indicates whether the corresponding storage address can be sequentially read or not; the read interface module sends the read data and the current sequential read address to downstream equipment; and the read interface module also receives a read-back enable signal and a read-back address input by the downstream equipment, reads corresponding read-back data from the memory according to the read-back enable signal and the read-back address, and sends the read-back data to the downstream equipment. According to the method and the device, the backward reading of the historical data of the first-in first-out device can be realized, and the hardware cost and the area of the first-in first-out device are reduced.

Systems and methods for dynamically providing a postal address. The method includes receiving non-standard postal address information for the user, determining whether the non-standard postal address information corresponds to an electronic identification of the user that is provided as the postal address of parcel or letter to be delivered to the user, in response to a determination that the non-standard postal address information corresponds to the electronic identification of the user, associating the non-standard postal address information with the electronic identification of the user, generating the postal address based on the non-standard postal address information and controlling at least one operation for shipping and delivery, communication and identification of the user based on the postal address.

Systems and methods for dynamically providing a postal address. The method includes receiving non-standard postal address information for the user, determining whether the non-standard postal address information corresponds to an electronic identification of the user that is provided as the postal address of parcel or letter to be delivered to the user, in response to a determination that the non-standard postal address information corresponds to the electronic identification of the user, associating the non-standard postal address information with the electronic identification of the user, generating the postal address based on the non-standard postal address information and controlling at least one operation for shipping and delivery, communication and identification of the user based on the postal address.

Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller or processing device of a host system adds an entry to a local shared work queue of the host system. The entry includes an NVMe command to be executed by the SSD. The entry also includes an address for a shared work queue of the SSD. The controller or processing device writes the command to the shared work queue of the SSD using a PCIe memory write. The command is then executed by the SSD.

Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller of the SSD receives, in a shared work queue, commands from a host system (e.g., GPU). Each command specifies an address for a completion record. In response to receiving the command, the controller executes the command to perform an operation (e.g., read or write) identified in the command. Then, the controller writes the completion record to a location in main memory of the host system at the address.

Embodiments of this disclosure provide an address control circuit, a method for operating the address control circuit, and a memory controller. The memory controller includes: a processor that generates a first address; a first memory device that stores a first instruction corresponding to the first address; a second memory device; and the address control circuit. The address control circuit is configured to: receive the first address from the processor; determine whether the first address replacement information for the first address is registered in the address register of the address control circuit; provide the first address to the first memory device in response to determining that the first address replacement information is not registered; and provide a first replacement address corresponding to the first address to the second memory device based on the first address replacement information in response to determining that the first address replacement information is registered.

A data transfer method, apparatus, medium, and product based on a solid-state drive (SSD) are disclosed, relating to the field of SSDs. In this method, a data layout description header is obtained from host memory via direct memory access based on the target memory start address. The data layout description header is parsed through the SSD's flash translation layer to identify each data segment entry, and the length information and lifecycle attribute tag of the corresponding data segment are extracted from each entry. Based on the lifecycle attribute tag, a corresponding physical flash page is planned for each data segment as the target write address. Based on the target write address, the SSD is controlled to perform DMA operations segment by segment according to the order of the data segment entries in the data layout description header until the total data length is written. Implementing the technical solution provided in this application improves the data storage efficiency of the SSD.

The invention aims to enhance community disaster risk reduction and management (DRRM), especially in remote disaster-prone areas, through the implementation of as Raspberry Pibased smart pole technology, which integrates web-based emergency communication, monitoring, and emergency response features. The optimized smart pole will serve as a multifunctional hub, equipped with environmental sensors, LAN connectivity, intercom and public address control systems, and emergency alert capabilities.

Disclosed is a node address configuration method for a multi-node system. The multi-node system includes an address controller connected to one or more nodes. The address controller sends an address configuration command packet to the nodes connected to it, and the address configuration command packet includes a target node address and a target node configuration address. A node parses the address configuration command packet: if the target node address in the address configuration command packet is equal to the address identifier of the node, the node configures its address identifier as the target node configuration address; if the target node address is not equal to the address identifier of the node and the node includes a forwarding table, the node queries the forwarding table using the target node address and sends the address configuration command packet to the connected node through the transmission channel indicated by the forwarding table.

The invention discloses an error counter, an error counting method, computing equipment and a chip, and belongs to the field of memory management. The error counter comprises a control unit and n entries; the control unit is used for receiving a first error address; the control unit is used for distributing the item which is not accessed for the longest time in the n items as a first item corresponding to the first memory line under the condition that the first memory line corresponding to the first error address does not correspond to the item in the n items, and resetting the number of errors of storage of the first item; and the control unit is used for increasing the number of errors stored in the first entry under the condition that the first memory row corresponding to the first error address corresponds to the first entry in the n entries. According to the method and the device, the error counter simultaneously keeps the error times of a plurality of memory lines, and when software reads the error times of one memory line to repair the memory line, the error times of other memory lines can still be counted continuously, so that line missing errors are avoided.

Disclosed is a nonvolatile memory device which include a memory cell array including a plurality of memory cells connected to a plurality of word lines, an address decoder that controls a selected word line among the plurality of word lines based on an address received from an external device including a first temperature sensor, a second temperature sensor that measures a read temperature of first memory cells connected to the selected word line from among the plurality of memory cells, and a temperature compensation circuit that calculates a read level offset based on the read temperature and a program temperature of the first memory cells measured by the first temperature sensor and generates a compensation read voltage based on the read level offset. The address decoder is further configured to provide the compensation read voltage to the selected word line.

A facility device management system (100) comprises: a controller (10) that manages a facility device (30); a relay device (20) that relays communication between the controller (10) and the facility device (30); and a first facility device (31) that communicates with the controller (10) via the relay device (20). The controller (10) designates the device address of the relay device (20) in a device address field of communication data that corresponds to a prescribed communication protocol. The controller (10) divides a second field into a facility device address field and a data address field. The controller (10) designates the device address of the first facility device (31) in the facility device address field, designates the data address of the first facility device (31) in the data address field, and communicates with the relay device (20). The relay device (20) transfers the device address of the first facility device (31) included in the facility device address field to the device address field and communicates with the first facility device (31).

The embodiment of the invention provides a redundancy control circuit, a memory, a redundancy control method and electronic equipment, and the redundancy control circuit comprises an address comparison circuit which is configured to receive an input address and compare M-bit signals from high to low in the input address with M-bit signals from high to low in a fuse address according to bits to obtain M comparison signals; wherein N comparison signals in the M comparison signals are sequentially output to the address selection circuit, and other comparison signals except the N comparison signals are output to the address control circuit; an address selection circuit configured to select the N comparison signals or signals of the input addresses corresponding thereto as address selection signals based on a selection control signal, and output the address selection signals to the address control circuit; and an address control circuit configured to logically process the N address selection signals and the remaining comparison signals to output an activation signal whether to activate a repair unit corresponding to the fuse address.

The application provides a full-process automatic management method and system for a bare metal server, and the method comprises the following steps: automatically obtaining initial configuration information of a server to be managed; automatically allocating an out-of-band management network address for the server to be managed; controlling the server to be managed to start and load a memory operating system through a network, obtaining state information according to an identity in the memory operating system, and the state information is used to determine a preset processing operation to be executed; determining a target operation to be executed from the preset processing operation by a proxy process and executing the target operation; after the target operation is executed, if the state information indicates that node registration is needed, a node registration request is initiated to a cloud platform bare metal service, and the server to be managed is registered as a bare metal node; and after the server to be managed is successfully registered as the bare metal node, a switch port connected with the server to be managed is automatically configured, and batch installation verification is performed. The application realizes full-process automatic management of the bare metal server.

A nonvolatile memory device includes a plurality of latch groups, an address controller, an encoder, and a buffer. The address controller controls an input address and an output address to indicate one of the plurality of latch groups. The encoder receives sector data from a latch group corresponding to the output address among the plurality of latch groups and also compresses the received sector data. The buffer stores the compressed sector data. Among the plurality of latch groups, the compressed sector data stored in the buffer is overwritten in a latch group corresponding to the input address.

A nonvolatile memory device includes a plurality of latch groups, an address controller, an encoder, and a buffer. The address controller controls an input address and an output address to indicate one of the plurality of latch groups. The encoder receives sector data from a latch group corresponding to the output address among the plurality of latch groups and also compresses the received sector data. The buffer stores the compressed sector data. Among the plurality of latch groups, the compressed sector data stored in the buffer is overwritten in a latch group corresponding to the input address.

The application relates to the chip technical field and proposes a memory access method and device, a chip and a computer readable storage medium, the method comprises the following steps: in response to a reset request, obtaining memory configuration information, the memory configuration information at least comprises a memory decoding mode bit and a memory access effective bit; based on the memory configuration information, determining an address decoding mapping relationship between a core and a memory block; according to the address decoding mapping relationship and the virtual address of the core, controlling the core to initiate memory access. According to the application, the mapping relationship between different memory blocks in the virtual addresses corresponding to various cores is determined based on the memory configuration information, and the core is controlled to initiate memory access according to the mapping relationship, so that the base address information of the memory block required by the core to be accessed and the offset address corresponding to the core do not need to be considered, programs can be compiled according to the base address of the system memory block, the difficulty of software compilation is reduced, the probability of bus conflict caused by improper configuration is reduced, and the efficiency of memory access is improved.