44 results about "Resistor ladder" patented technology

The invention relates to a full-simulation non-multiplication and addition operation method and device for simulation in-memory calculation, and the method comprises the steps: training a target full model, and obtaining a corresponding weight and a batch normalization parameter, the batch normalization parameter comprising bias information and a zoom factor; based on the simulation in-memory calculation array and the simulation bias array, in combination with the weight and bias information, carrying out multiplication and addition operation and batch normalized bias calculation; generating a target reference voltage of the ReLU-ADC based on a global resistance ladder voltage divider or an analog bias array in combination with a scaling factor, and setting a DAC minimum output voltage thereof; and based on the target reference voltage and the minimum output voltage of the DAC, the ReLU-ADC performs full-simulation non-multiplication-addition operation on the bias multiplication-addition simulation calculation result. Therefore, the problems that in a traditional CIM architecture, a mode of completing non-multiplication and addition operation depending on a digital domain has significant bottlenecks in key performance indexes such as speed, power consumption and area, and the requirements of resource-limited scenes such as an intelligent sensor are difficult to meet are solved.

A programmable gain amplifier (PGA) architecture provides for robust operation over a bandwidth and for a multitude of gain settings. For instance, the PGA architecture may include multiple switches to implement different current paths by bypassing resistors in a resistor ladder. The different current paths may result in different gain settings. In some implementations, the switches may be used to hold a value of RA constant while a value of RB may be varied over the different gain settings, where gain may be inferred from the equation Vout=Vin*(1+RB / RA).

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion / mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

A multi-reference voltage generator, comprising: a current source; a set of resistors coupled in series with the current source between an upper voltage rail and a lower voltage rail; a first set of switching devices coupled between a first output and a set of taps at respective terminals of the set of resistors, wherein the set of taps includes a first tap and a second tap; a second set of switching devices coupled between a second output and the set of taps, respectively; a switching device coupled between the first tap and the second tap; and a control circuit including an output coupled to a control input of the switching device.

In one aspect, a high voltage interlock apparatus is provided for a vehicle. The high voltage interlock apparatus includes a resistive ladder having a plurality of interfaces to connect to a plurality of high voltage interlock loop components. The resistive ladder has an input to receive electrical power for the plurality of interfaces. The resistive ladder is configured to output a signal indicative of which of the plurality of high voltage interlock components have a fault condition.

An apparatus comprises a microcontroller including a digital potentiometer provided in a microcontroller packaging. The digital potentiometer includes a resistor ladder including a plurality of resistors arranged in series and a plurality of selectively controllable potentiometer switches, a first resistor terminal connected to the resistor ladder, and a wiper terminal connected to the resistor ladder. The microcontroller includes a processor to transmit a wiper select signal to the digital potentiometer to selectively control the potentiometer switches to selectively connect at least a subset of the resistors between the first resistor terminal and wiper terminal, to thereby control the resistance between the first resistor terminal and wiper terminal. The microcontroller includes a first pin connected to the first resistor terminal and a second pin connected to the wiper terminal, the first and second pins being exposed through the microcontroller packaging to allow connection of the digital potentiometer to an external device.

Example circuitry is usable in testing a device under test (DUT). The circuitry includes test inputs; a resistor ladder including resistors electrically connected in series, with the resistor ladder being electrically connected to each of the test inputs; and first operational amplifiers, with each first operational amplifier including a first input and a first output, with each first input being electrically connected to the resistor ladder, and with each first output to electrically connect to the DUT. The circuitry includes floating circuitry which includes a second operational amplifier. The second operational amplifier includes a second input electrically connected to the resistor ladder and a reference input; a first power input to receive a first voltage; and a second power input to receive a second voltage. The floating circuitry is configured to apply the first voltage and the second voltage to power inputs of each of the first operational amplifiers.

Modulation testing separately enables slices of an analog varactor array of an LC oscillator. For each enabled slice, a reference voltage supplying a resistor ladder is set to a plurality of different reference voltage values. Resistor ladder voltages generated for the different reference voltage values are supplied to the enabled slice and a control voltage coupled to the enabled slice is swept for each of the reference voltage values. Respective frequencies of an oscillator signal coupled to an output of the LC oscillator are measured for each enabled slice for each combination of the reference voltage values and the control voltage values. The linearity of LC oscillator gain is determined for each of the reference voltage values for each slice based on the respective frequencies and the control voltage values. Passing / failing the modulation testing is based on the linearity of the LC oscillator gain.

Systems and methods are provided for identifying a location of a thermal event detected by a temperature sensing tape. In some embodiments, the temperature sensing tape may include a resistance ladder with parallel resistors between a plurality of temperature sensing elements for creating a voltage divider, and unique analog output voltages may correspond to different ones of the plurality of temperature sensing elements that are activated. In some embodiments, pulses injected into and reflected by the temperature sensing tape may be used to detect a distance to a location where a trigger event is detected.

In one aspect, a high voltage interlock apparatus is provided for a vehicle. The high voltage interlock apparatus includes a resistive ladder having a plurality of interfaces to connect to a plurality of high voltage interlock loop components. The resistive ladder has an input to receive electrical power for the plurality of interfaces. The resistive ladder is configured to output a signal indicative of which of the plurality of high voltage interlock components have a fault condition.

An apparatus comprises a microcontroller including a digital potentiometer provided in a microcontroller packaging. The digital potentiometer includes a resistor ladder including a plurality of resistors arranged in series and a plurality of selectively controllable potentiometer switches, a first resistor terminal connected to the resistor ladder, and a wiper terminal connected to the resistor ladder. The microcontroller includes a processor to transmit a wiper select signal to the digital potentiometer to selectively control the potentiometer switches to selectively connect at least a subset of the resistors between the first resistor terminal and wiper terminal, to thereby control the resistance between the first resistor terminal and wiper terminal. The microcontroller includes a first pin connected to the first resistor terminal and a second pin connected to the wiper terminal, the first and second pins being exposed through the microcontroller packaging to allow connection of the digital potentiometer to an external device.

Analog-to-digital converters (ADCs) with background calibration processes are disclosed. In one aspect, an ADC with a plurality of comparators that each compare an input voltage to voltages that are generated at taps across a plurality of references (e.g., a reference resistor ladder). The comparators are initially calibrated with foreground calibration routines and continuously recalibrated to compensate for aging, voltage, and temperature variations without interrupting operation of the ADC by randomly taking one comparator of the plurality of comparators off-line to run calibration processes without replacing that comparator. The value for the off-line comparator may be reliably inferred from values from neighboring comparators or, in some cases, guessed randomly. While possible errors may be introduced, such errors may be driven to a mean square quantization noise level through exemplary aspects of the present disclosure.

A positive logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion / mismatch losses, and can withstand high RF voltages. Embodiments include a FET stack that includes series-coupled positive logic FETs (i.e., FETs that do not require a negative voltage supply to turn off) that are connected at least at one end by a positive logic FET at its V GS The "end cap" FETs of the type that are off at zero volts are coupled in series. One or more end cap FETs provide an optional capacitive DC blocking function or a resistive signal path. Embodiments include zero V only GS type of FET stack, or positive logic and zero V GS Type of FET with zero V GS Some embodiments withstand high RF voltages by combining a resistor ladder including a FET gate resistor, a drain-source resistor, a body charge control resistor, coupled in series or in parallel, with one or more AC coupling modules.

An apparatus includes a driver stage comprising a pull-up driver circuit coupled to a pull-down driver circuit. The apparatus includes a driver-supporting circuit coupled to the pull-up driver circuit and the pull-down driver circuit. The apparatus includes a resistor ladder coupled to the driver-supporting circuit. The apparatus includes an electrostatic discharge (ESD) protection circuitry coupled to the resistor ladder and an input / output (I / O) pad.

An apparatus comprises a microcontroller including a digital potentiometer provided in a microcontroller packaging. The digital potentiometer includes a resistor ladder including a plurality of resistors arranged in series and a plurality of selectively controllable potentiometer switches, a first resistor terminal connected to the resistor ladder, and a wiper terminal connected to the resistor ladder. The microcontroller includes a processor to transmit a wiper select signal to the digital potentiometer to selectively control the potentiometer switches to selectively connect at least a subset of the resistors between the first resistor terminal and wiper terminal, to thereby control the resistance between the first resistor terminal and wiper terminal. The microcontroller includes a first pin connected to the first resistor terminal and a second pin connected to the wiper terminal, the first and second pins being exposed through the microcontroller packaging to allow connection of the digital potentiometer to an external device.

In accordance with a first aspect of the present disclosure, an active RC-type filter is provided, comprising: an input, an output and a signal path between said input and output; at least one capacitor bank and at least one resistor bank, wherein said capacitor bank and resistor bank are integrated into the signal path; wherein the resistor bank comprises a plurality of resistor ladders; wherein each one of said resistor ladders comprises a plurality of resistors connected in series; wherein each one of said resistors has an input node configured to be coupled selectively to the signal path through one of a plurality of controllable switches; and wherein said resistor ladders have output nodes directly coupled to each other and to the signal path. In accordance with a second aspect of the present disclosure, a corresponding method of implementing an active RC-type filter is conceived.

The present disclosure provides a voltage divider circuit using a non-volatile memory device. The non-volatile memory device may include a memristor device, a magnetoresistive random access memory (MRAM) device, a phase change memory (PCM) device, a floating gate or a spin electronic device, etc. The voltage divider circuit may include one or more non-volatile memory devices forming a resistor ladder circuit that may generate a reference voltage when the resistor ladder circuit is connected between two voltages. The present disclosure further provides a comparator using a non-volatile memory device and an analog-to-digital converter (ADCs) using the comparator. The comparator may be used to compare an analog input voltage to a reference voltage and to generate a digital output indicative of a result of the comparison. The digital output may represent a resistance state of the non-volatile memory device when applied to the comparator in response to the reference voltage and the analog input voltage.

The embodiment of the invention provides a resistance gradient effect compensation method and a voltage sampling circuit, and the method comprises the steps: dividing a divider resistor in the voltage sampling circuit into a high-order divider resistor and a low-order divider resistor, the high-order divider resistor and the low-order divider resistor are three-end resistors, connecting the third end of the high-order divider resistor with a power supply voltage, and connecting the second end of the low-order divider resistor with a power supply voltage; the third end of the low-level divider resistor is connected with sub potential; and adjusting the number of serially connected resistors of the high-level divider resistor, so that the deviation between the total resistance value of the high-level divider resistor and the low-level divider resistor and a target value is smaller than a preset deviation, and the target value is the sum of the ideal resistance values of the high-level divider resistor and the low-level divider resistor.

Systems and methods for identifying a location of a thermal event detected by a temperature sensing tape are provided. In some embodiments, the temperature sensing tape can include a resistive ladder with parallel resistors between a plurality of temperature sensing elements to create voltage dividers, and unique analog output voltages can correspond to different ones of the plurality of temperature sensing elements being activated. In some embodiments, pulses injected into and reflected by the temperature sensing tape can be used detect a distance to a location where a triggering event is detected.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion / mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

A hybrid digital-to-analog converter (DAC) driver is provided. The hybrid DAC driver includes an upper DAC stage configured to receive an upper set of bits of a digital signal, the upper DAC stage comprising an upper set of DAC units, with a first DAC unit in the upper set of DAC units having a different weight than a second DAC unit in the upper set of DAC units; a lower DAC stage configured to receive a lower set of bits of the digital signal, the lower DAC stage comprising a lower set of DAC units formed in an R-2R resistor ladder network; and an output stage for outputting an analog signal from the upper DAC stage and the lower DAC stage.

The utility model provides a liquefied air energy storage rock breaking device for tunnel excavation, and relates to the technical field of tunnel engineering construction devices, the liquefied air energy storage rock breaking device for tunnel excavation comprises a blasting pipe, an impact pipe and a tensioning sleeve, the blasting pipe is of a hollow cylindrical structure, and a blasting cavity filled with liquefied air is formed in the blasting pipe. A heating component capable of conducting gradient heating is arranged at the top of the blasting cavity, and a connecting shaft arranged at one end of the blasting pipe is further included in a preferable scheme. Through cooperation of the structures, the rock breaking device has the following beneficial effects that firstly, the outer ring of the tensioning sleeve is tensioned and fixed to the inner wall of the rock breaking hole, and the tensioning sleeve can prevent the problem of pipe flying caused by the fact that the rock breaking device flies out of the rock breaking hole due to the counter-acting force in the rock breaking process of the impact rod; and secondly, resistors in three different areas are arranged on a heating part, a resistance gradient with the high front part and the low rear part is formed, sectional type gasification is achieved, uncontrollable pressure impact caused by instantaneous energy concentration is avoided, and therefore the blasting pipe is prevented from being rushed out.

The embodiments of this disclosure provide a method for compensating for the resistance gradient effect and a voltage sampling circuit. The method includes: dividing the voltage dividing resistors in the voltage sampling circuit into high-order voltage dividing resistors and low-order voltage dividing resistors, both of which are three-terminal resistors; connecting the third terminal of the high-order voltage dividing resistor to the power supply voltage; and connecting the third terminal of the low-order voltage dividing resistor to the sub-potential; and adjusting the number of series resistors in the high-order voltage dividing resistors so that the deviation between the total resistance of the high-order and low-order voltage dividing resistors and the target value is less than a preset deviation, wherein the target value is the sum of the ideal resistance values ​​of the high-order and low-order voltage dividing resistors.

An example apparatus includes: resistor ladder circuitry including a plurality of intermediate voltage nodes; a first plurality of switches having inputs coupled to a plurality of intermediate voltage nodes and having outputs; first level decoder circuitry configured to: receive a set of input bits; and open or close ones of the first plurality of switches based on a first subset of the input bits; a second plurality of switches having inputs coupled to the outputs of the first plurality of switches and having outputs coupled to a common node; and second level decoder circuitry configured to: receive the set of input bits; and open or close ones of the second plurality of switches based on a second subset of the input bits, the first and the second subsets sharing one of the input bits, wherein the output voltage is to be coupled to the common node.

Example circuitry is usable in testing a device under test (OUT). The circuitry includes test inputs; a resistor ladder including resistors electrically connected in series, with the resistor ladder being electrically connected to each of the test inputs; and first operational amplifiers, with each first operational amplifier including a first input and a first output, with each first input being electrically connected to the resistor ladder, and with each first output to electrically connect to the OUT. The circuitry includes floating circuitry which includes a second operational amplifier. The second operational amplifier includes a second input electrically connected to the resistor ladder and a reference input; a first power input to receive a first voltage; and a second power input to receive a second voltage. The floating circuitry is configured to apply the first voltage and the second voltage to power inputs of each of the first operational amplifiers.

An apparatus comprises a microcontroller including a digital potentiometer provided in a microcontroller packaging. The digital potentiometer includes a resistor ladder including a plurality of resistors arranged in series and a plurality of selectively controllable potentiometer switches, a first resistor terminal connected to the resistor ladder, and a wiper terminal connected to the resistor ladder. The microcontroller includes a processor to transmit a wiper select signal to the digital potentiometer to selectively control the potentiometer switches to selectively connect at least a subset of the resistors between the first resistor terminal and wiper terminal, to thereby control the resistance between the first resistor terminal and wiper terminal. The microcontroller includes a first pin connected to the first resistor terminal and a second pin connected to the wiper terminal, the first and second pins being exposed through the microcontroller packaging to allow connection of the digital potentiometer to an external device.

Technologies are provided for variable gain amplifiers (VGAs). An example VGA includes a resistor ladder network comprising resistor legs coupled to a first plurality of resistors and a second plurality of resistors, a first set of differential switches connected to the resistor ladder network, a second set of differential switches connected to a set of output nodes, a third set of differential switches connected to the resistor ladder network, a fourth set of differential switches connected to the set of output nodes, and a fifth transistor and a sixth transistor comprising a differential pair coupled to a differential input signal. The fifth transistor is connected to the first set of differential switches and the sixth transistor connected to the third set of differential switches.

An example circuit may be used to test a device under test (OUT). The circuit includes a test input; a resistor ladder comprising resistors electrically connected in series, where the resistor ladder is electrically connected to each of the test inputs; and first operational amplifiers, where each first operational amplifier comprises a first input and a first output, where each first input is electrically connected to the resistor ladder, and where each first output is electrically connected to the OUT. The circuit includes a floating circuit including a second operational amplifier. A second operational amplifier including a second input electrically connected to the resistor ladder and the reference input; the first power input end is used for receiving a first voltage; and a second power input for receiving a second voltage. The floating circuit is configured to apply a first voltage and a second voltage to a power input of each of the first operational amplifiers.

The present disclosure relates to compensating for temperature variation of a mixer. Embodiments herein may include the mixer, a calibration circuit coupled to the mixer, a replica mixer circuit coupled to the calibration circuit, and a temperature compensation circuit coupled to the calibration circuit. The replica mixer circuit may generate or be used to generate a reference voltage that varies with a common mode voltage and / or a threshold voltage of a replica mixer. The reference voltage may be applied to a resistor ladder of the calibration circuit to adjust a bias voltage and compensate for temperature variations. Further, the temperature compensation circuit may generate a temperature coefficient that may be applied to a current going through the calibration circuit to facilitate compensating for temperature variation.

The invention relates to an on-chip open circuit, short circuit and LED voltage detection method for a micro LED or a micro OLED. A micro light emitting diode micro LED display includes a plurality of rows of light emitting diode LEDs, each of the LEDs in a row including a channel, where each channel includes: a feedback path configured to feed an anode voltage of each LED to an input of a voltage comparator; a column driver including a digital-to-analog converter (DAC) and the voltage comparator, where the DAC is configured to receive a plurality of voltage inputs from the resistor ladder and to provide a corresponding plurality of voltage outputs to the inputs of the voltage comparator, and wherein the voltage comparator is configured to continuously compare individual voltage outputs of the plurality of voltage outputs received from the DAC with the anode voltage of each LED; and a data latch configured to store a comparison result from the voltage comparator.