149 results about "Channel width" patented technology

Aspects of the present disclosure improve wireless networking performance by reducing or limiting performance issues caused by undetected or unknown interference sources and / or attenuation sources. Feedback from client devices can be utilized to reduce or limit wireless network performance issues caused by varying interference parameters and / or attenuation parameters observed by each client device. The feedback, associated with wireless communication conditions of corresponding client devices, in conjunction with a machine learning algorithm can be used to enable a dynamic selection of one or more particular operating bands, channels, and / or channel widths to avoid or limit signal interference and / or signal attenuation observed by each client device. Feedback from a plurality of client devices can be used to recommend one or more channels and / or one or more channel widths of one or more operating bands to use that reduces latency, CCI, and / or ACI and improves speed, throughput, and / or QoS.

Described herein are devices, systems, methods, and processes for optimizing the utilization of large bandwidth channels in wireless communication networks. This is achieved by an access point (AP) identifying parts of the channel available for standard power (SP) transmissions and using novel puncturing messages to allow simultaneous low-power indoor (LPi) transmissions on the “punctured” parts of the channel. The AP can implement different modes to allow concurrent transmissions at SP level on the SP-allowed parts of the channels and at LPi level on part of the channel that do not allow SP transmissions. The AP can also switch unicast communication with a client device to LPi but with a larger channel width as the device nears the AP. The techniques allow for fuller utilization of large bandwidth channels where only a part of the channel is available for SP transmissions, thereby improving network efficiency.

Disclosed are a method and apparatus for transmitting or receiving a physical layer protocol data unit (PPDU) including a multiple access point operation-related preamble in a wireless LAN system. According to an embodiment of the present disclosure, a method performed by a first station (STA) comprises: receiving, from a second STA, a first portion of a PPDU including one or more signal (SIG) fields related to information of a multiple access point (AP); and receiving, from the second STA, a second portion of the PPDU, on the basis of information included in the one or more SIG fields related to the information of the multiple AP, wherein the one or more SIG fields related to the information of the multiple AP may have different formats on the basis of whether the minimum channel width allocated to the multiple AP is equal to or greater than 80 MHz.

Methods, apparatuses, and computer readable media for basic service set (BSS) channel operation are disclosed. Apparatuses of a station (STA) are disclosed, where the apparatuses comprise processing circuitry configured to decode a first frame, the first frame comprising an extremely-high throughput (EHT) operation information field, the EHT operation information field comprising a channel width subfield and a channel center frequency segment, the channel width subfield indicating a basic service set (BSS) contiguous channel width, and the channel center frequency segment indicating a channel center frequency for the BSS channel width on which the BSS operates in 6 GHz. The processing circuitry further configured to encode for transmission a second frame for transmission on a primary channel within the BSS channel width.

A method and apparatus for indicating an operating mode for an extended bandwidth in a wireless LAN system are disclosed. A method performed by a station (STA) in a wireless LAN system according to an embodiment of the present disclosure may include generating a frame including information regarding an indication of an operating channel width, and transmitting a PPDU including the frame. Here, the information regarding the indication of the operating channel width may be included in an operating mode (OM) control subfield within an aggregated-control (A-control) field of the frame, and the OM control subfield may include a specific subfield capable of indicating a wide bandwidth greater than 320 MHz.

A method for producing a nanochannel (200) is described with the following steps a) depositing a nanochannel sacrificial layer (3) using an ALD process on a substrate (1), which defines the subsequent channel height at least at one point b) depositing a first covering layer (4) on the nanochannel sacrificial layer (3) c) At least partially structuring and / or etching the nanochannel sacrificial layer (3) and the first cover layer (4) so ​​that a first exposed region (10) is formed d) At least partial etching of the now exposed nanochannel sacrificial layer (3) with an etching rate < 100nm / min, preferably <10nm / min, and particularly preferably <5nm / min and even more preferably <2nm / min, so that an under-etched second exposed region (20) is formed which defines the channel width e) depositing a second cover layer (5) onto the first cover layer (4) and the first exposed region (10) so that the second exposed region (20) is sealed and forms a nanochannel (200).

The invention relates to the technical field of nano photonics and metasurfaces, in particular to a metasurface sensor based on a non-radiative dark state, which comprises a quartz substrate and dumbbell-shaped slotted silicon blocks arranged on the surface of the quartz substrate periodically; the dumbbell-shaped slotted silicon block is composed of two symmetrical circular slots and a rectangular channel connecting the two circular slots, the period P of the dumbbell-shaped slotted silicon block is 600-1000 nm, the length and width p of the silicon block are 500-700 nm, the height H of the dumbbell-shaped slotted silicon block is 80-120 nm, the width a of the channel is 15-30 nm, the length b of the channel is 30-50 nm, and the radiuses R1 and R2 of the initial circular slots are 70-100 nm. The device can excite two non-radiation modes at the same time, namely, an anapole mode and a quasi-continuous domain bound state (q-BIC) mode. By designing the dielectric metasurface structure composed of the dumbbell-shaped slotted silicon block and the quartz substrate, the high Q factor and strong electric field enhancement effect is achieved, and the device not only has excellent optical performance, but also shows high sensitivity and modulation depth in multiband sensing, and is suitable for high-precision optical sensing application.

A read-port of a Static Random Access Memory (SRAM) cell includes a read-port pass- gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. A write-port of the SRAM cell port includes at least a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. The R_PG transistor, the R_PD transistor, the W_PG transistor, the W_PD transistor, and the W_PU transistor are gate-all-around (GAA) transistors. The R_PG transistor has a first channel width. The R_PD transistor has a second channel width. The W_PG transistor has a third channel width. The W_PD transistor has a fourth channel width. The W_PU transistor has a fifth channel width. The first channel width and the fourth channel width are each smaller than the second channel width. The third channel width is greater than the fifth channel width.

A system including a memory controller chiplet having a memory interface that is configured to couple the memory controller chiplet to first and second memory devices. The memory interface includes first and second memory channels having respective data widths, and configured to couple first and second I / O interfaces of the memory controller chiplet to an interface of the first memory device having a data channel width at least equal to the combined first and second memory channel widths, where the first and second memory channels have independent command / address (CA) paths; and third and fourth memory channels having respective data widths, and configured to couple third and fourth I / O interfaces of the memory controller chiplet to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have independent CA paths.

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

The invention discloses a channel mobility testing method, a channel mobility testing structure and a manufacturing method of the channel mobility testing structure. The channel mobility test method comprises the following steps: applying test voltage to source electrodes, drain electrodes and grid electrode structures of at least two different semiconductor devices, and determining resistance between the source electrode and the drain electrode of each semiconductor device; wherein the channel widths of at least part of the semiconductor devices in the at least two different semiconductor devices are different; the channel width is the width of the well region between the JFET region and the first region in the direction from the first region to the JFET region; measuring the resistance between the source electrode and the drain electrode of each semiconductor device; and determining the channel mobility of each semiconductor device according to the resistance between the source electrode and the drain electrode of each semiconductor device and the channel width of each semiconductor device. According to the embodiment of the invention, the measurement of the channel field effect mobility can be realized, the measurement mode is simple, and the measurement efficiency is high.

The invention relates to a design method of an elastic circular ring bubble-shaped buckling structure under double-circular-ring constraint. An inner constraint circular ring with the radius being r, an outer constraint circular ring which is concentric with the inner constraint circular ring and has the radius being R and an elastic circular ring which is located in a channel between the inner constraint circular ring and the outer constraint circular ring and has the perimeter being L, the thickness being h and the width being b are included. Lambda = L / 2pi R is the perimeter ratio of the elastic circular ring to the constraint circular ring, and mu = (R-r) / R is the width of the dimensionless constraint channel; when 0 lt; lambda < lt >; when lambda is 1, the elastic circular ring is attached to the outer constraint circular ring to keep a circular ring structure; when the perimeter of the elastic circular ring is increased, lambda 1lt; lambda < lt >; when lambda is 2, the elastic circular ring generates a bubble-shaped buckling structure which is not in contact with the inner constraint circular ring; when lambda 2lt; lambda < lt >; when lambda < 3 > is greater than lambda < 3 >, the elastic ring generates a bubble-shaped buckling structure in contact with the inner constraint ring; when lambda is 3lt; when lambda is greater than lambda, the elastic circular ring generates an inclined bubble-shaped buckling structure. The method is beneficial for accurately predicting the critical strain when the elastic ring bubble-shaped buckling structure is generated and finished.

The invention provides a thermal resistance model construction method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device, which is characterized in that a plurality of N-type doped isolation layers are formed on a substrate, an LDMOS structure is formed on each N-type doped isolation layer, all LDMOS structures are divided into different test groups according to different key sizes, and the key sizes at least comprise a total channel width and a cross index; measuring the thermal resistance of the LDMOS structure in each test group so as to respectively extract a thermal resistance value array of each group, and performing data fitting on the thermal resistance value array of each group so as to obtain a thermal resistance model of the relationship between the thermal resistance value of the LDMOS structure and the critical dimension; according to the method, the thermal resistance model of the full-size LDMOS device can be constructed by only utilizing a limited number of LDMOS structures in a primary tape, so that the thermal resistance of the LDMOS devices with different sizes can be predicted, the self-heating effect of the device can be accurately evaluated in the design stage, the device design is optimized, the development cost of the device is reduced, and the research and development period is shortened.

This invention provides a modeling method for metal-oxide-semiconductor semiconductors, comprising: establishing an initial sub-circuit simulation model, as follows: where Y_MF is the multi-interdigitation effect correction parameter, NF is the interdigitation index of the gate of the MOS device, and X... nf0 A, X nf1 B, X nf2 C, X nf3 D, X nf4 E, X nf5 F and W are both fitting parameters, W is the channel width, L is the channel length, and X is the channel length. nf6 To obtain the fitting parameters, multiple measured electrical characteristic parameters of metal-oxide-semiconductor semiconductors under different interdigitation indices, different channel widths, and different channel lengths are obtained. The fitting parameters are adjusted so that the errors of the multi-interdigitation effect correction parameters obtained from simulations under different interdigitation indices, different channel widths, and different channel lengths are all within the set values. The corresponding fitting parameter values ​​are then determined. The following multi-interdigitation effect model is established: Y = K + Y_MF.

A semiconductor device according to the present disclosure includes a first base fin and a second base fin extending from a substrate, an isolation feature disposed between the first base fin and the second base fin, a first dummy epitaxial layer disposed on the first base fin, a second dummy epitaxial layer disposed on the second base fin, a first insulator layer over the first dummy epitaxial layer, a second insulator layer over the second dummy epitaxial layer, a first source / drain feature disposed on the first insulator layer, a second source / drain feature disposed on the second insulator layer. A thickness of the first dummy epitaxial layer measured from a top surface of the first base fin is smaller than a thickness of the second dummy epitaxial layer measured from a top surface of the second base fin.

The present invention provides a novel SiC MOSFET power device, comprising: a substrate; a drain metal layer disposed under the substrate; a drift region disposed on the substrate; a well region disposed on the drift region; a source region disposed on the well region; a channel region disposed on the well region; a trench disposed parallel to the direction of channel current in the channel region and passing through the channel region and reaching the source region; a gate metal layer disposed on the trench; and a source metal layer disposed on the gate metal layer. The present invention can increase the channel width of the trench sidewalls, and because different surfaces of silicon carbide have different electron mobilities, a side with relatively high electron mobility can be selected, thereby ensuring that the electron mobility of the inversion layer of the trench sidewalls is higher than that of the inversion layer on the device surface, thereby effectively reducing the channel resistance of the device.

An SRAM device and its formation method are disclosed. The formation method includes: providing a substrate comprising a first type of device region and a second type of device region; the first type of SRAM device having a maximum channel width; both the first and second type of device regions comprising a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region; forming a stacked structure on the substrate, comprising a first sacrificial layer and a channel layer; the width of each stacked structure in the second type of device region being equal to a preset width of the corresponding transistor region in the first type of device region; performing a channel width adjustment process; in the second type of device region, removing a portion of the channel layer width from any one or two of the transistor regions (transmission gate transistor region, pull-down transistor region, and pull-up transistor region); after removing the portion of the channel layer width, removing the first sacrificial layer; and after removing the first sacrificial layer, forming a gate structure spanning the channel layer. This invention uses the same design layout to form the stacked structure, saving design costs.

The invention provides a two-dimensional extensible sub-array based on a long and narrow circuit channel, and relates to the technical field of millimeter wave / terahertz frequency band phased array front-end, and the two-dimensional extensible sub-array comprises a plurality of two-channel sub-arrays; taking the two-channel sub-array as a standard sub-array module, and expanding the standard sub-array module to a target channel number step by step through cascading in a two-dimensional direction; the two-channel sub-array comprises a two-channel chip and a two-channel antenna sub-array; the two-channel chip comprises two circuit channels which are distributed side by side, and respective antenna ports, common ports and signal flow directions of the two circuit channels are opposite; each antenna unit in the two-channel antenna sub-array covers one side, close to the antenna port, of the corresponding circuit channel; wiring modes and lengths of interconnection lines between the two antenna ports and the corresponding antenna signal feed points are consistent; the width of the circuit channel does not exceed 0.25 lambda, and the length of the circuit channel does not exceed 1 lambda. Standard sub-arrays can be modularized, a large-scale two-dimensional extensible full array is supported, main hot spots are dispersed, and uniform heat dissipation is facilitated.

The invention discloses a flow battery performance improvement method based on flow channel geometrical shape optimization, and provides a calculation formula of a performance optimal coefficient (POC) in order to solve the problem of multi-parameter coupling in a traditional flow channel design method. Through the formula, an optimal coefficient can be calculated according to geometric parameters (such as flow channel width, rib width, sectional area, diagonal length, flow velocity and the like) of the flow channel, and the optimal coefficient is used for quantifying the influence of different flow channel geometric shapes on the battery performance. The formula not only simplifies the complex flow channel design process, but also can accurately predict the performance of the geometric structure of the flow channel in practical application. By accurately controlling parameters such as runner width, rib width, flow velocity, pump power and the like, the energy loss can be reduced while the optimal battery performance is maintained.

Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced. Specifically, an oxide semiconductor whose band gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV is used for a semiconductor layer of a transistor, and the concentration of an impurity which serves as a carrier donor included is reduced. Consequently, the off current of the transistor per micrometer in channel width can be reduced to lower than 10 zA / μm at room temperature and lower than 100 zA / μm at 85° C.

An access point may include a processing device configured to: identify a puncturing pattern for a channel width of a physical layer protocol data unit (PPDU) of a transmit signal; compute one or more tone rotation patterns using one or more tone rotation pattern parameters; and select a tone rotation pattern of the one or more tone rotation patterns based on the puncturing pattern for the channel width to minimize a peak to average power ratio (PAPR) of the transmit signal. The access point may include a transceiver configured to transmit the transmit signal to a wireless device based on the tone rotation pattern.

A MEMS having a fluid channel in at least one MEMS layer is provided. The fluid channel is designed to provide fluid connection between a first channel side and a second channel side. The sidewall structure of the fluid channel includes a scallop-shaped component, wherein, due to the scallop-shaped structure, the acoustic channel has an effective acoustic channel width that is enlarged compared to the nominal channel width.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises an epitaxial layer; the drift region and the body region are located in the epitaxial layer; the gate structure is located on the epitaxial layer and stretches across the drift region and the body region; the drain injection region is positioned in the drift region; the source injection region and the plurality of body region injection regions are positioned in the body region; wherein the source injection region comprises a plurality of first source injection regions and a plurality of second source injection regions; the plurality of first source injection regions and the plurality of body region injection regions are alternately distributed in the channel width direction of the LDMOS device; and the plurality of second source injection regions are respectively positioned in the side edge regions, facing the gate structure, of the plurality of body region injection regions so as to form the source injection regions which are communicated along the width direction of the channel. According to the scheme, the N-type injection region is additionally arranged on the polycrystalline silicon channel side of the device to achieve channel compensation, and balance among the cellular pitch, the leakage current and the electric safety working region of the device is better achieved under the condition that the specific on-resistance of the device can be reduced.

The invention provides a semiconductor device with good reliability and a method for manufacturing the semiconductor device. A semiconductor device including a transistor, the transistor including: a first insulator; a second insulator; a first oxide; a second oxide; a third oxide; a first conductor and a second conductor; a third insulator; a third conductor; a fourth insulator; and a fifth insulator. The fourth insulator and the fifth insulator are provided with openings that reach the second oxide, and a third oxide, a third insulator, and a third conductor are provided in this order from the inner wall side of the openings so as to be embedded in the openings. In a channel length direction of the transistor, at least a portion of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap is in contact with the first insulator. In a channel width direction of the transistor, at least a portion of the third oxide in a region where the third oxide and the second oxide do not overlap is in contact with the first insulator.

The application relates to a parameter determination method of a thin film transistor, a preparation method and a display panel. The parameter determination method comprises the following steps: obtaining design parameters of the thin film transistor, wherein the design parameters comprise at least one of a threshold voltage, a channel width, a channel length, a ratio of the channel width and the channel length and a preparation process coefficient; determining target parameter information according to the design parameters and a design relationship corresponding to the thin film transistor; and the design relationship represents the correlation between the threshold voltage, the channel width, the channel length, the ratio of the channel width and the channel length and the preparation process coefficient. The parameter determination method of the thin film transistor provided by the application can realize the target that each thin film transistor meets the circuit working requirement at the same time.

The present application relates to a kind of intelligent warehousing systems for latex matrix ground station applied to the technical field of intelligent warehousing, the system includes warehouse, multiple densely arranged shelves, multiple AGVs and central dispatch system. Formed between the shelves and the inner wall of the warehouse one-way traffic loop network by multiple channel segments, channel width and the minimum safe traffic width required for a single AGV match, central dispatch system plans path for AGV executing task, and generates reservation occupancy time window for channel segment passed by it, and then maintains global space-time table to detect space-time conflict between AGVs in real time;When detecting conflict, the system dynamically calculates the traffic priority of conflict AGV, and instructs low-priority AGV to stagger its time window through speed regulation, thereby fundamentally avoiding deadlock.The present application realizes efficient, continuous and reliable operation of the system while ensuring space utilization.

The invention relates to a parameter determination method and device of a circuit simulation model, a medium, equipment and a product, and the method comprises the steps: obtaining a first capacitance value of a first MOS structure, and a first channel width and a first channel length of a first MOS device in the first MOS structure, the first MOS structure comprises n first MOS devices which are connected in parallel, the first channel widths of the first MOS devices are the same, and n is a positive integer; the lengths of first channels of the first MOS devices are the same, each first MOS device comprises a first active region and a first gate region arranged above the first active region, and n is a positive integer greater than 1; and determining a parameter DLC of a circuit simulation model SPICE according to the first capacitance value, the first channel width and the first channel length. According to the scheme, the parameter DLC of the SPICE model is accurately determined, so that an accurate reference basis is provided for establishment of the SPICE simulation model of the MOS tube.

The invention provides a semiconductor packaging device and a semiconductor wiring board thereof. The semiconductor wiring board comprises at least one circuit layer, at least one dielectric layer and a redistribution layer. The at least one circuit layer comprises a plurality of signal wires and a plurality of grounding wires which are arranged alternately, and has a channel width. The at least one dielectric layer is disposed between the at least one circuit layer. The redistribution layer is disposed over the at least one circuit layer for placement of the first and second solder bumps, and includes first and second metal contacts. The first and second solder bumps are electrically connected to the at least one circuit layer via the first and second metal contacts, respectively, such that the channel width is greater than the distance between the first and second solder bumps. Through the redistribution layer, a plurality of signal wires and a plurality of grounding wires which are alternately arranged can be configured according to design requirements under the condition that the distance between the first welding convex block and the second welding convex block is not adjusted, so that the semiconductor wiring board has the advantages that the channel width is relatively wide, the wiring flexibility is improved, the signal integrity is improved, the cost is reduced and the like.

An integrated digital RF circuit system includes: a substrate, the substrate including a substrate integrated waveguide, the substrate integrated waveguide including a waveguide width, a first plurality of vias and a second plurality of vias; and a source circuit board including a waveguide channel, wherein: the waveguide channel is at least partially positioned between the first plurality of vias and the second plurality of vias; the waveguide channel defines a channel length and a channel width; the channel length is greater than the channel width; and the channel length is greater than the waveguide width.

A system and method are described herein. The system comprises a wavelength selective switch having a minimum passband width; a processor; and a memory storing a datastore and processor-executable instructions that when executed cause the processor to: receive a connection request comprising an optical channel; determine an affinity group ID of an affinity group associated with the requested optical channel, the affinity group being associated with two or more adjacent optical channels having a combined channel width equal to or greater than the minimum passband width; create a loading group based on the two or more adjacent optical channels associated with the affinity group; receive a loading request to load the optical channel associated with the affinity group; and in response to receiving the loading request, load the two or more adjacent optical channels associated with the affinity group.