168 results about "Design flow" patented technology

High-level synthesis (HLS) is a complex design flow that exploits the benefit of modern language features such as loops, inheritance, templates, etc. for rapid prototyping of hardware designs. Hardware engineers explore various design space parameters in a time-consuming trial-and-error approach to meet a target design specification. This invention provides a framework where machine learning methods are integrated with Bayesian optimization (BO) to accelerate hardware design in HLS. This tool is built around the context of HLS pragma exploration and kernel transformation. It can produce best set of pragma installments to determine parameters by optimizing on multi-objective functions, such as reduction of digital signal processor, flip-flop, look-up table, power consumption, and latency. The method uses classical deep neural network and quantum neural network for reinforcement meta learning to predict the synthesis characteristics and synthesizability under a given time budget. A large language model can also assist transpilation to modify the original codes so that the best tradeoff between hardware complexity, latency, and power consumption is realized.

The invention relates to the technical field of building design and digitization, and discloses an automatic design method for a special-shaped facing structure based on parametric modeling. The method comprises the following steps: firstly, acquiring a geometrical characteristic parameter set of the special-shaped facing structure, wherein the geometrical characteristic parameter set comprises curved surface curvature distribution, boundary constraint conditions and a material attribute threshold value; thirdly, according to the curved surface curvature distribution, generating an initial geometric topological grid by using a dynamic subdivision algorithm, adjusting node positions according to boundary constraint conditions to obtain an optimized structural framework, and performing layered mapping on material attribute thresholds to generate a material distribution map; then, the input parametric modeling engine generates a three-dimensional parametric model, finally, a self-adaptive adjustment strategy graph is constructed through a multi-objective optimization algorithm, and a final design scheme is output. By means of the method, automation of design of the special-shaped facing structure is achieved, design efficiency and accuracy are improved, material utilization is optimized, scheme adaptability is enhanced, and design process collaboration is improved.

The invention discloses a product collaborative design management method and system based on data driving, and relates to the technical field of product design management, and the method comprises the steps: constructing a double-flow heterogeneous quantitative collection network; establishing an incidence matrix and calculating dynamic coupling strength among the parameters; designing a recursive deep belief network based on the incidence matrix and the dynamic coupling strength, encoding product structure parameters and design process data into a probability graph model, and constructing a design knowledge base; dynamically distributing the design rules in the design knowledge base by adopting a swarm intelligent optimization algorithm, generating a collaborative decision-making unit, and establishing a constraint propagation link; and generating a multi-target collaborative optimization scheme group, and screening an optimal scheme group based on Pareto frontier. According to the invention, omnibearing acquisition of product structure parameters and design flow data is realized through the double-flow heterogeneous quantitative acquisition network, and the data integrity is improved.

The invention discloses a digital back-end full-process script design method, and relates to the field of digital integrated circuit design, and the method comprises the steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file valeeb.tcl; a gate-level netlist and a corresponding comprehensive report are generated by using a library configuration file valerib.tcl; performing logic synthesis according to the behavior level netlist and the make syn to generate a gate level netlist, and generating layout and wiring data through make out; according to the layout and wiring data, antenna inspection is carried out through a make ant command, design rule inspection is carried out through a make drc command, and comparison inspection of a generated layout and a schematic diagram is carried out through a make lvs command; performing power consumption analysis according to the layout and wiring data; and performing IR analysis according to the parasitic parameters. Aiming at the problem that the chip digital back-end design process is low in efficiency in the prior art, the design efficiency is improved.

The invention discloses an automatic integrated system from an asynchronous pipeline to an asynchronous circuit, which adopts a modular architecture, takes a high-level structure description file in a JSON / XML format as input, and gradually maps to generate a gate-level netlist and a standard delay format file so as to be in butt joint with a commercial back-end design process. According to the method, asynchronous design based on an asynchronous structure can be automatically mapped into an asynchronous circuit, the automatic mapping process can seamlessly process multi-level design representation, the mapping result is stable and cooperatively operated, asynchronous circuit time sequence detection and delay matching are automatically completed, the design efficiency is greatly improved, and the design cost is reduced. An automatic delay matching mechanism enables the circuit to have a good data ready detection and handshake mechanism, and the characteristics of low power consumption, high throughput and no global clock drift sensitivity are realized; in addition, automation of asynchronous design key links such as structure abstraction, time delay modeling and testability insertion is achieved while design readability, hierarchical consistency and time sequence controllability are guaranteed.

The invention discloses a W-band coupling multi-band filter parameter optimization method, which is characterized in that each step from the determination of an ideal characteristic function to the adjustment of a final performance index has a clear guidance and optimization target through a systematic design process, so that the design efficiency is improved, and the design cost is reduced. And the frequency response characteristic of the filter can accurately meet the expectation. The design indexes of the filter, such as center frequency and bandwidth, are determined, so that the design process is more accurate, and the filter can meet the requirements of a specific communication system. And the accurate coupling matrix is automatically generated by utilizing the coupling matrix comprehensive software, so that the design efficiency and accuracy are improved. By converting the coupling matrix into specific physical design parameters, detailed guidance is provided for actual manufacturing of the filter, and seamless joint from design to manufacturing is ensured. The resonant frequency of the resonant cavity is calculated to ensure that the filter works at the predetermined frequency, and the selectivity and insertion loss performance of the filter are improved.

The invention provides a digital-analog hybrid circuit design method, device and equipment and a storage medium, and the method comprises the steps: constructing a simulation auxiliary unit library for a simulation module needing to be used in a digital-analog hybrid circuit; in the RTL (Register Transfer Level) design stage, the digital standard cell library and the analog auxiliary cell library are called to carry out digital-analog hybrid circuit design, and a digital-analog hybrid circuit is obtained; automatically generating a layout of the digital-analog hybrid circuit through a digital back-end tool; and after physical verification and parasitic parameter extraction are carried out on the layout of the digital-analog hybrid circuit, post-simulation verification is carried out. Therefore, layout generation of the digital-analog hybrid circuit can be automatically completed, a schematic diagram and a layout of a top layer do not need to be completed manually, the design process is greatly simplified, and the design period is shortened. For a process migration scene, only a small number of simulation auxiliary units need to be redesigned, codes of other digital parts can be reused and rapidly modified, and the designed process migration efficiency is improved.

The invention provides a chip logic function verification method, computer equipment, a program product and a medium. The chip logic function verification method comprises the following steps: obtaining a division scheme of a back-end design for each sub-module of a chip, so that the chip is re-divided into a plurality of to-be-verified modules; obtaining an RTL design scheme corresponding to the to-be-verified module; keeping the port of the to-be-verified module unchanged, and obtaining a gate-level netlist corresponding to the RTL design scheme; physical implementation of the to-be-verified module is carried out through the gate-level netlist and an EDA tool, and a design netlist after physical implementation is obtained; according to the design netlist, obtaining the time sequence information of each to-be-verified module after the time sequence convergence and the first time delay from the port of each to-be-verified module to the target register, and respectively subtracting the first time delay from the preset time delay to mark the port of each to-be-verified module so as to perform logic function verification with the time sequence information on the to-be-verified module. According to the scheme, optimization of manpower and calculator resources in the whole design process can be achieved, and the efficiency of chip logic function verification is improved.

The invention relates to the technical field of computer aided design, in particular to a coal mine roadway support parameter processing system and method based on the Internet of Things, and the system comprises a data collection and integration module which receives real-time environment information from an Internet of Things terminal, obtains roadway excavation contour data, front geological forecast data and field equipment state information, and sends the data to a data processing module; and generating a roadway model associated with the environment information. According to the method, the real-time monitoring data of the Internet of Things and the roadway support design process are fused, a dynamic closed-loop optimization mechanism is constructed in support parameter processing, and the reliability and adaptability of the support system are improved. Roadway excavation outline, geological forecast and equipment state data are collected in real time and directly embedded into the three-dimensional roadway model, so that support design basic parameters get rid of limitation of traditional static geological hypothesis, and the support strength can be corrected in advance according to the deformation trend of surrounding rock in front.

The invention discloses a turbine part modular design method, device and equipment combined with machine learning and a storage medium. Comprising the following steps: constructing an agent by utilizing a large language model and an expert knowledge base, and carrying out turbine demand capture and one-dimensional parameter design; performing quick generation and simulation of a two-dimensional blade profile by using an agent model based on a full-connection neural network and an auto-encoder; whether to enter a three-dimensional stage or return optimization is determined through performance judgment; and carrying out rapid generation of a three-dimensional blade profile and viscous flow field simulation by utilizing an attention mechanism-based proxy model, and carrying out performance judgment again to decide that the design is completed or optimization is continued. Through the modularized and intelligent design process, the large language model and various machine learning agent models are integrated, full-process automation and intellectualization of turbine component design are achieved, the design period is remarkably shortened, dependence on artificial experience is reduced, and the design quality is guaranteed.

The invention provides a design method of a Bump module at the rear end of a digital integrated circuit, and belongs to the field of power consumption analysis of the rear end of a digital chip of the integrated circuit. The invention provides a Bump module design process for solving the problems of inaccurate power consumption analysis and low analysis efficiency caused by insufficient power supply points during voltage drop analysis. The method comprises the steps of preparing digital back-end layout wiring data, selecting a metal layer according to project indexes to create a power strip line, setting a power strip mode, opening holes and connecting the metal layer, creating Bump specific data information, selecting a corresponding Bump to connect a power line and a ground wire, exporting specific position information of the Bump and marking the specific position information to an AP layer, and creating Physic Pin and exporting a def.gz file. The method is mainly applied to providing a power supply point for voltage drop analysis after digital back-end layout wiring and before voltage drop analysis, facilitates subsequent RC parasitic parameter extraction, further reduces dynamic voltage drop through the power supply point, is more convenient to operate, reduces the design cycle of a digital integrated circuit, and shortens the sign-off time.

The invention discloses a three-dimensional design method for a water turbine pipeline of a hydropower station. The method comprises the steps that a pipeline object database and a pipeline object parameterized three-dimensional model are constructed; according to the port information of the parameterized three-dimensional model of the pipeline object and the pipeline design flow direction, the connection logic of the pipeline object is designed; designing an arrangement method of the pipeline objects according to the connection logic of the pipeline objects, and completing preliminary design of a water machine pipeline network according to the arrangement method of the pipeline objects; and adjusting specification parameters and paths of the pipeline objects of the water machine pipeline network according to the connection logic of the pipeline objects and actual hydropower station building structure adjustment changes. According to the technical scheme, the accuracy and efficiency of water machine pipeline design are improved, and powerful technical support is provided for construction and maintenance of a hydropower station.

The invention relates to the technical field of integrated circuit design automation, and discloses an integrated circuit design whole-process collaborative verification and consistency guarantee method, which comprises the following steps of: constructing a unified design data model, and representing design data from function specifications to physical layout by using a multi-level attribute graph structure; establishing a design intention keeping mechanism, and tracking the transmission of the design intention in the hierarchical refinement process through intention semantic annotation, cross-level entity mapping and intention keeping degree evaluation; executing a hybrid verification strategy, combining formalized verification with dynamic simulation, and guiding verification resource allocation through a coverage rate feedback mechanism; performing constraint consistency check, performing constraint comparison at key nodes of the design process, and automatically identifying and positioning constraint conflicts; according to the method, the capture time of design errors can be brought forward by 80%, the number of design iterations is reduced by 40%, and the design quality and efficiency are remarkably improved.

The invention discloses an on-chip transformer reverse design method based on deep learning, relates to the technical field of artificial intelligence, and aims to solve the problems that in the prior art, the design of an on-chip transformer mostly adopts a forward design process, the efficiency is low and the like. The electrical parameters of the on-chip transformer to be designed serve as input, and a two-port S parameter sequence of the on-chip transformer to be designed is obtained based on output of the S parameter fitting neural network model; taking the two-port S parameter sequence of the to-be-designed on-chip transformer as input, and generating neural network model output based on geometric parameters to obtain geometric parameters of the to-be-designed on-chip transformer; and completing the design of the on-chip transformer according to the geometric parameters of the to-be-designed on-chip transformer in combination with a manufacturing process. According to the method, reverse design from electrical parameters to geometric parameters of the on-chip transformer is realized, the design efficiency is improved, and effective reference is provided for chip designers.

The embodiment of the invention provides a network-on-chip design method and device, electronic equipment and a readable storage medium, and the method comprises the steps: constructing a target behavior model based on a target design demand; generating a target code based on the target behavior model and a preset code library; under the condition that the target code does not meet the preset constraint target, the target behavior model is optimized, and the target code is updated based on the optimized target behavior model until the target code meets the preset constraint target; and generating an on-chip network code file based on the target code meeting the preset constraint target. Through the mode of performing constraint verification on the target code in the design process and optimizing and adjusting the target behavior model, the code optimization and adjustment range in the design process is narrowed, the code modification cost is reduced, and on the premise of ensuring that the target design requirement of the network-on-chip and the preset constraint target are verified to meet the expectation, the optimization and adjustment efficiency of the network-on-chip is improved. And the code generation efficiency of the network-on-chip is improved.

The invention relates to an aided design method, electronic equipment and a storage medium, and the method comprises the steps: responding to a received starting instruction of design software, and starting an aided design interface to obtain a preset operation; obtaining or generating a target template and a first design parameter of the target template according to a preset operation; receiving an adjustment operation for the first design parameters, and adjusting the first design parameters according to the adjustment operation to obtain second design parameters for generating the target model and a constraint relationship between the second design parameters; and sending the target template, the second design parameters and the constraint relationship among the second design parameters to design software, so that the design software generates a target model according to the target template, the second design parameters and the constraint relationship among the second design parameters. According to the technical scheme, the template is determined based on the aided design interface, the model is automatically generated according to the design parameters and the constraint relation corresponding to the template, the design process is simplified, the error rate is reduced, and the overall working efficiency is improved.

The invention relates to a satellite-borne electronic hardware design guarantee method and system. The method comprises the following steps: determining a satellite-borne hardware guarantee level (SHL) of satellite-borne electronic hardware; integrating a fault mode injection FM I into a design process of satellite-borne electronic hardware, and adjusting the execution depth of the FM I based on the SHL level; and providing a process cutting engine, and realizing adaptive process cutting based on a DO-254 standard according to the SHL level and in combination with the execution depth of the FM I. The system comprises an SHL evaluation module; an FM I management module; a space environment effect knowledge base; and a process cutting engine. According to the method, the problem that the DO-254 standard is insufficient in adaptability in the aerospace field is solved, the reliability design and verification efficiency of satellite-borne electronic hardware is remarkably improved, and the method is suitable for aerospace tasks such as various satellites and deep space probes.

The invention provides an automatic generation method supporting an MBSE system model and a design document. MBSE system model project information is read, and design document basic information is automatically generated; system design flow information of a methodological model constructed in an MBSE system model project is read, corresponding document chapters are generated according to flow design content C, the sequence of the document chapters is determined according to the design flow sequence A, and the outline level of each chapter in the design document is determined according to the hierarchical relation in the design flow hierarchy B; on the basis of the generated design document structure and the read design process corresponding model D, automatically filling each chapter with model content; and dynamically updating the content of the design document. The problems that in the prior art, a design document generation method based on templates and rules is poor in flexibility, and the document and the model are difficult to dynamically synchronize can be solved, and the consistency of the system model and the design document is guaranteed.

The invention provides a truss structure autonomous design system and method based on multiple agents. A layered multi-agent architecture is adopted, a general control agent is taken as a core, and a high-level design intention is analyzed and a plurality of downstream special agents are arranged for cooperative work; the whole design process realizes automatic closed loop through a graph-based workflow engine; the core innovation of the method is a hybrid intelligent optimization algorithm of LLM heuristic exploration and genetic algorithm accurate fine tuning, and the algorithm is driven by an original and quantifiable design quality scoring system to efficiently carry out analysis-diagnosis-optimization iteration so as to cooperatively improve the safety and economy of the design. The design time can be shortened from several hours to several minutes, about 7.0% of material consumption is saved on average, it is ensured that the scheme completely conforms to industry specifications, the design efficiency, economy and reliability are greatly improved, and meanwhile the use threshold of professional design software is remarkably reduced through natural language interaction.

The invention provides a method and a device for searching design point parameters of a gas compressor and electronic equipment. The method comprises the steps that for a first aerodynamic design scheme of the gas compressor, candidate inlet flow of the gas compressor is determined based on a specified gas compressor flow interval and / or a trained proxy model, and the proxy model is used for predicting the inlet flow of the gas compressor; the candidate inlet flow is the associated inlet flow when the first convergence working condition occurs in the design flow searching process of the first aerodynamic design scheme; the calculated pressure ratio of the gas compressor under the first convergence working condition is obtained; on the basis of the relation between the calculated pressure ratio and the target pressure ratio, the candidate inlet flow is adjusted till the relation between the calculated pressure ratio and the target pressure ratio meets a preset condition; based on the adjusted candidate inlet flow, the target inlet flow meeting the target pressure ratio under the first aerodynamic design scheme is determined through an interpolation algorithm. The risk of compressor design point search failure can be reduced, and the number of design point search times can be reduced.

The invention discloses a critical path optimization method and device and an optimization strategy determination method and device in logic synthesis. The optimization method comprises the following steps: identifying an initial key path from a comprehensive result corresponding to an RTL code, deleting a buffer tree on the path, and recording the path as a target key path; identifying abnormal path segments from all the target key paths, grouping all loads corresponding to the target signal lines on each abnormal path segment according to the obtained actual fan-out number on each abnormal path segment, copying the drivers of the target signal lines according to a copying strategy, and connecting the copied drivers with the load groups based on a preset connection strategy; and circularly executing optimization operation on all the abnormal path segments, and obtaining an optimized gate-level netlist after the path optimization operation on all the target key paths is completed. According to the method, the key path can be accurately identified, the comprehensive result is directly optimized, repeated modification and debugging on the RTL level are effectively avoided, and the efficiency of the whole design process is improved.

The invention belongs to the technical field of embedded software communication, and particularly relates to a method and device for automatically generating a radar interface control file, and the method comprises the steps: S1, forming a first editing interface for carrying out the content editing of an interface control file; s2, generating an index entry of the interface control file in the first editing interface according to the attribute of the interface control file input by the user; s3, generating a complete interface control file according to the content and the attribute of each element input by the user and the hierarchical relationship among the elements; s4, generating a word document or an xml document from the complete interface control file according to user appointment; and S5, in a second editing interface, generating the xml document into a header file program through editing according to a preset mapping specification. According to the method, the ICD design process is simplified, the ICD multiplexing degree is improved, the ICD specification degree is improved, and the ICD design accuracy is improved.

Embodiments of the present disclosure provide enhanced systems and methods for predicting optimal design flow parameters for optimized output targets for physical design synthesis of a given IC design. A Variational Autoencoder (VAE) along with a regression network are trained using a dataset comprising synthesis design construction flows from historical IC designs to provide a training data representation of the dataset constrained to a latent space of the VAE. The system generates feature vectors based on the training data representation of the dataset and updates the feature vectors with initial design characteristics of the given IC design. The system iteratively performs an input gradient search of the updated feature vectors to optimize an objective function of the design targets to identify locally optimal design parameters. The system identifies globally optimal design flow parameters for optimized design targets based on locally optimal design parameters.

The invention discloses an agent security execution control method and system, and relates to the technical field of artificial intelligence, and the method comprises the following steps: receiving a natural language input of a user, analyzing a spoken language demand into a structured design intention expression through an intention analysis agent, and obtaining a structured design intention expression; the design intention representation at least comprises a target entity, an operation constraint and an acceptance condition; on the basis of the design intention representation, relevant context information is retrieved from design data and a rule base through a retrieval enhancement agent until the retrieval coverage degree and the key anchor point positioning confidence degree reach preset threshold values; by introducing multi-agent cooperation and a natural language driven normal form, a DFT design process is upgraded from tedious and error-prone manual script writing to an intention-driven automatic closed loop. The system can automatically analyze the spoken requirements of the user, intelligently retrieve the design context and generate an interpretable and rollback execution plan, so that engineers are liberated from underlying commands and primitive operations, and the design efficiency is remarkably improved.

The application provides a radio frequency device behavior model parameter extraction method based on transfer learning, extracts polynomial model coefficients through a neural network model, reduces the amount of data required for establishing the neural network model, improves the portability and optimization efficiency of the model, realizes seamless integration of the neural network model and EDA software, and accelerates the progress of the electronic design process; the neural network model uses a test model in an old working state as a starting point for a new working state, avoids re-extracting model coefficients, and saves test time and instrument cost.

An embodiment method of forming a layout plan of an integrated circuit (IC) device includes obtaining a placement of a plurality of digital circuit cells in a region of a layout plan; obtaining an initial placement of one or more thermal sensing resistor cells in a subset of a plurality of metallization layers and a subset of a plurality of via layers of the layout plan; obtaining a routing plan based on a clock tree synthesis and the initial placement of the one or more thermal sensing resistor cells; performing a thermal analysis based on the placement of the plurality of digital circuit cells and the routing plan to identify one or more areas of interest in the region of the layout plan; and obtaining a refined placement of the one or more thermal sensing resistor cells respectively over the one or more areas of interest.

The invention discloses an improved scheduling virtual oscillation control method based on a differential controller, and belongs to the technical field of network construction control, and the method comprises the following steps: S1, obtaining LC filter inductive current and grid-connected point voltage data in a current system; s2, by adding an inertia link containing a differential controller into an active loop, virtual inertia is introduced into virtual oscillation control, and system frequency response is optimized; s3, establishing a complete parameter design process through an active power-frequency loop of virtual oscillation control and virtual synchronous machine control which are equivalently improved; and S4, based on the step S2, the voltage vector output by the virtual oscillation circuit is subjected to voltage and current double-closed-loop control and is compared with the direct current side voltage, and a duty ratio signal required by SPWM is output. According to the improved scheduling virtual oscillation control method based on the differential controller, additional hardware burden does not need to be added, parameter design is simple, good engineering practicability is achieved, and the frequency response capability of the system is remarkably improved.

When designing a circuit to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. At early stages of a circuit design (e.g., synthesis or placement), a designer can have limited information to rely on in order to determine whether the final circuit or some design variation thereof will meet the constraints without needing to fully design the circuit. The methods described herein use a machine learning (ML) model to predict whether an entire circuit is likely to meet a constraint based on features of a partial circuit design at an early stage of the design flow. Additionally, the disclosed methods allow for ranking various circuit designs or design implementations to determine the best candidate to proceed with full design.

The present application relates to the field of industrial software, and provides a chemical process automatic generation method, system and medium. The chemical process automatic generation method comprises the following steps: receiving a natural language description about an industrial process, wherein the natural language description comprises design constraints of the industrial process; starting a multi-agent collaboration system, converting the natural language description into an intermediate representation of the design process through closed-loop interaction among the multi-agents, wherein the multi-agent collaboration system utilizes a semantic entropy index to monitor the logical determinacy of each generation node in the process of generating the design process and triggers a real-time correction mechanism according to the uncertainty quantification result; mapping the intermediate representation into executable instructions of a heterogeneous simulation engine through an adaptation interface to drive the heterogeneous simulation engine to perform physical simulation calculation; and asynchronously extracting the calculation result of the heterogeneous simulation engine to realize closed-loop verification of the design process.

The invention provides a ship power system visualization process development method and system, electronic equipment and a storage medium. The method comprises the following steps: carrying out assembly modularization on a universal design tool in the ship power field; the design tool after component modularization is applied to edit the design process in a visual form, and the design process is constructed; simulating the constructed design process, verifying the correctness of the design process, and storing the design process which is verified to be correct as a design process template; and calling the design process template to reuse the design process which is verified to be correct. According to the scheme provided by the invention, the visualization level and the self-definition capability of the design process of the ship power system can be improved, and the starting difficulty of a design process tool is reduced. The solidified design process is stored as the process template for reuse in the design process, so that the design efficiency is improved.