80 results about "Design flow" patented technology

The invention discloses a host equipment data transmission extension method based on an AXI bus. The host equipment data transmission extension method is characterized in that a protocol conversion module is added between an AXI bus and an FIFO interface bus of host equipment; the protocol conversion module comprises an MST_FIFO module and an MST_IF module; the MST_IF module receives a read-writeaddress, a read-write length and a control command from the AXI interface; the MST_FIFO comprises five independent FIFOs which respectively correspond to five independent channels of a write command,a write data, a write response, a read command and a read data of an AXI bus; and the five independent FIFOs receive or send the five independent channels to host equipment. According to the host equipment data transmission extension method, the protocol conversion of the AXI signal and the FIFO signal is realized through the protocol conversion module, so that the self-research module does not need to accord with the AXI protocol any more, and the design flow of the self-research module is simplified, and the independence of each channel of the AXI protocol and the characteristics of high performance, and high bandwidth and low delay of the protocol are maintained.

Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed. To predict stress-induced displacements, the method inputs said density characteristics data into a programmed model that predicts displacements as a function of density, and outputs the predicted shift data.

Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.

The invention relates to a method for establishing a CAE linear analysis sub-assembly connection relation. The method is characterized by comprising the following steps of: 1) dividing an assembly: according to a design process of the whole vehicle, dividing a linear analysis model into nine parts, namely a white vehicle body (1), an engine hood (2), left and right front doors (3), left and right rear doors (4), a secondary frame (5), a trunk lid (6), a front-end module (7), an instrument board cross beam (8) and seats (9); 2) defining node and unit sections of each assembly: according to the assemblies divided in the step 1), performing node and unit section definition on a numerical model of each assembly by utilizing ANSA preprocessing software; 3) defining a connection position node number of each assembly: establishing a rigid connection at a connection position in the numerical model of each assembly, and performing redefinition on a central node of the connection position according to a node section in a format; defining the format of a node number of a connection point as follows: first two digits of the minimum value of the section 1# of a part plus first two digits of the minimum value of the section 2# of the part plus node range; and 4) establishing a connection file. (/b)

The invention relates to a workflow generation method and device, computer equipment and a storage medium. The method comprises the steps of: displaying a workflow design interface which comprises a selection control of at least one atomic task; in response to the selection operation on the selection control of at least one atomic task, displaying task patterns of at least two atomic tasks; in response to a connection operation on the task patterns of the at least two atomic tasks, obtaining a superior-subordinate relationship between the at least two atomic tasks; obtaining task execution parameters of the at least two atomic tasks; generating a target workflow based on the superior-subordinate relationship between the at least two atomic tasks and the task execution parameters of the atleast two atomic tasks. According to the method, a user can design an automatically executed workflow by himself/herself through a visual design process, and does not need to develop the workflow bywriting program codes by developers, so that the code development time is saved, and the application efficiency of the workflow is improved.

A method for hierarchical specification and modeling of scheduling in system-level simulations. The invention addresses the specification aspect by introducing an explicit notion of a scheduler that must be designed as part of the system. A scheduler effectively represents a scheduling policy for an architectural resource. A scheduling policy governs how behaviors assigned to a resource, gain access and share the resource. The invention includes a general framework for modeling a scheduling policy, which includes a simple mechanism that covers many common cases. This framework is part of a Virtual Component Codesign (VCC) process, which is targeted at consumer embedded system design. Two orthogonal models, one of a scheduler and one of a schedulable, comprise the overall modeling of scheduling in the invention. The two models interact by sending messages to each other via a simple protocol. The protocol itself is implemented by a pair of abstract interfaces, which in turn are implemented in concrete schedulable and scheduler objects in the simulator.

The invention discloses an IP management system and an IP management method, and relates to an IP management system and an IP management method. The invention aims to solve the problems that the existing IP-level SoC design process is complicated and lengthy and the accuracy is reduced due to excessive repetitive work along with the increase of the system. The IP management system comprises a configuration management module, a grammar analysis module, a register analysis module, a model generation module, a text generation module, a global check module and an integration module. The content ofthe configuration file comprises source file of each soft IP and hard IP or the position information of the model files of each soft IP and each hard IP, the macro information of each soft IP and each hard IP, the path information of each soft IP and each hard IP, the SystemRDL file position information corresponding to each soft IP and each hard IP or the user-defined register information description file position information. The method is applied to the field of digital chip design and EDA tools thereof.

The invention relates to the field of product data management, and provides a product design process problem full-life-cycle management method and system. The method comprises the steps: obtaining technical parameters in customer demand information, and decomposing the technical parameters of a product into a node data set of product design; establishing a constraint rule set and rule priorities among the product technical parameters; establishing constraint relationship in the design process nodes and between the nodes; when an engineering change form is created in the PDM system, sending theengineering change form to an approval node, and sending the approval form generated after approval is passed and the engineering change form to an engineering change process node; and adjusting a subsequent design flow node module. According to the method, engineering changes and technical parameters can be changed, the association between the nodes is realized before the product design activityis started, and once the engineering change occurs, the repeated communication required by the data change generated by the engineering change is reduced, the full-life-cycle management of the automatic information change and the engineering change is realized, and the product collaborative design efficiency is further improved.

The invention discloses an intelligent process engine service system and method, the logic level of the system comprises an application layer, a service layer, an acquisition and data processing layer and a database, and the process management and design interface of the application layer provides a processing permission and operation type setting module for manual processing nodes in the process; and the flow engine of the service layer controls the execution of the flow by reading the settings. The system adopts a micro-service architecture, provides convenient and flexible configuration and deployment, and can be fused with an enterprise information system through a small amount of simple configuration modification, and a user can design a flow by completely operating on an interface without programming or code modification; a process design interface is simple and clear; the process storage efficiency is higher, and modification is more convenient.

The invention discloses a special graph avoiding method for optimizing manufacturability of an integrated circuit. The back-end process of the integrated circuit comprises five basic steps of design data input, layout planning, layout, clock tree synthesis and wiring, after the steps are completed, a generated integrated circuit layout is analyzed, a graph with the manufacturing success rate of achip manufacturer lower than a preset threshold value is found out, and it is determined that associated standard units cannot be adjacent in the specific placement direction according to the graph; and then, according to a layout graphic result extracted after the wiring of the back-end process step is completed, the formed unit limiting file is supplemented into a file list provided by a processmanufacturer in the init stage of inputting the design data, the design data is read in again, and then, the whole back-end design process is carried out again. According to the method, files related to process manufacturing provided by process manufacturers and EDA tool manufacturers do not need to be modified, and new file formats of the EDA tool manufacturers do not need to be supplemented.

The invention discloses a process engine implementation method and a device. The method comprises the following steps: acquiring a plurality of process nodes involved in executing a preset service; defining path parameters of the plurality of process nodes and an execution sequence and a parallel relationship of the plurality of process nodes according to a preset configuration rule; designing a flow chart according to the path parameters, the execution sequence and the parallel relationship, and storing and publishing the designed flow chart to a flow engine; and calling a preset process template by the business system according to the API interface data of the process engine, and transmitting preset parameters to the process engine to generate a process instance. The development period of the process engine can be shortened, the flexibility of the process engine is improved, and later maintenance after an error occurs is facilitated.

The invention discloses an integrated circuit layout design system and method, and the system comprises a control module which is at least used for defining and initiating a design demand; a parameter setting module used for automatically generating parameters according to the information provided by the control module; a calling module used for calling a function according to the generated parameters to obtain a preliminary design and docking with a simulation tool; and a verification module used for judging whether the preliminary design meets the requirement or not and whether the design is completed or not. It can be seen that engineers and tools in a traditional design process are decoupled, the software-defined automatic design process is achieved, automation of integrated circuit layout design is achieved through the modularized, functionalized and structured design architecture and process, the integrated circuit development and design period is shortened, and the design efficiency is improved.

The invention provides a file inspection method and device, and the method comprises the steps: obtaining a configuration file of an IC design flow after the IC design flow executes an electronic design automation (EDA) operation to obtain an output file, wherein the configuration file comprises a file inspection function identification corresponding to the inspection needing to be carried out bythe output file; generating a file checking script according to the configuration file and a file checking function corresponding to the file checking function identifier; and performing file inspection on the output file by utilizing the file inspection script and outputting a file inspection result. By adopting the method, the automation of file inspection is realized, and the efficiency of fileinspection is improved.

The invention discloses a method for hierarchically identifying a circuit gate based on a workload, and belongs to the field of high reliability of high-performance processors. The method comprises: obtaining a workload signal, and, in a signal probability extracting stage, reading a circuit net list and design constraints, obtaining path delay of a circuit, and obtaining a potential critical path. The method comprises the signal probability extracting stage, a parameter analysis and calculation stage and a hierarchical identification gate determination stage. The parameter analysis and calculation stage is used for calculating the maximum critical path delay which can be borne by the circuit path and is obtained by aging delay degradation under the effect of the NBTI; and the hierarchicalidentification gate determination stage, which is used for determining a gate with relatively high aging sensitivity in the critical path, and proposing a new weight calculation method, and sorting the determined circuit gates according to the weights so as to perform hierarchical batch processing on the gate circuit. The method can be integrated in the ASIC design process, the aging critical path and the aging critical door can be effectively identified, the complexity of replacing the door in the critical path in a traditional method is reduced, and the working efficiency is improved.

The invention discloses a large-capacity medium-voltage high-frequency transformer design method. The method comprises the steps of transformer design requirement input, material parameter and iteration step length determination, iterative calculation, Pareto plane drawing of calculation results, result optimization, finite element verification of optimization results and result output. According to the method, the design process is fully numeralized, the model precision is ensured, the design time consumption is greatly reduced, traversal calculation of a full design space can be realized, and finally, rapid optimization is realized by combining a multi-objective optimization genetic algorithm. The method provided by the invention greatly simplifies the design process of the transformer, and is verified by a specific embodiment.

The invention discloses an existing building reconstruction digital design method based on full life cycle carbon emission calculation, and the method takes a digital tool as a carrier, i.e., building information model software and a secondary development plug-in thereof as tools to carry out existing building reconstruction design. According to the method, the reconstruction scheme is evaluated on the basis of the carbon emission index of the whole life cycle of the building, the carbon emission calculation method is embedded in the design process, and the existing building reconstruction scheme with the carbon emission index reaching the standard is finally obtained through repeated iteration, so that the double control of building energy conservation and emission reduction is realized, the digitization level of building reconstruction design is comprehensively improved, and the construction efficiency is improved. The design process is optimized, the design quality is improved, the living environment can be improved, and a high-quality green building can be built.

The invention provides an optimization design method of a siphon rectifier based on ISIGHT software. Firstly, an internal flow channel model of the siphon rectifier is established and an optimizationdesign variable of the internal flow channel is determined. Then, the optimization design objective function of the internal flow channel is determined, and the constraint conditions of the internal flow channel model are determined. Finally, based on ISIGHT software, the optimization design flow of inner flow channel is designed. The optimization module integrated in ISIGHT software is used to solve the objective function iteratively, and the design parameters that make the inner flow channel performance of siphon rectifier optimal are obtained. The invention can accurately obtain the internal flow channel structure design scheme with the best performance, and has great practical value for improving the performance and efficiency of the siphon rectifier.

The invention provides a netlist ECO method and device, equipment and a readable storage medium. The method comprises the following steps: carrying out the function modification of an original behavior-level code set according to a modification demand, modifying an original netlist set according to a first ECO script, obtaining a modified behavior-level code set and a modified netlist set, extracting a modification layer code and a modification layer netlist, and performing modification layer logic equivalence verification according to the obtained target modification module behavior-level code and the target modification module gate-level netlist; and if the modification layer logic equivalence verification result is consistent, sending the first ECO script to the IC back end for operation. In the debugging stage, only the codes of the modified part and the netlist need to be compared, logic equivalence verification is carried out, due to the fact that the data size of the local code module is small, debugging debugging can be rapidly completed, the ECO script debugging efficiency is improved, and the ECO script debugging time and the whole IC design process time are shortened.

The invention discloses a BIM-based fabricated exterior wall design method and system. The BIM-based fabricated exterior wall design method comprises the following steps: prefabricating a functional color block according to the parameter structure of an exterior wall component and the parameter structure of a mold, and prefabricating an instruction book according to the functional color block in an exterior wall tool box; sequentially calling functional color blocks according to a CAD drawing and an instruction book provided by a designer to input positioning and size information of the external wall component; importing the outer wall tool box with the positioning and size information of the outer wall component input into a BIM modeling platform, calling a matched component node in the outer wall tool box, generating an outer wall component model, and generating a BOM original table at the same time; and calling the matched mold form nodes in the outer wall tool box on the basis of the outer wall component model, and generating the outer wall component mold. The external wall component model and the external wall component mold which meet user requirements and the statistical BOMtable can be quickly and efficiently created, so that the design period is shortened, and the design process is simplified.

The invention discloses a dynamic layout changing method. The method comprises the following steps: creating standard unit pin access and a corresponding rectangle; sorting the standard units, findingout a pin access rectangle of each standard unit, and checking a design rule to obtain a state violating the design rule; and constructing a directed weighted graph according to the state of violating the design rule, performing overturning processing on the standard unit, and finishing pin wiring of the standard unit. According to the dynamic layout changing method, the electronic equipment andthe computer readable storage medium, early-stage repair can be carried out on the faulty standard unit layout, so that standard unit pins can be smoothly wired and connected, and the design process is accelerated.

The invention discloses a BIM-based fabricated PCF board design method and system. The BIM-based fabricated PCF board design method comprises the following steps of prefabricating a PFC board toolboxaccording to a parameter structure of a PCF board and a parameter structure of a mold; sequentially inputting all positioning and size information of the PCF board into a PFC board tool box accordingto a preliminary drawing provided by a designer; selecting matched component nodes in a PFC board toolbox according to the selected component types, generating component models item by item, and meanwhile generating a BOM original table; and on the basis of the component model, selecting corresponding mold form nodes on all sides from the PFC board tool box according to the component requirements,and integrally generating the mold model. According to the BIM-based fabricated PCF board design method, real parametric modeling, associated mold design and BOM automatic statistics are carried out,and a component model, a mold model and a statistical BOM table which meet user requirements can be quickly and efficiently created, and the effectiveness, standardization and reusability of the prefabricated PCF board are ensured, so that the design period is shortened, and the design process is simplified.