75 results about "Design flow" patented technology

The invention discloses a turbine part modular design method, device and equipment combined with machine learning and a storage medium. Comprising the following steps: constructing an agent by utilizing a large language model and an expert knowledge base, and carrying out turbine demand capture and one-dimensional parameter design; performing quick generation and simulation of a two-dimensional blade profile by using an agent model based on a full-connection neural network and an auto-encoder; whether to enter a three-dimensional stage or return optimization is determined through performance judgment; and carrying out rapid generation of a three-dimensional blade profile and viscous flow field simulation by utilizing an attention mechanism-based proxy model, and carrying out performance judgment again to decide that the design is completed or optimization is continued. Through the modularized and intelligent design process, the large language model and various machine learning agent models are integrated, full-process automation and intellectualization of turbine component design are achieved, the design period is remarkably shortened, dependence on artificial experience is reduced, and the design quality is guaranteed.

The invention relates to the technical field of integrated circuit design automation, and discloses an integrated circuit design whole-process collaborative verification and consistency guarantee method, which comprises the following steps of: constructing a unified design data model, and representing design data from function specifications to physical layout by using a multi-level attribute graph structure; establishing a design intention keeping mechanism, and tracking the transmission of the design intention in the hierarchical refinement process through intention semantic annotation, cross-level entity mapping and intention keeping degree evaluation; executing a hybrid verification strategy, combining formalized verification with dynamic simulation, and guiding verification resource allocation through a coverage rate feedback mechanism; performing constraint consistency check, performing constraint comparison at key nodes of the design process, and automatically identifying and positioning constraint conflicts; according to the method, the capture time of design errors can be brought forward by 80%, the number of design iterations is reduced by 40%, and the design quality and efficiency are remarkably improved.

The invention relates to a satellite-borne electronic hardware design guarantee method and system. The method comprises the following steps: determining a satellite-borne hardware guarantee level (SHL) of satellite-borne electronic hardware; integrating a fault mode injection FM I into a design process of satellite-borne electronic hardware, and adjusting the execution depth of the FM I based on the SHL level; and providing a process cutting engine, and realizing adaptive process cutting based on a DO-254 standard according to the SHL level and in combination with the execution depth of the FM I. The system comprises an SHL evaluation module; an FM I management module; a space environment effect knowledge base; and a process cutting engine. According to the method, the problem that the DO-254 standard is insufficient in adaptability in the aerospace field is solved, the reliability design and verification efficiency of satellite-borne electronic hardware is remarkably improved, and the method is suitable for aerospace tasks such as various satellites and deep space probes.

The invention provides a truss structure autonomous design system and method based on multiple agents. A layered multi-agent architecture is adopted, a general control agent is taken as a core, and a high-level design intention is analyzed and a plurality of downstream special agents are arranged for cooperative work; the whole design process realizes automatic closed loop through a graph-based workflow engine; the core innovation of the method is a hybrid intelligent optimization algorithm of LLM heuristic exploration and genetic algorithm accurate fine tuning, and the algorithm is driven by an original and quantifiable design quality scoring system to efficiently carry out analysis-diagnosis-optimization iteration so as to cooperatively improve the safety and economy of the design. The design time can be shortened from several hours to several minutes, about 7.0% of material consumption is saved on average, it is ensured that the scheme completely conforms to industry specifications, the design efficiency, economy and reliability are greatly improved, and meanwhile the use threshold of professional design software is remarkably reduced through natural language interaction.

Embodiments of the present disclosure provide enhanced systems and methods for predicting optimal design flow parameters for optimized output targets for physical design synthesis of a given IC design. A Variational Autoencoder (VAE) along with a regression network are trained using a dataset comprising synthesis design construction flows from historical IC designs to provide a training data representation of the dataset constrained to a latent space of the VAE. The system generates feature vectors based on the training data representation of the dataset and updates the feature vectors with initial design characteristics of the given IC design. The system iteratively performs an input gradient search of the updated feature vectors to optimize an objective function of the design targets to identify locally optimal design parameters. The system identifies globally optimal design flow parameters for optimized design targets based on locally optimal design parameters.

The invention discloses an agent security execution control method and system, and relates to the technical field of artificial intelligence, and the method comprises the following steps: receiving a natural language input of a user, analyzing a spoken language demand into a structured design intention expression through an intention analysis agent, and obtaining a structured design intention expression; the design intention representation at least comprises a target entity, an operation constraint and an acceptance condition; on the basis of the design intention representation, relevant context information is retrieved from design data and a rule base through a retrieval enhancement agent until the retrieval coverage degree and the key anchor point positioning confidence degree reach preset threshold values; by introducing multi-agent cooperation and a natural language driven normal form, a DFT design process is upgraded from tedious and error-prone manual script writing to an intention-driven automatic closed loop. The system can automatically analyze the spoken requirements of the user, intelligently retrieve the design context and generate an interpretable and rollback execution plan, so that engineers are liberated from underlying commands and primitive operations, and the design efficiency is remarkably improved.

The application provides a radio frequency device behavior model parameter extraction method based on transfer learning, extracts polynomial model coefficients through a neural network model, reduces the amount of data required for establishing the neural network model, improves the portability and optimization efficiency of the model, realizes seamless integration of the neural network model and EDA software, and accelerates the progress of the electronic design process; the neural network model uses a test model in an old working state as a starting point for a new working state, avoids re-extracting model coefficients, and saves test time and instrument cost.

An embodiment method of forming a layout plan of an integrated circuit (IC) device includes obtaining a placement of a plurality of digital circuit cells in a region of a layout plan; obtaining an initial placement of one or more thermal sensing resistor cells in a subset of a plurality of metallization layers and a subset of a plurality of via layers of the layout plan; obtaining a routing plan based on a clock tree synthesis and the initial placement of the one or more thermal sensing resistor cells; performing a thermal analysis based on the placement of the plurality of digital circuit cells and the routing plan to identify one or more areas of interest in the region of the layout plan; and obtaining a refined placement of the one or more thermal sensing resistor cells respectively over the one or more areas of interest.

When designing a circuit to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. At early stages of a circuit design (e.g., synthesis or placement), a designer can have limited information to rely on in order to determine whether the final circuit or some design variation thereof will meet the constraints without needing to fully design the circuit. The methods described herein use a machine learning (ML) model to predict whether an entire circuit is likely to meet a constraint based on features of a partial circuit design at an early stage of the design flow. Additionally, the disclosed methods allow for ranking various circuit designs or design implementations to determine the best candidate to proceed with full design.

The present application relates to the field of industrial software, and provides a chemical process automatic generation method, system and medium. The chemical process automatic generation method comprises the following steps: receiving a natural language description about an industrial process, wherein the natural language description comprises design constraints of the industrial process; starting a multi-agent collaboration system, converting the natural language description into an intermediate representation of the design process through closed-loop interaction among the multi-agents, wherein the multi-agent collaboration system utilizes a semantic entropy index to monitor the logical determinacy of each generation node in the process of generating the design process and triggers a real-time correction mechanism according to the uncertainty quantification result; mapping the intermediate representation into executable instructions of a heterogeneous simulation engine through an adaptation interface to drive the heterogeneous simulation engine to perform physical simulation calculation; and asynchronously extracting the calculation result of the heterogeneous simulation engine to realize closed-loop verification of the design process.

Some embodiments of the invention provide an Al-enabled method for integrated circuit (IC) architecture discovery, circuit topology and parameter optimization. The method of some embodiments explores the high dimensional design space beyond human intuition and extracting circuit features, configurations and designs unidentifiable to human experts in a variety of tasks. The method of some embodiments is used for RFIC architecture discovery, circuit topology and parameter optimization. For instance, the method of some embodiments provides an automated design flow for RFICs (e.g., RF or mmWave IC) that allows: (1) architecture selection, (2) circuit topology optimization, (3) parameter optimization, and (4) inverse design EM synthesis in a non-intuitive design space. In some embodiments, the method automates the synthesis of high-performance power amplifier (PA) circuits for transmitter systems, leveraging a combination of reinforcement learning (RL) and inverse design to optimize respectively active and passive components in the design. Some embodiments of the invention provide an Al-enabled method for integrated circuit (IC) architecture discovery, circuit topology and parameter optimization. The method of some embodiments explores the high dimensional design space beyond human intuition and extracting circuit features, configurations and designs unidentifiable to human experts in a variety of tasks. The method of some embodiments is used for RFIC architecture discovery, circuit topology and parameter optimization. For instance, the method of some embodiments provides an automated design flow for RFICs (e.g., RF or mmWave IC) that allows: (1) architecture selection, (2) circuit topology optimization, (3) parameter optimization, and (4) inverse design EM synthesis in a non-intuitive design space. In some embodiments, the method automates the synthesis of high-performance power amplifier (PA) circuits for transmitter systems, leveraging a combination of reinforcement learning (RL) and inverse design to optimize respectively active and passive components in the design.

The invention relates to a method and a device for determining optimization parameters of a magnetic element, electronic equipment and a medium. The method comprises the steps of performing parameter adjustment on a preset multi-target optimization model based on target working condition parameters of a to-be-optimized element, and solving the adjusted multi-target optimization model by using a preset genetic algorithm to obtain a Pareto optimal solution set; determining a target optimization parameter from the Pareto optimal solution set, constructing a performance analysis model of the to-be-optimized element based on the target optimization parameter, and simulating the performance analysis model to obtain a performance evaluation result; and in response to the condition that the matching degree of the performance evaluation result and the target working condition parameter meets a preset condition, judging that the target optimization parameter is an effective optimization parameter set of the to-be-optimized element. Therefore, by constructing a full-automatic and model-driven design process from target input to parameter output, the problems that the design of the high-frequency magnetic element depends on artificial experience, the design period is long and the performance is difficult to be globally optimal are solved.

Method and system are provided for performing physical-aware logic synthesis. A synthesis environment receives an RTL design, associated design constraints, and one or more design flow and physical design parameter settings. The RTL design is synthesized into a gate-level netlist while incorporating physical design considerations. A scoring result is computed from a logic synthesis result including the synthesized gate-level netlist to provide a quantitative measure of design quality. In certain aspects, the scoring result includes a scattering metric that evaluates placement density of standard cell instances, rankings across multiple modules, PPA results, and runtime prediction estimates. In further aspects, the design parameters are iteratively adjusted using artificial intelligence, reinforcement learning, or machine learning agents to optimize design quality. The invention enables improved integration of logical and physical design stages at advanced semiconductor process nodes.

The invention discloses a process control method and device for rear-end design of a digital chip and EDA tool software, and the method comprises the steps: firstly, carrying out RC automatic calibration on a pre-wiring database according to a design database, a reference database, a reference parasitic parameter information file and / or a preset time sequence calibration target, and then obtaining a parameter configuration file, the parameter configuration file comprises calibration configuration parameters for parasitic parameter extraction and / or time sequence values; and then loading the parameter configuration file in a logic synthesis stage, a layout stage, a clock tree synthesis stage, a wiring stage and / or an ECO stage of physical perception in a digital chip back-end design for RC extraction. According to the calibration configuration parameters, RC extraction or a time sequence value of a certain stage is used as a reference value to guide an RC engine of another stage, and then an optimized RC estimation model is used for iterative design again, so that a calibrated RC estimation or extraction model can be applied in different stages, the RC estimation and extraction precision is improved, and the design process efficiency is further improved.

The invention relates to the technical field of airborne system design, and discloses an airborne system digital forward design method, device, equipment and medium, a design process from demand analysis, architecture design, architecture tradeoff to simulation verification is established, integration and optimization of the airborne system design process are effectively realized, machine learning and multidisciplinary design optimization are combined, and the design efficiency is improved. According to the method, knowledge in multiple fields such as machinery, electronics and software is fused, design rules are mined from historical design cases through deep learning, a multi-target tradeoff analysis model is established, automatic generation and optimization of an architecture scheme are achieved, dependence on artificial experience is remarkably reduced, airborne system design efficiency is improved, design change cost is reduced, and the method is suitable for large-scale popularization and application. And the reliability of the airborne system is improved.

A method includes generating a plurality of intermediate designs for a chip by executing a first sub-step based on a first plurality of inputs, adding at least one intermediate design of the plurality of intermediate designs to a second plurality of inputs, generating a plurality of final designs by executing a second sub-step of the step of the design flow based on the second plurality of inputs, and selecting using a machine learning model a final design from the plurality of final designs. The first sub-step is a sub-step of a step of a design flow and the first plurality of inputs corresponds to input parameters associated with the first sub-step.

The application discloses a kind of electronic factory warm water system hydraulic balance rapid debugging method, first according to design drawing build simulation model including pressure boundary, main supply return water pipe, branch pipe, balance valve and equivalent resistance loss element, balance valve is adjusted to intermediate ring number, corresponding resistance coefficient is input to simulation model, then each branch balance valve is adjusted to intermediate ring number, the pressure drop, flow and main supply return water pressure of each branch balance valve under current working condition are measured, and input simulation model calculates the resistance coefficient that each branch equivalent resistance loss element needs to be set, combined with design flow, the most unfavorable branch balance valve opening degree is set to 1, the resistance coefficient and ring number of other branch balance valve adjustment are calculated, and balance valve is actually adjusted to corresponding ring number and locked, adjust pump speed to make total flow standard, realize hydraulic balance.The application combines simulation and field test, all balance valves are considered as a whole, compared with traditional manual debugging and hydraulic calculation method, the setting ring number of all balance valves can be given at one time, with high accuracy and short debugging time.

The invention provides a parameterized three-dimensional curve geometric feature generation method and device and a computer storage medium. According to the method, the analytic function of the target three-dimensional curve is automatically generated based on the discrete point set, and a plurality of nodes are uniformly distributed along the arc length direction of the curve, so that the problems of insufficient precision and non-uniform node distribution in a traditional modeling method are solved. The method not only improves the accuracy of axis modeling, but also enables the distribution of the equally-divided nodes to accurately adapt to the requirements of mechanical simulation calculation, and effectively supports subsequent engineering design and analysis. Through automatic calculation and optimization, manual intervention and error accumulation are remarkably reduced, the reliability and efficiency of the whole design process are improved, and the method is particularly suitable for the high-precision modeling requirement of a complex structure.

The application relates to the field of integrated circuit design and test technology, and discloses a scan chain port layout optimization method, device and electronic equipment. The core of the method comprises the following steps: an intelligent nearest matching step of a scan chain port and a scan chain, in which a nearest unassigned scan chain is searched as a candidate by sequentially selecting a scan chain port, and it is judged whether the scan chain is matched according to a preset distance constraint threshold, so that a first matching relationship is established; and a step of performing dynamic port rearrangement on the unassigned ports and scan chains that are not successfully matched to generate a second matching relationship. Through a two-stage adaptive matching mechanism, physical perception optimization of the scan chain connection relationship is realized, wiring congestion and interconnection delay are significantly reduced, and the robustness of the design process and the convergence of the test timing are improved.

The present disclosure relates to an engineering design process data quality evaluation method and device, and relates to the technical field of computers. The method comprises: obtaining target engineering design process data; structurally processing the target engineering design process data to determine a plurality of fields; determining a plurality of evaluation parameters according to the fields; determining evaluation information of the target engineering design process data according to the evaluation parameters; and outputting the evaluation information. The present disclosure can deeply mine and model the proofreading opinion data in the background, evaluate the quality of each process, and achieve more objective evaluation.

The invention discloses a wheel disc characteristic structure simulation part design method based on an additive manufacturing thought, which comprises the following steps of: firstly, establishing a parameterized model of a wheel disc, and acquiring stress field data of a wheel disc characteristic structure by adopting a finite element analysis means; secondly, based on stress field data of the wheel disc feature structure, an MATLAB program is written to solve a stress gradient space curve; and finally, determining the initial section size of the simulation piece based on the test condition of the testing machine, determining a size iterative formula based on the additive manufacturing idea, iteratively calculating the profile curve of the simulation piece according to the stress gradient space curve, and determining the configuration of the simulation piece in combination with the test condition of the testing machine. Compared with the prior art, the method has the advantages that stress gradient path selection, design of the initial configuration of the simulation part and size optimization of the initial configuration are not needed in the whole design process, standardization and standardization of design of the wheel disc feature structure simulation part are greatly improved, repetition of the design process is fundamentally avoided, the design period is shortened, and the design efficiency is improved.

The invention relates to the technical field of integrated circuit design and testing, and discloses a scan chain port layout optimization method and device and electronic equipment. The method comprises the following steps: sequentially selecting scan chain ports, searching an unallocated scan chain with the shortest physical distance as a candidate, and judging whether the unallocated scan chain is matched or not according to a preset distance constraint threshold value, so as to establish a first matching relationship; and executing dynamic port rearrangement on the ports which are not successfully matched and the scan chain to generate a second matching relationship. Through a two-stage adaptive matching mechanism, physical perception optimization of a scan chain connection relationship is realized, wiring congestion and interconnection delay are significantly reduced, and robustness of a design process and convergence of a test time sequence are improved.

The invention discloses a multi-terminal collaborative design practical training platform for nonferrous metal engineering design. The platform comprises a unified portal and client system, an application service system, a platform service system and a cloud computing and infrastructure system. Through clear division and cooperation of all the systems, the platform realizes a modern architecture which is high in cohesion, low in coupling, easy to expand and easy to maintain, can support large-scale and high-concurrency multi-terminal collaborative design practical training tasks, provides collaborative design and practical training management capability through a micro-service architecture, is an ecological system supported by cloud infrastructures, and has a good practical training effect. Finally, the core goals of design process collaboration, data management standardization, teaching management process and terminal access diversification are achieved, the requirements of modern engineering education and industry practice are perfectly met, the platform breaks through the design process through cloud data collaboration, the professional ability is enhanced through an integrated tool, and the design efficiency is improved. And full-link teaching management focuses on talent training.

The application discloses a separation flow control method and system based on a flow field feature and reinforcement learning, and relates to the technical field of flow control.The application combines pre-solution analysis with reinforcement learning to establish an integrated design process from flow sensitivity analysis to control law training.First, the most sensitive input structure of a flow system is extracted by using pre-solution analysis, and the optimal control position is quantitatively screened through effective gain, thereby avoiding the blindness of a traditional trial-and-error method.Second, a closed-loop control law is trained on the position by using reinforcement learning, so that the controller can be self-adaptively adjusted according to a real-time flow field state, and when the control effect is not up to the standard, the joint matching of the control position and the control law is realized through base flow reconstruction and iterative optimization, thereby the design efficiency and the control effect of the separation flow control system can be significantly improved, and the application is especially suitable for the control scheme design of strong non-steady and non-linear flow, such as transonic shock oscillation.

The invention provides a DFT process optimization method and device, electronic equipment and a storage medium, and belongs to the technical field of testability design. The DFT process optimization method comprises the steps of obtaining configuration data of a testability design DFT process of a preset data mode; before the DFT script used for the DFT process is generated, verifying the configuration data; and generating a DFT script based on the configuration data passing the verification. Thus, through verification of the configuration data, potential errors are positioned instantly, and data defects are intercepted before script generation.

The application provides a heat dissipation structure design method of an intelligent processor, comprising the following steps: a model reconstruction step, combining a design process of a structure design software and a thermal simulation software, reconstructing models according to modeling results of the two design processes, and obtaining temperature results of the two design processes; an error calculation step, the thermal simulation software calculating error parameters of the two design processes according to the temperature results of the two design processes; and an equivalent transformation step, the structure design software performing equivalent transformation design according to the error parameters. The application also provides a heat dissipation structure design device of an intelligent processor, a storage medium and an electronic device. Therefore, the application fully utilizes the advantages of the two heat dissipation structure design methods, simplifies the process, reduces the design cost, and improves the design efficiency.

1. The name of the design product: electronic system development management platform graphical user interface for electronic equipment. 2. The use of the design product: for electronic equipment. 3. The design points of the design product: the graphical user interface displayed on the display screen panel. 4. The picture or photo that best indicates the design points: front view. 5. The use of the graphical user interface: for chip and electronic system full-process development, through a unified interface to realize design process visualization, auxiliary optimization, real-time simulation analysis and RTL analysis, multi-tool collaborative operation, and graphical presentation of key indicators such as power consumption / timing. 6. The change state of the graphical user interface: the front view is the initial interface of the "electronic system development management platform", the top and left side of the front view are navigation menu bars, clicking the corresponding name button can expand or fold the submenu, the middle part of the front view is divided into four windows, each window can be dragged and adjusted in size up, down, left and right; right-clicking the "design run" button in the lower left window of the front view, a drop-down menu is displayed in real time, as shown in interface change state figure 1; clicking the "move to one" button in interface change state figure 1, the window is updated to the upper left window, as shown in interface change state figure 2; clicking the zoom-in button of the upper right window of interface change state figure 2, the interface changes to interface change state figure 3.

The application discloses a RISC-V style 8-bit reduced instruction set customization method, comprising the following steps: S1, based on the function and demand of the target application scene, a target instruction set is selected from a RISC-V32I instruction set, the data bit width, PC width, memory space and register group size of the processor are selected; S2, according to the interruption and exception types supported by the instruction set, the processing flow of the interruption and exception is determined; S3, the encoding space is reduced and the register grouping is optimized through a register coding multiplexing strategy, and the customization of the register addressing mode of the instruction set is realized; S4, each instruction is classified according to the instruction format; S5, each instruction is coded based on the format of each instruction. The customization method has a simple and efficient process, is easy to implement and deploy, does not need to be designed from zero, significantly shortens the research and development cycle, can adapt to multiple scene demands, and realizes the miniaturization of the instruction set, minimization of hardware resources and efficient design process.

A method includes generating a plurality of intermediate designs for a chip by executing a first sub-step based on a first plurality of inputs, adding at least one intermediate design of the plurality of intermediate designs to a second plurality of inputs, generating a plurality of final designs by executing a second sub-step of the step of the design flow based on the second plurality of inputs, and selecting using a machine learning model a final design from the plurality of final designs. The first sub-step is a sub-step of a step of a design flow and the first plurality of inputs corresponds to input parameters associated with the first sub-step.

This invention discloses a modular design method, apparatus, device, and storage medium for turbine components that incorporates machine learning. It includes: constructing an intelligent agent using a large language model and expert knowledge base to capture turbine requirements and design one-dimensional parameters; rapidly generating and simulating two-dimensional airfoils using a proxy model based on a fully connected neural network and autoencoder; determining whether to proceed to the three-dimensional stage or return to optimization based on performance evaluation; and rapidly generating three-dimensional airfoils and viscous flow field simulation using a proxy model based on an attention mechanism, followed by another performance evaluation to determine whether the design is complete or continues optimization. This invention, through a modular and intelligent design process, integrates a large language model and multiple machine learning proxy models, achieving full automation and intelligence in turbine component design, significantly shortening the design cycle, reducing reliance on human experience, and ensuring design quality.