Host equipment data transmission extension method based on AXI bus

A technology of host equipment and extension method, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of AXI bus read and write response not realized, unable to realize high stability of AXI bus, etc., to improve design efficiency and reusability, improve Transmission efficiency and response efficiency, the effect of improving utilization

Inactive Publication Date: 2020-01-17
SHANDONG SINOCHIP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For the part of the read and write data channel, the read and write response of the AXI bus has not been realized, so the advantages of high stability of the AXI bus cannot be realized

Method used

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  • Host equipment data transmission extension method based on AXI bus
  • Host equipment data transmission extension method based on AXI bus
  • Host equipment data transmission extension method based on AXI bus

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Experimental program
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Embodiment 1

[0022] This embodiment discloses an AXI bus-based host device data transmission extension method, such as figure 1 As shown, the function of this method is to realize the protocol conversion between the AXI bus and the FIFO interface bus, including address, control, data, and response protocol conversion and transmission, the AXI bus is connected to the slave, and the FIFO interface bus is connected to the host device or self-developed module.

[0023] This data transmission extension method is realized through the protocol conversion module, such as figure 2As shown, the protocol conversion module is located between the AXI bus and the FIFO interface bus of the host device, including MST_IF and MST_FIFO modules. The MST_FIFO module contains 5 independent FIFOs, corresponding to AXI write address, write data, write response, read address, and read data Five separate channels, FIFO input wr_cmd_push, wr_cmd-addr&control corresponding to AXI write address, output wr_cmd-full, ...

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Abstract

The invention discloses a host equipment data transmission extension method based on an AXI bus. The host equipment data transmission extension method is characterized in that a protocol conversion module is added between an AXI bus and an FIFO interface bus of host equipment; the protocol conversion module comprises an MST_FIFO module and an MST_IF module; the MST_IF module receives a read-writeaddress, a read-write length and a control command from the AXI interface; the MST_FIFO comprises five independent FIFOs which respectively correspond to five independent channels of a write command,a write data, a write response, a read command and a read data of an AXI bus; and the five independent FIFOs receive or send the five independent channels to host equipment. According to the host equipment data transmission extension method, the protocol conversion of the AXI signal and the FIFO signal is realized through the protocol conversion module, so that the self-research module does not need to accord with the AXI protocol any more, and the design flow of the self-research module is simplified, and the independence of each channel of the AXI protocol and the characteristics of high performance, and high bandwidth and low delay of the protocol are maintained.

Description

technical field [0001] The invention relates to an AXI bus-based host device data transmission extension method, and belongs to the technical field of AXI bus data transmission. Background technique [0002] The AXI bus is a close cooperation between Xilinx and ARM to jointly define the AXI protocol specification for FPGA-based high-performance systems and designs. The AXI protocol is adopted on the new-generation FPGA chip. Therefore, when implementing the self-developed module on the FPGA chip, the module interface must meet the AXI protocol. However, because the AXI protocol needs to meet the characteristics of high performance and low latency, the bus signals are complex and numerous. And the handshake signal mechanism is not easy to implement. [0003] The existing AXI bus-based data transmission, when aiming at the continuous handling and transmission of large quantities of data, there are many channel signals in the transmission, and frequent data transmission operat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40
CPCG06F13/4018
Inventor 孙中琳刘尚刘大铕朱苏雁刘奇浩王运哲
Owner SHANDONG SINOCHIP SEMICON
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