52 results about "Leakage current reduction" patented technology

The invention relates to the technical field of MOS semiconductors, and discloses a variably doped planar gate silicon carbide VDMOS device and a preparation process thereof, the variably doped planar gate silicon carbide VDMOS device comprises a plurality of MOS cells which are parallel to each other, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell; lateral symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, and the section contours of the corresponding sides of the lateral symmetric P-layers on the two sides are in an arc shape. By arranging the lightly doped N layer in the middle of the N drift layer and introducing the arc-shaped laterally-symmetrical P-layers to the two sides, the electric field distribution of the device is optimized, the local electric field concentration is reduced, the breakdown voltage is remarkably improved, and the charge balance capability is enhanced and the leakage current is reduced through the contact between the laterally-symmetrical P-layers and the N substrate layer.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The invention is applicable to the field of photovoltaic technology, and provides a back contact cell, a cell assembly and a photovoltaic system, the back surface of the substrate comprises a plurality of first regions, the first regions are first doped regions or second doped regions, the first regions and the first edge of the substrate are arranged at intervals to form first spacer regions, and the second regions are second doped regions or second doped regions. In the direction far away from the first edge of the substrate, texture structures with different morphologies are arranged in the first spacer region, so that on one hand, the light trapping effect in the spacer region can be improved, and the light absorptivity can be increased; the texture structures with different morphologies can disperse electric field concentration at the edge of the PN junction, avoid local breakdown, reduce leakage current, change the geometric shape of the edge of the PN junction and optimize local electric field distribution so as to achieve the effect of enhancing PN isolation, and finally the photoelectric conversion efficiency of the cell and the reliability of the assembly are improved.

The invention relates to a motor outgoing line technology, and discloses a special material for a motor outgoing line. The polyimide composite material is prepared from the following components in percentage by weight: 50 to 70 percent of polyimide matrix material, 5 to 12 percent of nano-scale low-dielectric-constant filler, 10 to 20 percent of micron-scale reinforcing filler, 3 to 8 percent of conductive filler, 0.5 to 2 percent of interface regulating agent and 1 to 3 percent of processing aid. The invention also provides a preparation method of the special material for the motor outgoing line. The preparation method comprises the following steps: S1, carrying out surface modification on a nanoscale low-dielectric-constant filler and an interface regulating agent through solvent dispersion; by adopting the technical scheme of compounding the surface modified silicon dioxide nanoparticles and the polyimide matrix, the technical effects of reducing the dielectric constant and reducing the leakage current are achieved. By modifying the filler, the dispersity and interface bonding property of particles are improved, and the defects of high dielectric constant and large leakage current caused by interface polarization and uneven distribution of the filler in the prior art are overcome.

The invention relates to a totem pole bridgeless power factor correction module and device, a power supply and a power supply system, the power factor correction module is used for performing power factor correction on alternating current input by an alternating current power supply, and the power factor correction module comprises a first transistor, a second transistor, a third transistor, a fourth transistor and an inductor, a first adjusting assembly and a second adjusting assembly are connected to the third transistor and the fourth transistor in parallel respectively, at least one of the first adjusting assembly and the second adjusting assembly is a switch, and the switches in the first adjusting assembly and the second adjusting assembly are conducted before the transistors connected in parallel are switched on when the alternating current power supply crosses zero. According to the embodiment of the invention, the switches in the first adjusting assembly and the second adjusting assembly are configured to be switched on before the transistors connected in parallel when the AC power supply crosses zero, and the connection point of the third transistor and the fourth transistor can be slowly discharged, so that the common-mode switching speed is slowed down, the common-mode interference is reduced, and the leakage current peak is reduced.

The present invention relates to a low-cost low-voltage anti-fuse array, which includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistors of all anti-fuse memory cells have anti-fuse gates shared with other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit lines, and the anti-fuse memory cells in the same row are connected to different bit lines, while all anti-fuse memory cells are connected to the same selection line and are respectively connected to different word lines. The present invention utilizes a configuration method of sharing source contacts to achieve a stable source architecture and reduce the overall layout area. At the same time, the least control voltage types can be used to reduce leakage current.

A device includes a thinned semiconductor substrate having a first side and a second side opposite to the first side; and at least one radio frequency device at the first side, wherein the second side of the thinned semiconductor substrate is processed to reduce leakage currents or to improve a radio frequency linearity of the at least one radio frequency device through Bosch etching.

The invention provides a battery protection method, circuit and chip, the battery protection circuit comprises a battery protection unit and a trigger unit, and the battery protection unit is connected between a positive electrode and a negative electrode of a battery; the trigger unit is connected with the battery protection unit and used for triggering an enabling state when it is detected that the battery voltage drops to be smaller than a first voltage threshold value so as to control the battery voltage to drop to be smaller than a second voltage threshold value and enable the battery to enter an under-voltage protection mode. The sensitivity of the battery entering the under-voltage protection mode is improved through the trigger unit, the leakage current is reduced to the maximum extent, the shutdown power consumption is reduced, the shutdown storage time of the electronic equipment is prolonged, the safety risks such as swelling of the battery are avoided, and the circuit is simple in structure, easy and convenient to operate and wide in applicability.

The invention relates to the technical field of photoelectric elements, and discloses a laser element with a two-dimensional Moire superlattice layer. Comprising a substrate layer, an n-type coating layer, the two-dimensional Moire superlattice layer, a lower waveguide layer, a quantum well active region, an electron blocking layer, an upper waveguide layer, a p-type coating layer and a p-type contact layer from bottom to top in sequence. The two-dimensional Moire superlattice layer is introduced between the n-type coating layer and the lower waveguide layer, the limiting effect of current carriers can be effectively improved, leakage current is reduced, meanwhile, the superlattice layer has a unique energy band structure, light field distribution of a device is optimized, in addition, by optimizing the structural design and the doping process of the p-type region, the light field distribution of the device is optimized, and the light field distribution of the device is optimized. And the electrical performance of the device can be obviously improved.

The embodiment of the invention provides a preparation method of a ferroelectric field effect transistor. The preparation method comprises the following steps: depositing a plurality of layers of OMO structures on a source electrode metal layer; photoetching and punching on the multi-layer OMO structure to form a cylindrical hole; a ferroelectric HZO layer and a channel IGZO layer are deposited in the cylindrical hole; and opening a hole at the bottom of the cylindrical hole, and performing oxide deposition between the channel IGZO layers to form an oxide filling layer. According to the preparation method of the ferroelectric field effect transistor provided by the embodiment of the invention, through the macaroni structure, the contact area between the grid electrode and the storage unit is increased, the leakage current is effectively reduced, and the electrical performance of the ferroelectric field effect transistor can be improved. The embodiment of the invention further provides the ferroelectric field effect transistor.

A display apparatus capable of reducing a leakage current and effectively transmitting an electrical signal to a plurality of opposite electrodes includes a pixel definition layer including a first opening, a spacer including a second opening, wherein at least a portion of a body portion of the spacer is disposed in the first opening to cover a side surface of the pixel defining layer.

The LED ceiling lamp comprises a shell, a light source plate and an inductor or a wireless control module, a reflection cup is installed in the shell, the light source plate is installed in the reflection cup, and the inductor or the wireless control module is arranged on the light source plate; the LED lamp has the advantages that the reflection cup is arranged, and the light source plate is installed in the reflection cup, so that the creepage distance between the light source plate and the shell is increased, leakage current is reduced, the situation that the inductor or the wireless control module fails due to the leakage current is avoided, meanwhile, the light emitting efficiency is further improved due to the use of the reflection cup, and the use efficiency of the LED lamp beads on the light source plate is improved.

The invention discloses a high-heat-dissipation double-layer back barrier transistor and a preparation method and application thereof, and relates to the technical field of microelectronics. Comprising a substrate, and a multi-layer h-BN layer, a position control B diffusion double-layer back barrier layer, a channel layer, a barrier layer, a cap layer, a passivation layer and a metal gate layer which are sequentially laminated on the substrate, the multi-layer h-BN layer is a multi-layer h-BN layer in which high-energy aluminum ions are injected at fixed points; and the position control B diffusion double-layer back barrier layer comprises an AlN layer and a GaN layer which are sequentially deposited on the multiple h-BN layers. According to the invention, the fixed-point ion implantation technology is utilized to achieve the effect of controlling the B diffusion to assist the epitaxial barrier layer, a double-layer back barrier is further formed on the upper layer GaN and the lower layer AlN of the back barrier through a two-step B diffusion Gaussian distribution method, the problems of lattice mismatch and thermal mismatch between the upper layer and the lower layer are optimized due to the regulation and control of the B interface state in the back barrier, and the performance of the back barrier is improved. Meanwhile, the double-layer back potential barrier can effectively reduce leakage current, and the breakdown voltage of the transistor is improved.

This invention provides a trench-type MIM capacitor and its manufacturing method, belonging to the semiconductor field. The trench-type MIM capacitor includes a semiconductor substrate with multiple trenches within a first dielectric layer on the semiconductor substrate; a bottom electrode disposed along the bottom and sides of the multiple trenches and extending laterally along the upper surface of the first dielectric layer; an oxygen donor layer covering only the bottom electrode on the trench sides; and a top electrode disposed on the surface of the high-dielectric-constant dielectric layer and filling the trenches. The high-dielectric-constant dielectric layer isolates the bottom electrode and the top electrode. This invention reduces leakage current by providing an oxygen donor layer only on the bottom electrode layer on the trench sides, allowing the oxygen donor layer to supply oxygen to the bottom electrode layer and reducing the concentration of oxygen vacancies. The absence of an oxygen donor layer in the horizontal portion ensures that the capacitance dielectric constant k does not decrease.

A memory device for reducing leakage current is provided. The memory device includes: a functional circuit including a plurality of semiconductor devices; and a body bias generator that supplies a body bias voltage to the body terminals of the plurality of semiconductor devices. The functional circuit includes a first circuit, a second circuit, and first to fourth switches. The first switch is connected between the first circuit and a first node to which a body bias voltage is applied. The second switch is connected between the second circuit and the first node. The third switch is connected between the first circuit and a second node to which the supply voltage is applied. The fourth switch is connected between the second circuit and the second node. The switch is controlled by a control signal. The device threshold voltage is increased by the applied body bias voltage, thereby reducing leakage current.

A piezoelectric device that exhibits good piezoelectric characteristics, while reducing generation of leakage current paths, and a method of manufacturing the same, are provided. The piezoelectric device has a multilayer stack in which a first electrode, a piezoelectric layer, and a second electrode are stacked in this order on a substrate, wherein at least the first electrode is formed of an amorphous oxide conductor.

The invention provides a groove type MIM capacitor and a manufacturing method thereof, and belongs to the field of semiconductors. The groove type MIM capacitor comprises a semiconductor substrate, wherein a plurality of grooves are formed in a first dielectric layer on the semiconductor substrate; the bottom electrodes are arranged along the bottoms and the side surfaces of the plurality of grooves and transversely extend along the upper surface of the first dielectric layer; the oxygen donor layer only covers the bottom electrode on the side surface of the trench; and the top electrode is arranged on the surface of the high-dielectric-constant dielectric layer and fills the groove, and the high-dielectric-constant dielectric layer isolates the bottom electrode from the top electrode. The oxygen donor layer is only arranged on the bottom electrode layer on the side face of the groove, the oxygen donor layer can provide oxygen for the bottom electrode layer, the concentration of oxygen vacancies is reduced, and therefore leakage current is reduced. And no oxygen donor layer is arranged at the horizontal part, so that the capacitance dielectric constant k value cannot be reduced.

The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a bit line structure, a seed layer, a first spacer, a second spacer, a third spacer and an air gap. The substrate is provided with a groove, and the groove is provided with a sharp corner. The bit line structure is located on the substrate, wherein the groove surrounds the bit line structure. The seed layer is located on a sidewall of the bit line structure. A first spacer is on a sidewall of the seed layer and on a bottom surface of the recess. The second spacer fills the recess. The third spacer is located on the substrate and adjacent to the first spacer. The air gap is located between the first spacer and the third spacer. Wherein the bottom of the air gap exposes part of the top surface of the second spacer. The second spacer supports the first spacer at the bottom, so that collapse in the air gap forming process can be reduced, the air gap integrity is improved, and leakage current and stray capacitance faults are reduced.

A delay measuring circuit includes a control oscillation module with its input terminal connected to its output terminal, which sequentially generates a number of time delay signals with a cycle time T after receiving first enable control signal; a target oscillating module receives a second enabling signal delayed by a first preset threshold than the first enabling signal; after the first preset time T1 is disconnected from the ground terminal / power supply terminal, each stage of the target unit in the target oscillating module connects at the second preset time T2. The level of the target unit turns over at first preset time T1, and target unit maintains logic level for second preset time T2; T1+T2=T / 2, and N is an odd integer. So leakage current is reduced and mutual influence of the action current between the adjacent two-level target units are avoided, thus improving ring oscillator performance and reliability.

This invention discloses a high-heat-dissipation double-layer back barrier transistor, its fabrication method, and its applications, relating to the field of microelectronics technology. It includes a substrate, and multiple layers of h-BN layers, a site-controlled B-diffusion double-layer back barrier layer, a channel layer, a barrier layer, a cap layer, a passivation layer, and a metal gate layer sequentially stacked on the substrate. The multiple h-BN layers are multi-layer h-BN layers implanted with high-energy aluminum ions. The site-controlled B-diffusion double-layer back barrier layer includes AlN and GaN layers sequentially deposited on the multiple h-BN layers. This invention utilizes site-controlled ion implantation technology to achieve the effect of a site-controlled B-diffusion-assisted epitaxial barrier layer. Furthermore, a double-layer back barrier is formed between the upper GaN layer and the lower AlN layer using a two-step B-diffusion Gaussian distribution method. Due to the B interface state modulation within the back barrier, the lattice mismatch and thermal mismatch between the upper and lower layers are optimized, significantly improving heat dissipation. Simultaneously, the double-layer back barrier can effectively reduce leakage current and improve the transistor breakdown voltage.

The invention relates to a totem-pole bridgeless power factor correction device, a power supply and a power supply system, the totem-pole bridgeless power factor correction device comprises a power factor correction module and a control module, the control module is used for outputting a first switch control signal and a second switch control signal when an alternating current power supply crosses zero, the first switch control signal comprises a plurality of pulse signals with gradually increased pulse widths, and the second switch control signal comprises a plurality of pulse signals with gradually increased pulse widths; in the first time period, the pulse width of each pulse signal of the first switch control signal is broadened from being close to zero, and the increasing amplitude is smaller than a first preset pulse width; and in the second time period, the pulse width of each pulse signal of the first switch control signal is gradually increased to the full duty ratio, the increasing amplitude is greater than a second preset pulse width, the first preset pulse width is smaller than the second preset pulse width, the first switch control signal acts on the active tube, and the second switch control signal is used for disconnecting the follow current tube. According to the embodiment of the invention, the common-mode switching speed can be slowed down during the zero-crossing period of the alternating-current power supply, and the common-mode interference is reduced, so that the leakage current peak is reduced.

The invention provides a semiconductor device, a storage system and a preparation method of the semiconductor device, relates to the technical field of semiconductor chips, and aims to improve the control capability of a grid electrode on a channel and reduce the generation of leakage current. The semiconductor device comprises a substrate, fins arranged on the surface of the substrate, a shallow trench isolation layer and a grid electrode. Each fin comprises a first sub-part, a second sub-part and a third sub-part which are sequentially connected in the direction away from the substrate; the side surface of the second sub-part is recessed relative to the side surface of the third sub-part; the side surface is a surface extending in the length direction of the fin. The shallow trench isolation layer is arranged on the surface of the substrate and surrounds the first sub-part. The grid electrode is arranged on the side, away from the substrate, of the shallow groove isolation layer and arranged on the side face of the second sub-part, the side face of the third sub-part and the surface, away from the substrate, of the third sub-part. The semiconductor device has good grid control capability.

Embodiments provide a memory device capable of reducing leakage current. According to one embodiment, a memory device includes first wiring extending in a first direction and second wiring extending in a second direction. A memory cell is connected between the first wiring and the second wiring and includes a variable resistance memory element. A first drive circuit is provided to supply a voltage to the first wiring, and a second drive circuit is provided to supply a voltage to the second wiring. The first drive circuit applies a first voltage to a selected first wiring, and the second drive circuit applies a second voltage to a selected second wiring. A voltage between half of a sum of the first voltage and the second voltage and the second voltage is applied to an unselected first wiring, and a voltage between half of the sum of the first voltage and the second voltage and the first voltage is applied to an unselected second wiring.

The utility model discloses an adjustable nanoamp constant current source circuit and a test system, the adjustable nanoamp constant current source circuit comprises a precision reference source circuit, an operational amplifier feedback regulation circuit, a control circuit, an analog switch circuit and a junction field effect transistor, the analog switch circuit is respectively connected with the control circuit and the operational amplifier feedback regulation circuit, and the junction field effect transistor is connected with the operational amplifier feedback regulation circuit. And the operational amplifier feedback regulation circuit is also connected with the precise reference source circuit and the junction field effect transistor respectively. According to the utility model, the precise reference source circuit is adopted to provide a reference voltage source; the operational amplifier feedback regulation circuit performs voltage-current conversion on the reference voltage of the reference voltage source to generate a current source, and controls the junction field effect transistor to be conducted to output a constant current source; the control circuit is used for controlling the analog switch circuit to adjust the constant current source, the control circuit is used for controlling the analog switch circuit to achieve output adjustment of the constant current source, the junction field effect transistor is used for reducing leakage current, and therefore output precision of the nanoampere-level constant current source is improved, and high-precision measurement and testing are achieved.

The present disclosure relates to fluid warmers such as intravenous fluid warmers for medical applications that exhibit improved leakage current suppression or cancellation during fault conditions of an intravenous fluid delivery system.

Procedure (600) comprising the following: Providing (602) a substrate (720) having a first active region (702) and a second active region (704) adjacent to the first active region (702) at a boundary (711); Forming a first rib (710) within the first active region (702), a second rib (712) within the second active region (702), and a dummy rib (714) along the border (711); Deposition of a photoresist layer (715) and structuring of the photoresist layer to expose the dummy rib (714) while the first rib (710) and the second rib (712) remain covered by the structured photoresist layer (715); Performing a threshold voltage implantation (722) through the structured photoresist layer (715) into the dummy rib to provide an ion-implanted dummy rib (714A); and Forming a gate stack (716) over the first rib (710), the second rib (712) and the ion-implanted dummy rib (714A).

The invention discloses a pressure sensor chip and a manufacturing method thereof, and relates to the technical field of pressure sensors. A pressure sensor chip comprises an epitaxial layer, a sensing module and a shielding layer, and the epitaxial layer is of a first conductive type; the sensing module is arranged in the epitaxial layer, and the sensing module is of a second conduction type; the epitaxial layer and the sensing module form a first PN junction; the shielding layer is arranged on one side of the epitaxial layer and is in contact with the sensing module, the shielding layer is of the first conduction type, and the shielding layer and the sensing module form a second PN junction; wherein the epitaxial layer and the shielding layer wrap the sensing module so as to electrically isolate the sensing module from the surrounding area of the sensing module. According to the pressure sensor, leakage current can be reduced, so that the detection precision and the working stability of the pressure sensor are improved, nonlinear errors are prevented from being increased, and the requirements for high precision and high reliability in various application scenes are met.

The application belongs to the technical field of new energy materials and devices, and particularly relates to a perovskite solar cell and a preparation method thereof. The perovskite solar cell comprises a conductive glass layer, an electron transport layer, an interface modification layer, a perovskite light absorption layer, a hole transport layer and a metal electrode layer. The perovskite light absorption layer is doped with arginine of a certain concentration and is subjected to an annealing process. The interface modification layer is a sodium alginate film layer. The perovskite light absorption layer film shows stronger crystallinity and a smoother surface after being doped with arginine. In combination with the interface modification of the sodium alginate, the dangling bonds on the surface of the perovskite layer between the interface of the electron transport layer and the perovskite light absorption layer can be passivated, so as to reduce the binding of deep level defects to carriers, effectively reduce the contact between the electron transport layer and the hole transport layer, reduce the leakage current, improve the photoelectric conversion efficiency, and be beneficial to blocking the penetration of oxygen and reducing the oxidation of the perovskite material.

A radiation imaging device (90) includes a substrate (92) and a radiation-sensitive imaging region (96) in the substrate (92) including pixels (60). The radiation imaging device (90) includes a protective region (94) located at or adjacent to a cut edge (95) of the substrate (92), wherein the protective region (94) reduces leakage current from the cut edge (95) to the radiation-sensitive imaging region (96) when the radiation imaging device (90) is in use. The radiation-sensitive imaging region (96) is reverse electrically biased relative to the substrate (92). The radiation-sensitive imaging region (96) includes a portion (134) adjacent to the protective region (94) that is closest to the location where incident radiation impacts the radiation imaging device (90). The pixel (60) includes a first pixel electrode (146) located in a portion (134) in which a first longitudinal end (150) of the first pixel electrode (146) closest to the protective region (94) is at a first distance (154) from the protective region (94), the first distance reducing the amount of leakage current received by the first pixel electrode (146).