16 results about "Leakage current reduction" patented technology

A display apparatus capable of reducing a leakage current and effectively transmitting an electrical signal to a plurality of opposite electrodes includes a pixel definition layer including a first opening, a spacer including a second opening, wherein at least a portion of a body portion of the spacer is disposed in the first opening to cover a side surface of the pixel defining layer.

The LED ceiling lamp comprises a shell, a light source plate and an inductor or a wireless control module, a reflection cup is installed in the shell, the light source plate is installed in the reflection cup, and the inductor or the wireless control module is arranged on the light source plate; the LED lamp has the advantages that the reflection cup is arranged, and the light source plate is installed in the reflection cup, so that the creepage distance between the light source plate and the shell is increased, leakage current is reduced, the situation that the inductor or the wireless control module fails due to the leakage current is avoided, meanwhile, the light emitting efficiency is further improved due to the use of the reflection cup, and the use efficiency of the LED lamp beads on the light source plate is improved.

A piezoelectric device that exhibits good piezoelectric characteristics, while reducing generation of leakage current paths, and a method of manufacturing the same, are provided. The piezoelectric device has a multilayer stack in which a first electrode, a piezoelectric layer, and a second electrode are stacked in this order on a substrate, wherein at least the first electrode is formed of an amorphous oxide conductor.

The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a bit line structure, a seed layer, a first spacer, a second spacer, a third spacer and an air gap. The substrate is provided with a groove, and the groove is provided with a sharp corner. The bit line structure is located on the substrate, wherein the groove surrounds the bit line structure. The seed layer is located on a sidewall of the bit line structure. A first spacer is on a sidewall of the seed layer and on a bottom surface of the recess. The second spacer fills the recess. The third spacer is located on the substrate and adjacent to the first spacer. The air gap is located between the first spacer and the third spacer. Wherein the bottom of the air gap exposes part of the top surface of the second spacer. The second spacer supports the first spacer at the bottom, so that collapse in the air gap forming process can be reduced, the air gap integrity is improved, and leakage current and stray capacitance faults are reduced.

The invention relates to a totem-pole bridgeless power factor correction device, a power supply and a power supply system, the totem-pole bridgeless power factor correction device comprises a power factor correction module and a control module, the control module is used for outputting a first switch control signal and a second switch control signal when an alternating current power supply crosses zero, the first switch control signal comprises a plurality of pulse signals with gradually increased pulse widths, and the second switch control signal comprises a plurality of pulse signals with gradually increased pulse widths; in the first time period, the pulse width of each pulse signal of the first switch control signal is broadened from being close to zero, and the increasing amplitude is smaller than a first preset pulse width; and in the second time period, the pulse width of each pulse signal of the first switch control signal is gradually increased to the full duty ratio, the increasing amplitude is greater than a second preset pulse width, the first preset pulse width is smaller than the second preset pulse width, the first switch control signal acts on the active tube, and the second switch control signal is used for disconnecting the follow current tube. According to the embodiment of the invention, the common-mode switching speed can be slowed down during the zero-crossing period of the alternating-current power supply, and the common-mode interference is reduced, so that the leakage current peak is reduced.

Embodiments provide a memory device capable of reducing leakage current. According to one embodiment, a memory device includes first wiring extending in a first direction and second wiring extending in a second direction. A memory cell is connected between the first wiring and the second wiring and includes a variable resistance memory element. A first drive circuit is provided to supply a voltage to the first wiring, and a second drive circuit is provided to supply a voltage to the second wiring. The first drive circuit applies a first voltage to a selected first wiring, and the second drive circuit applies a second voltage to a selected second wiring. A voltage between half of a sum of the first voltage and the second voltage and the second voltage is applied to an unselected first wiring, and a voltage between half of the sum of the first voltage and the second voltage and the first voltage is applied to an unselected second wiring.

The present disclosure relates to fluid warmers such as intravenous fluid warmers for medical applications that exhibit improved leakage current suppression or cancellation during fault conditions of an intravenous fluid delivery system.

Procedure (600) comprising the following: Providing (602) a substrate (720) having a first active region (702) and a second active region (704) adjacent to the first active region (702) at a boundary (711); Forming a first rib (710) within the first active region (702), a second rib (712) within the second active region (702), and a dummy rib (714) along the border (711); Deposition of a photoresist layer (715) and structuring of the photoresist layer to expose the dummy rib (714) while the first rib (710) and the second rib (712) remain covered by the structured photoresist layer (715); Performing a threshold voltage implantation (722) through the structured photoresist layer (715) into the dummy rib to provide an ion-implanted dummy rib (714A); and Forming a gate stack (716) over the first rib (710), the second rib (712) and the ion-implanted dummy rib (714A).

A radiation imaging device (90) includes a substrate (92) and a radiation-sensitive imaging region (96) in the substrate (92) including pixels (60). The radiation imaging device (90) includes a protective region (94) located at or adjacent to a cut edge (95) of the substrate (92), wherein the protective region (94) reduces leakage current from the cut edge (95) to the radiation-sensitive imaging region (96) when the radiation imaging device (90) is in use. The radiation-sensitive imaging region (96) is reverse electrically biased relative to the substrate (92). The radiation-sensitive imaging region (96) includes a portion (134) adjacent to the protective region (94) that is closest to the location where incident radiation impacts the radiation imaging device (90). The pixel (60) includes a first pixel electrode (146) located in a portion (134) in which a first longitudinal end (150) of the first pixel electrode (146) closest to the protective region (94) is at a first distance (154) from the protective region (94), the first distance reducing the amount of leakage current received by the first pixel electrode (146).

The invention provides a carbon-based semiconductor device and a preparation method thereof. The carbon-based semiconductor device includes: a substrate; the channel layer is made of a carbon-based material; an oxide layer; a gate electrode; the side walls are formed on the two sides of the grid electrode, each side wall is in a bent shape comprising a first part and a second part, the first part extends in the first direction, the second part extends in the second direction, the first direction is the direction perpendicular to the surface of the substrate, and the second direction is the direction parallel to the surface of the substrate. The drain electrode is located on the outer side of the side wall on one side of the grid electrode, and the drain electrode and the grid electrode are separated through the side wall on one side; the source electrode is positioned on the outer side of the side wall on the other side of the grid electrode; the source electrode and the grid electrode are separated through the side wall on the other side. According to the carbon-based semiconductor device disclosed by the invention, the side wall can form a widened transverse isolation region at the bottom of the gate, so that the regulation and control capability on a channel is remarkably enhanced, a short channel effect is effectively inhibited, gate-source / drain parasitic capacitance is reduced, leakage current is reduced, and the like.

The invention relates to the field of semiconductor device preparation, and discloses a gate oxide layer growth method and a semiconductor device, and the method comprises the steps: providing a silicon substrate, and sequentially carrying out the first dry oxygen oxidation, the wet oxygen oxidation and the second dry oxygen oxidation of the silicon substrate, so as to form a gate oxide layer on the surface of the silicon substrate, after the wet oxygen oxidation and before the second dry oxygen oxidation, heat preservation annealing operation is executed, and the heat preservation annealing operation comprises the steps that under the condition that oxygen is not introduced, the environment temperature is increased to the intermediate temperature from the first temperature of the wet oxygen oxidation, and after the intermediate temperature is maintained for a specified duration, the temperature is increased to the second temperature of the second dry oxygen oxidation. According to the technical scheme provided by one or more embodiments of the invention, the yield can be improved, the DSBL failure number can be reduced, the leakage current LKG can be reduced, and the performance of the semiconductor device can be improved while the reliability of the device is ensured.

The invention relates to an SOI-based MIS p-GaN HEMT half-bridge integrated circuit and a preparation method thereof. The SOI-based MIS p-GaN HEMT half-bridge integrated circuit comprises an SOI substrate, an AlN layer, a GaN layer, an AlGaN layer, a p-GaN layer and a second insulating dielectric layer which are sequentially arranged from bottom to top. The SOI substrate comprises substrate silicon, a first insulating medium layer and top silicon; etching the p-GaN layer and the second insulating dielectric layer, growing a third insulating dielectric layer, and preparing a grid electrode; source electrode metal and drain electrode metal respectively grow on two sides of the grid electrode; field plate metal grows above the source electrode metal and the grid electrode metal and is filled with a fourth insulating dielectric layer; a deep groove is formed in the middle of the circuit and penetrates through the fourth insulating medium layer, the third insulating medium layer, the AlGaN layer, the GaN layer, the AlN layer, the top silicon layer and the filling insulating medium. Filling the top with a fifth insulating dielectric layer; and obtaining a half-bridge integrated circuit through a top through hole and an interconnection process. According to the invention, the parasitic effect can be reduced, and leakage current and switching loss are reduced.

Exemplary embodiments include a reduction circuit for a transformerless rectifier, for reducing leakage and / or touch currents.The reduction circuit is designed to provide a control signal for the rectifier and to generate the control signal based on at least one of the following measurement information: a mains-side measurement of a displacement voltage, a mains-side measurement of a zero-sequence voltage, a DC-side voltage between a positive terminal of the rectifier and the center point of the rectifier's intermediate circuit, a DC-side voltage between the center point of the rectifier's intermediate circuit and a negative terminal of the rectifier, a common-mode component of a rectifier's dead-time voltage, a fault current, and / or a modulation-induced voltage of the rectifier. Examples of implementation also include corresponding systems, methods and computer programs for reducing leakage and / or touch currents.

The utility model relates to the technical field of integrated circuit, especially relate to a totem pole bridgeless power factor correction device, power supply and power supply system, in the device, power factor correction module includes first transistor, second transistor, third transistor, fourth transistor, inductance, control module includes first input signal processing circuit, second input signal processing circuit, first drive assembly, second drive assembly, first adjusting transistor, second adjusting transistor, the output of first drive assembly is connected in the grid of third transistor, the output of second drive assembly is connected in the grid of fourth transistor, first adjusting transistor, second adjusting transistor have respectively in parallel on third transistor and fourth transistor. The utility model embodiment can reduce the discharge speed of the connecting point of third transistor, fourth transistor, to slow down common mode switching speed, reduce common mode interference, thereby reduce the leakage current peak.

A radiation imaging apparatus includes a substrate and a radiation-sensitive imaging region in the substrate including pixels. The radiation imaging apparatus includes a guard region at or immediately adjacent a cut edge of the substrate, wherein the guard region reduces the leakage current reaching the radiation-sensitive imaging region from the cut edge when the radiation imaging apparatus is in use. The radiation-sensitive imaging region is electrically reverse biased with respect to the substrate. The radiation-sensitive imaging region includes a portion adjacent the guard region that is closest to where incident radiation impacts the radiation imaging apparatus. The pixels include a first pixel electrode located in the portion where a first longitudinal end of the first pixel electrode closest to the guard region is a first distance from the guard region that reduces an amount of the leakage current received by the first pixel electrode.

To provide a solar cell and a method of forming the same.SOLUTION: The solar cell includes a substrate and a plurality of unit cells including a first electrode, an active layer, and a second electrode, and the unit cells are spaced apart from each other to expose the substrate. Since the unit cells are spaced apart from each other to have an insulation structure or a non-power generation region in which the substrate is exposed, a leakage current may be minimized and power generation efficiency of the solar cell may be increased.SELECTED DRAWING: Figure 3