325 results about "Leakage current reduction" patented technology

In a semiconductor integrated circuit, a control transistor 4 and a potential clamp circuit 9 are arranged between a power supply line 2 and a virtual power supply line 3. Even in a sleeve mode where the control transistor 4 is turned off, the potential clamp circuit 9-1 clamps the virtual power supply line 3 at a certain potential to hold a potential state (high level or low level) of each node of a logical circuit. At this time, each FET forming the logical circuit is applied with a back bias so that a threshold voltage Vt becomes higher than that in an active mode. Therefore, a leakage current can be decreased. In the semiconductor integrated circuit, the threshold voltage Vt of the control transistor 4 can be selected to be equal to that of one FET of the complementary FET forming the logical circuit. Therefore, the layout area and the number of manufacturing steps can be reduced.

An amorphous-silicon TFT (thin-film-transistor) in an LCD device has a larger channel length at both the edge portions of the channel of the TFT compared to the central portion of the channel by forming chamfers at the corners of the source and drain electrodes. The larger channel length at both the edge portions reduces the leakage current caused by the turned-around light incident onto the channel.

An integrated circuit transistor body bias regulation circuit and method of especial applicability with respect to low voltage applications wherein the threshold voltage (V_t) of certain transistors is lowered at low power supply voltage (VCC) levels, low temperature and/or high V_t process conditions to assure adequate transistor drive but may also be raised at high VCC levels, high temperature and/or low V_t process conditions to reduce leakage current. In this manner, circuit speed that is closer to constant (versus VCC, temperature and process variation) is thereby achieved.

Embodiments of the invention provide a standby leakage current reduction circuit and a semiconductor memory device comprising the standby leakage current reduction circuit. The invention provides a circuit adapted to reduce standby leakage current in a semiconductor memory device comprising memory cells. The circuit comprises a bias signal generator adapted to generate a bias signal, wherein a voltage level of the bias signal is set in accordance with a result of a standby leakage current test. The circuit further comprises a ground voltage controller adapted to receive the bias signal from the bias signal generator and to control a level of a voltage apparent on a virtual ground terminal in response to the bias signal while the semiconductor memory device is in a standby mode.

Leakage current through stray or parasitic capacitance (which is particularly large in devices such as photovoltaic cell arrays and which are damaged by such leakage currents) due to common mode switching noise in a full bridge single phase power converter is reduced at high frequencies by magnetically coupling the two phase legs on the AC side of the power converter and connecting mid points of the AC and DC sides of the power converter and is reduced at low frequencies by use of a feedback arrangement that modifies sinusoidal modulation of the switches of the full bridge converter to function as an active filter. The magnetic coupling for the two phase legs is designed in a simple manner to avoid saturation based on volt-second considerations.

There is provided a MTCMOS flip-flop configured to operate at high speed and to reduce leakage current while realizing a retention function in a sleep mode. The MTCMOS flip-flop may include a signal generator adapted to output an internal clock signal or a sleep mode control signal based on changes in a retention signal and an external clock signal, a master latch adapted to latch an input signal and to output a master latch output signal based on the internal clock signal, and a slave latch connected to an actual ground and adapted to latch the master latch signal, to output a slave latch output signal under control of the internal clock signal, and to maintain the latched signal under control of the sleep mode control signal in the sleep mode.

The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.

By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.

A method of semiconductor manufacturing is disclosed in which doping is accomplished by the implantation of ion beams formed from ionized molecules, and more particularly to a method in which molecular and cluster dopant ions are implanted into a substrate with and without a co-implant of non-dopant cluster ion, such as a carbon cluster ion, wherein the dopant ion is implanted into the amorphous layer created by the co-implant in order to reduce defects in the crystalline structure, thus reducing the leakage current and improving performance of the semiconductor junctions. Dopant ion compounds of the form A_nH_x⁺ and A_nR_zH_x⁺ are used in order to minimize crystal defects as a result of ion implantation. These compounds include co-implants of carbon clusters with implants of monomer or cluster dopants or simply implanting cluster dopants. In particular, the invention described herein consists of a method of implanting semiconductor wafers implanting semiconductor wafers with carbon clusters followed by implants of boron, phosphorus, or arsenic, or followed with implants of dopant clusters of boron, phosphorus, or arsenic. The molecular cluster ions have the chemical form A_nH_x⁺ or A_nR_zH_x⁺, where A designates the dopant or the carbon atoms, n and x are integers with n greater than or equal to 4, and x greater than or equal to 0, and R is a molecule which contains atoms which, when implanted, are not injurious to the implantation process (for example, Si, Ge, F, H or C). These ions are produced from chemical compounds of the form A_bL_zH_m, where the chemical formula of L_z contains R, and b may be a different integer from n and m may be an integer different from x and z is an integer greater than or equal to zero.

There is provided a semiconductor device, in which characteristics of the semiconductor device are improved by thinning a gate insulating film and a leak current can be reduced, and a manufacturing method thereof. An aluminum film which is a metal film is formed over a polycrystalline semiconductor film, and plasma oxidizing treatment is performed to the aluminum film, whereby an aluminum oxide film is formed by oxidizing the aluminum film, and a silicon oxide film is formed between the polycrystalline semiconductor film and the aluminum oxide film.

A method for forming a Ta2O5 capacitor on a semiconductor device reduces leakage current and increases cell capacitance by utilizing a two-step rapid thermal nitridation (RTN) process to form a nitride layer on a hemi-spherical grain (HSG) storage node. The first RTN process is performed in a NH3 atmosphere at 800±40° C. for 180±60 seconds, thereby forming a nitride layer having a thickness of about 4 Å. The second RTN process is performed in a NH3 atmosphere at 850±40° C. for 180±60 seconds, thereby increasing the thickness of the nitride layer to at least about 7 Å. Therefore, a nitride layer that is thick enough to act as an oxidation barrier is achieved, but agglomeration of the HSGs on the storage node due to high process temperatures is prevented. To make the structure more readily adaptable to process for manufacturing DRAMs with Ta2O5 dielectric layers, a rapid thermal oxidation (RTO) process can then be performed in an O2 or N2O atmosphere at 850±50° C. for 90±30 seconds to thereby form a combined layer comprising a nitride layer and an oxide layer.

A charge pump circuit able to enhance the rising and falling characteristics of a current output, drive the current output with a short pulse, reduce leakage current at the OFF time when a current is not output, and realize a reduction of a power consumption and a PLL circuit using same. By outputting a charge current or a discharge current in accordance with an up signal or a down signal and turning on a third transistor (PC, NC) at the OFF time when the current is not output, an inverse bias voltage is supplied between a gate and a source of the second transistor (PA, NA), whereby a reduction of the leakage current can be realized. When the second or third transistor is switched in accordance with the up signal or the down signal, the timing of the control signal is appropriately controlled, simultaneous turning on of the second and third transistors can be avoided, release or injection of charges from and to the output terminal of the charge pump circuit can be prevented, and the stability of an oscillation frequency of a VCO can be improved.

A programmable logic device (PLD) having minimal leakage current for inactive logic blocks is provided. The PLD includes an array of logic blocks. Among the array of logic blocks, one of the array of logic blocks monitors the level of activity of each of the remaining logic blocks. The level of activity may be monitored by observing the input and output pin of the logic blocks. The PLD further includes a plurality of driven wires defining a routing pattern between the array of logic blocks. When one of the array of logic blocks detect inactivity in any one of the remaining logic blocks for a certain duration, the one of the array logic blocks transmits a signal invoking a sleep mode for the inactive logic blocks. A sleep transistor with a threshold voltage level that is capable minimizing the leakage current is associated with each of the remaining block. The gate of the sleep transistor receives the signal transmitted by one of the array logic blocks and the signal switches off the sleep transistor.

Systems and methods that may be implemented for time-based management of storage memory controller (e.g., RAID controller) backup battery life in information handling systems by limiting the backup battery system operation time in order to save energy, reduce the impact of leakage current, and prolong memory controller backup battery shelf life while at the same time meeting requirements of back-up time for storage/server applications. The disclosed systems and methods may be implemented, for example, by providing a battery system controller that implements a pre-set memory controller backup battery operation time, in combination with a hardware-controlled mechanism that extends backup battery system operation time by disabling one or more current leakage paths within the storage memory controller circuitry.

To provide a measurement device which allows long-term accurate measurement of voltage without adversely affecting a device under test, by ensuring a predetermined level of resistance to ESD and reducing leakage current. A measurement device includes a probe needle for contacting a device under test, a first FET for detecting voltage of the device under test, and a protection circuit for protecting the first FET from static electricity. The protection circuit includes a second FET having an oxide semiconductor film as a channel formation region.

Various methods, apparatuses, and systems are described in which a volatile memory that includes a plurality of volatile memory cells as well as a voltage limiting component and a current limiting component. Power consumption in a standby mode is controlled. The voltage limiting component and the current limiting component couple between the volatile memory cells and the ground voltage potential. One or more rows of memory cells in the memory array are isolated from the ground voltage potential to control power consumption in the standby mode by having the current limiting component stop passing current in the standby mode. A floating ground voltage potential sensed by each memory cell when in the standby mode is controlled by configuring the voltage limiting component to conduct when the floating ground voltage potential is larger than a threshold voltage of the voltage limiting component in order to reduce leakage current but reliably maintain the stored contents of the volatile memory cell. The floating ground voltage potential is internally raised higher than a voltage biasing the bulk of the transistors in the volatile memory cells by coupling the floating ground voltage potential to the voltage limiting component.