Method and manufacturing low leakage MOSFETs and FinFETs

Abstract

By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation / relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to the fabrication of integrated circuits and, more specifically, a method for fabricating field effect transistors (FETs) wherein source-drain current flows along a (100) crystal plane. BACKGROUND

[0002] Semiconductor integrated circuit chips are constructed as dice on wafers. A typical wafer material is crystalline silicon. Wafers are cut from single crystal silicon ingots grown from polysilicon by means of, for example, Czochralski method (CZ) crystal growth. CZ wafers are preferred for VLSI applications as they can withstand high thermal stresses and are able to offer an internal gettering mechanism that can remove unwanted impurities from device structures on a wafer surface. This also gives the wafer a uniform internal structure based on silicon's diamond cubic lattice structure. Although the diamond cubic lattice provides strength and rigidity to the wafer, defects in the crystal lattice, for example, slip dislocatio...

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