35results about How to "Improve electrical isolation" patented technology

The invention provides a gallium oxide ultraviolet detector based on a difunctional self-assembly passivation layer and a preparation method thereof, the gallium oxide ultraviolet detector comprises a substrate layer, an oxidant layer and the difunctional self-assembly passivation layer which are arranged from bottom to top, and two sides of the difunctional self-assembly passivation layer are provided with metal electrodes in contact with a gallium oxide layer. Wherein the bifunctional self-assembly passivation layer comprises a first passivation layer and a second passivation layer which are arranged from bottom to top, the passivation material of the first passivation layer is a material for reducing surface defects of the gallium oxide layer, and the passivation material of the second passivation layer is a material for enhancing the ultraviolet photon absorption rate. Passivation materials with different functions are combined to form the dual-function self-assembly passivation layer, and the dual-function self-assembly passivation layer is adopted to perform passivation treatment on the gallium oxide ultraviolet detector, so that the performance of the gallium oxide ultraviolet detector is jointly improved from two aspects of reducing surface defects of gallium oxide and enhancing ultraviolet photon absorption.

The utility model discloses an IGBT (Insulated Gate Bipolar Transistor) protection circuit, which comprises a driving module, the input control end of the driving module is connected with the cathode of a Zener diode D0, and the cathode of the Zener diode D0 is also connected to the emitter E of an insulated gate bipolar transistor Q0. The grid electrode G of the insulated gate bipolar transistor Q0 is connected to the driving output end of the driving module through a resistor R6, and the collector electrode C of the insulated gate bipolar transistor Q0 is connected with the overcurrent detection output end of the driving module through a fast recovery diode FR107. According to the technical scheme, transient voltage spikes can be effectively restrained, the IGBT is protected against overvoltage damage, the anti-interference capacity of the circuit is enhanced, a fast recovery diode FR107 is further arranged at the overcurrent detection output end of the driving module, the switching speed can be increased, the overvoltage phenomenon during switching-off is reduced, the service life of the IGBT and the driving module is prolonged, and the service life of the IGBT and the driving module is prolonged. And the working reliability of the whole circuit is improved.

The invention discloses a semiconductor device, a preparation method of the semiconductor device and an electronic device, and the semiconductor device comprises a semiconductor substrate which is provided with a first surface and a second surface which are opposite to each other; a plurality of photodiodes formed in the semiconductor substrate; a plurality of quenching resistor structures corresponding to the plurality of photodiodes; and trench isolation structures formed between adjacent photodiodes. The trench isolation structure comprises a deep trench isolation structure which extends into the semiconductor substrate from the first surface, and a first shallow trench isolation structure and a second shallow trench isolation structure which extend into the semiconductor substrate from the second surface. The two shallow trench isolation structures are distributed on the two sides of the deep trench isolation structure and intersect with the deep trench isolation structure in the semiconductor substrate, and a preset distance exists between the bottom of the deep trench isolation structure and the second surface. According to the invention, the electrical isolation between the polycrystalline silicon and the deep trench isolation structure is better, the high-voltage resistance is stronger, and electric leakage is avoided under high working voltage.

The utility model provides a solid-sealed polar pole, a breaker and a ring main unit, the solid-sealed polar pole comprises a polar pole body, a moving end shielding seat and a static end shielding seat, the moving end shielding seat is formed by casting metal, the outer surface of the metal is covered with an insulating resin layer, the static end shielding seat is formed by casting metal, and the outer surface of the metal is covered with an insulating resin layer. And the insulating resin layers of the pole body, the moving end shielding seat and the static end shielding seat are integrally poured to form a whole. Therefore, the insulating resin covers the outer surfaces of the polar column body, the moving end shielding seat and the static end shielding seat together, and the insulating resin is used as an insulating material, so that the polar column body, the moving end shielding seat and the static end shielding seat can be tightly combined together in an integrated pouring manner, and the connecting parts of all the components are wrapped by the insulating material; in addition, an extra insulating layer is provided, and electrical isolation is carried out on the whole solid-sealed polar pole, so that the insulating strength of the whole solid-sealed polar pole is improved.

The invention discloses a multi-mode switching control method suitable for a grid-connected isolation inverter, and the method comprises the steps: in each half power grid voltage period, according to a power grid instantaneous voltage phase Theta g outputted by a phase-locked loop in the isolation inverter, the phase Theta g is within [0, pi], then the phase Theta g is compared with given power grid voltage phases Theta g1 and Theta g2, the Theta g1 and Theta g2 meet the condition that Theta g1 is smaller than or equal to Theta g2, and the Theta g1 is smaller than or equal to Theta g2; a variable-frequency discontinuous conduction mode, namely a variable-frequency DCM mode, is adopted in the ranges of 0 < theta g < theta g 1 and pi-theta g 2 < theta g < pi, a main switching tube of a flyback converter in the isolation inverter is controlled to be switched on when the period is larger than a given switching period and the drain-source voltage valley value, and a critical conduction mode, namely a BCM mode, is adopted in the range of theta g 1 < theta g < pi-theta g 2. And controlling a main switch tube of the flyback converter to be switched on at the drain-source voltage valley value. Different working modes are adopted under different output voltages, so that the switching loss of the isolation inverter in a full-load range is reduced, and the energy conversion efficiency of the isolation inverter is greatly improved.

The invention relates to a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the active array is positioned on the substrate and comprises a plurality of active columns which are arranged at intervals along a first direction and a second direction, and the first direction is intersected with the second direction; the bit line structure is positioned on the substrate, the bit line structure comprises a plurality of bit lines which are arranged at intervals along a second direction, and the bit lines extend along the first direction and are electrically connected with the plurality of active columns which are arranged at intervals along the first direction; the isolation structure is located below the bit line, the isolation structure comprises an isolation layer and an air gap located in the isolation layer, and the resistivity of the isolation layer is larger than that of the substrate. According to the invention, the electrical isolation effect between the adjacent bit lines is enhanced, so that the problem of electric leakage between the adjacent bit lines is reduced.

The invention provides a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps of forming a substrate and a plurality of active columns located on the substrate, wherein an isolation groove for exposing the substrate is formed between every two adjacent active columns; forming an isolation layer filling the isolation groove, wherein the isolation layer has a solid structure and the top surface of the isolation layer is flat; forming a signal line groove exposing part of the active column; a conductive line is formed in the signal line trench. According to the invention, the problem of electric leakage between adjacent memory cells is reduced, and the electrical performance of the semiconductor structure is improved.

The embodiment of the invention provides a capacitor chip structure and a manufacturing method. The manufacturing method comprises the following steps: forming a first conductive layer on a first surface of a glass substrate; forming a capacitor dielectric layer on one side, far away from the glass substrate, of the first conductive layer; the capacitor dielectric layer also covers the side wall of the first conductive layer, the capacitor dielectric layer is provided with a first through hole, and the first through hole penetrates through the capacitor dielectric layer and exposes part of the surface of the first conductive layer; forming a second conductive layer on one side, away from the first conductive layer, of the capacitor dielectric layer; the boundary of the second conductive layer shrinks inwards towards the center of the capacitor chip structure relative to the boundary of the first conductive layer; forming an insulating layer on one side, away from the capacitor dielectric layer, of the second conductive layer; forming a first electrical connection structure; and forming a second electrical connection structure.

The invention relates to the technical field of electric energy routers, in particular to a power distribution area flexible mutual aid system based on an electric energy router, and the system is characterized in that a DC bus in a flexible mutual aid device is connected with an external power distribution area through a plurality of bidirectional DC / AC ports, and is used for completing electrical coupling and power intercommunication; the plurality of bidirectional DC / AC ports are connected with the direct current bus in parallel, the direct current bus is connected with an energy storage port and a photovoltaic port, the energy storage port is communicated with an external energy storage device, the photovoltaic port is communicated with an external photovoltaic device, and the flexible mutual aid device is communicated with an external power grid dispatching through a controller. According to the invention, normalized flexible interconnection between feeder lines is realized through the flexible mutual aid device, potential safety hazards caused by frequent displacement of a conventional switch based on an interconnection switch are avoided, the control flexibility and rapidity of the power distribution network are improved, and the power distribution network has the advantages of open-loop operation and closed-loop operation at the same time.

The invention discloses a low-cost BMS isolation driving circuit scheme and an implementation method, and relates to the technical field of isolation driving, the low-cost BMS isolation driving circuit scheme comprises a driving module and a conversion module, the driving module and the conversion module are connected in parallel, and the driving module is used for being connected with external equipment and the conversion module and sending an isolation driving signal. The conversion module is used for outputting a 12V isolated voltage-stabilized power supply; the driving module comprises a signal processing unit and an output control unit, the conversion module comprises a voltage processing unit and a voltage output unit, the signal processing unit is electrically connected with the output control unit and the voltage processing unit, and the voltage processing unit is electrically connected with the voltage output unit. Through cooperative operation of the triode Q26, the photoelectric coupler U2, the MOS tube Q25 and the common-mode inductor T1, cost effectiveness and simplified design are achieved, and meanwhile good electrical isolation performance and voltage output stability are kept.

The present invention discloses a micro display device and a preparation method thereof, which relates to the field of display technology, wherein the micro display device comprises: a driving substrate; a pixel array layer, comprising a plurality of micro display units, arranged on the surface of the driving substrate; a nano composite film, comprising a multi-layer nano-scale film layer, located in the light emitting direction of the side wall of the micro display unit; wherein the multi-layer nano-scale film layer comprises an insulating bottom layer, an intermediate transmission layer, a reflection layer and a protective layer which are sequentially away from the side wall. The technical solution provided by the present invention not only enhances the optical isolation and electrical isolation between the micro display units, but also meets the demand for preparing micro display units of smaller size.

The invention relates to the technical field of micro electro mechanical systems, in particular to an MEMS pressure sensor chip capable of working in an extreme environment and a manufacturing method of the MEMS pressure sensor chip. The pressure sensor comprises an SOI silicon-on-insulator substrate, a piezoresistive resistor, a middle silicon nitride insulation isolation layer, a through hole layer, an organic epoxy insulation packaging layer, a sensor film layer and a conductive material assembly used for connection. Four piezoresistive resistors are formed by ion implantation and are symmetrically distributed on the thin film layer to form a Wheatstone bridge structure. The sensor film layer is square, the size of the sensor film layer is smaller than that of the substrate, the sensor film layer is I-shaped, the thermal stress concentration effect is reduced, cracks or deformation is avoided, the sensor film layer and the substrate jointly form a vacuum cavity, and high structural stability is kept. The insulating packaging layer is connected with the through hole layer, and the through holes are connected with the insulating layer through the conductive material of the opening of the insulating layer. The sensor provided by the invention can keep higher measurement precision and sensitivity in an extreme temperature environment.

The invention discloses a semiconductor device, a preparation method, a chip and electronic equipment, and relates to the technical field of semiconductors, the semiconductor device comprises a plurality of high-electron-mobility transistors and isolation grooves, the isolation grooves are arranged between adjacent first high-electron-mobility transistors and second high-electron-mobility transistors, and the first high-electron-mobility transistors and the second high-electron-mobility transistors are adjacent to the first high-electron-mobility transistors and the second high-electron-mobility transistors. The isolation groove at least penetrates through the layer where the ohmic contact layers of the high-electron-mobility transistors are located, the ohmic contact layers of the first high-electron-mobility transistor and the second high-electron-mobility transistor are separated, and electrical isolation is achieved. Moreover, a film layer is arranged between the bottom wall of the isolation groove and the substrate, the film layer is also arranged between the barrier layer and the substrate, the film layer below the isolation groove comprises an ion implantation region, and the ohmic contact layer is further electrically isolated. Therefore, the isolation groove and the ion implantation region are mutually combined to realize electrical isolation, the isolation difficulty of a subsequent device is effectively reduced, isolation high-temperature failure is avoided, and the isolation stability of the device is improved.

The application relates to a high-voltage pulse electric field ablation device and method, and belongs to the technical field of medical instruments, which solves the problem of long pulse edge and pulse width generated by an existing high-voltage fast switch. The device comprises a high-voltage output module, a capacitor and a control unit. The high-voltage output module comprises a first branch, an additional branch and a second branch which are connected in parallel between a direct-current high-voltage power supply and a grounding end in sequence. The first branch comprises first and second power switches which are connected in series. The second branch comprises fifth and sixth power switches which are connected in series. The additional branch comprises third and fourth power switches which are connected in series. The capacitor is connected between a first node between the first and second power switches and a second node between the third and fourth power switches. The first to sixth power switches are opened and closed to generate a bipolar high-voltage pulse with picosecond or nanosecond rising and falling edges and nanosecond pulse width. The amplitude, rising time, falling time, frequency, pulse width, positive and negative pulse time difference and pulse number of the pulse can be adjusted. The device realizes super-fast pulse rising and falling edges and super-short pulse width.

The present application discloses a bonding structure and a forming method for a MEMS micromirror, comprising an SOI substrate, a patterned bonding layer, a bonding substrate and an isolation groove structure, wherein the patterned bonding layer is located between the SOI substrate and the bonding substrate; the SOI substrate has a plurality of metal interconnect structures that penetrate vertically, and a dielectric layer is provided between the metal interconnect structure and the SOI substrate; at least a portion of the patterned bonding layer is located on the metal interconnect structure, and the metal interconnect structure and the bonding substrate are electrically connected through the patterned bonding layer; the isolation groove structure penetrates the patterned bonding layer and the bonding substrate vertically, and exposes the dielectric layer on the peripheral side of at least a portion of the metal interconnect structures in the plurality of metal interconnect structures. The present application introduces a patterned bonding layer with a certain thickness and pattern between the SOI substrate and the bonding substrate, avoids the undesired adhesion between the two layers of silicon materials in the vertical direction, improves the isolation effectiveness of the SOI substrate and the bonding substrate, and further improves the reliability and stability of electrical isolation applied to the MEMS micromirror.

The application discloses a three-dimensional memory device, comprising a substrate, a stack structure arranged on the substrate, and a memory string structure penetrating through the stack structure. The stack structure comprises a plurality of conductive layers and a plurality of dielectric layers arranged alternately. The memory string structure comprises a conductive pillar and a memory layer between the conductive pillar and the stack structure and surrounding the conductive pillar, wherein the memory layer comprises a plurality of first protrusions respectively filled in a plurality of first recesses at the junctions of the conductive layers and the dielectric layers. The application can improve the electrical isolation between memory cells and reduce the signal interference problem between adjacent memory cells during writing or reading.

The utility model relates to the technical field of generator car access boxes, in particular to a wall-mounted access box, which comprises a box body, an insulating back plate, a knife switch and a plurality of quick connection assemblies, the box body is provided with an inner cavity, the insulating back plate divides the inner cavity into a front cavity and a rear cavity, the knife switch is mounted on the insulating back plate, and the quick connection assemblies are mounted on the front cavity and the rear cavity. The plurality of quick-connection assemblies are arranged in the front cavity in a row at intervals, each quick-connection assembly comprises a connection busbar, a quick-insertion connector arranged on the connection busbar, a terminal block arranged on the connection busbar and a grounding ring arranged on the connection busbar, the connection busbar is vertically arranged, and the quick-insertion connector is connected with the terminal block. The quick-plug connectors, the terminal blocks and the grounding rings are distributed on the connecting busbar at intervals. According to the utility model, the structure is novel, and a good electrical isolation effect can be achieved; the functions of the quick-plug connector, the terminal block and the grounding ring are integrated on the connecting busbar, so that the connecting busbar is integrally compact in structure, small in occupied volume, convenient to assemble, disassemble, replace and maintain, and high in use flexibility.

This disclosure provides a method for fabricating a laser chip. An electrically isolated layer group comprising a first N-type InP layer, a second N-type InP layer, and a first active layer are sequentially grown on a substrate. A second active layer is grown outside a first position of the first active layer. First and second electrically isolated layers and a conductive layer are grown at the interface between the first and second active layers. Second and third P-type InP layers and a contact layer are sequentially grown on the first active layer, the conductive layer, and the second active layer. A second position of the contact layer is etched down to the third P-type InP layer. Both the first and second contact layers are etched down to the first N-type InP layer. A passivation layer is grown and etched down to the first and second contact layers and the first N-type InP layer. Positive and negative electrodes are grown. In this disclosure, the substrate is conductive, avoiding the problem of charge accumulation on the substrate surface leading to internal electric field distortion. The electrically isolated layer group prevents current from flowing from the second N-type InP layer into the substrate. The first N-type InP layer is conductive, enabling the positive and negative electrodes to conduct.

The invention discloses a bonding structure for an MEMS micromirror and a forming method, the bonding structure comprises an SOI substrate, a graphical bonding layer, a bonding substrate and an isolation groove structure, and the graphical bonding layer is located between the SOI substrate and the bonding substrate; the SOI substrate is provided with a plurality of metal interconnection structures which longitudinally penetrate through the SOI substrate, and a dielectric layer is arranged between the metal interconnection structures and the SOI substrate; at least part of the graphical bonding layer is located on the metal interconnection structure, and the metal interconnection structure is electrically connected with the bonding substrate through the graphical bonding layer; the isolation groove structure longitudinally penetrates through the graphical bonding layer and the bonding substrate and exposes the dielectric layer on the peripheral side of at least part of the metal interconnection structures in the multiple metal interconnection structures. The graphical bonding layer with a certain thickness and pattern is introduced between the SOI substrate and the bonding substrate, unexpected adhesion between the two layers of silicon materials is avoided in the longitudinal direction, the isolation effectiveness of the SOI substrate and the bonding substrate is improved, and then the electrical isolation reliability and stability applied to the MEMS micromirror are improved.

The application relates to a DNA self-assembly nano-floating gate type 3D NAND structure, which comprises a substrate, a periodic stack structure arranged on the substrate, the stack structure comprising a plurality of first insulating medium layers and nano-floating gate storage structures alternately stacked, a plurality of through holes penetrating through the stack structure, a center channel layer being arranged on the side wall of the through hole, and a center insulating medium layer being filled in the center channel layer; wherein the nano-floating gate storage structure comprises a tunneling medium layer contacting the center channel layer, a blocking medium layer wrapping the outside of the tunneling medium layer, and a gate word line metal located outside the blocking medium layer, and a carbon nanotube floating gate layer is arranged in the tunneling medium layer. The structure can significantly improve the storage density and size miniaturization ability, and greatly reduce the working voltage and driving power consumption.

The utility model relates to the technical field of adapters, in particular to a BOSA adapter with ground isolation, which comprises a first metal piece, a second metal piece clamped on the first metal piece and a ceramic pin inserted on the second metal piece, and further comprises an insulating ring sleeved at the clamping position of the first metal piece and the second metal piece and used for enhancing electrical isolation; the first buckling piece is arranged on the first metal piece and used for being connected with the insulating ring in a clamping mode; the second buckling piece is arranged on the second metal piece and used for being connected with the insulating ring in a clamping mode; according to the utility model, the insulation ring is sleeved at the clamping part of the first metal piece and the second metal piece, and the two buckling pieces are arranged on the insulation ring, so that the connection strength of the insulation ring is enhanced, the structure is exquisite and firm, the insulation ring can be repeatedly used, the electrical isolation performance is good, and good insulation can be ensured in a power supply state below 50V.

A memory structure and a method for forming the same, wherein the memory structure includes: a substrate; a plurality of isolation layers located within the substrate; a plurality of floating gate structures located on the substrate, the isolation layers being located between adjacent floating gate structures; a barrier layer located on the surface of the floating gate structures; and a control gate located on the substrate, the control gate covering the plurality of floating gate structures, wherein a cavity is formed within the control gate between adjacent floating gate structures. The cavity within the control gate between adjacent floating gate structures increases the dielectric constant between adjacent floating gate structures, thereby improving the electrical isolation between adjacent floating gate structures and reducing crosstalk between adjacent floating gate structures.

The utility model discloses a packaging structure for a chip, which comprises an electric connection limiting frame, an electric connection clamping groove is arranged in the electric connection limiting frame, the electric connection clamping groove is arranged in four inner walls, the outer part of the electric connection clamping groove is communicated with a plurality of electric connection jacks, and the plurality of electric connection jacks are respectively arranged in four side walls of the electric connection limiting frame. Through the combination of the electric connection limiting frame and the lamination limiting frame, the modular packaging of the integrated chip is realized, the design facilitates the installation, replacement and expansion of the integrated chip, the flexibility and maintainability of the packaging are improved, the multi-layer lamination of the integrated chip can be realized through the increase and decrease of the lamination limiting frame, and the packaging efficiency is improved. The structural design is suitable for application scenes needing high integration, the packaging density and the space utilization rate are effectively improved, the connecting lines are etched in the connecting pole pieces, customized design can be carried out according to the connecting requirements of different types of integrated chips, and the compatibility and adaptability of the packaging structure to different chips are improved through the design.

The utility model discloses a packaging structure of a chip and an antenna module, which comprises an isolation frame, a semiconductor chip, an antenna module and a plastic package body, the isolation frame is provided with a plurality of frame pins and a plurality of base islands, a gap is arranged between two adjacent base islands, the base islands are provided with the semiconductor chip, the antenna module is fixed on the base islands in an adhesive manner, and the plastic package body is arranged on the isolation frame. The semiconductor chip is electrically connected with the antenna module through the first bonding wire, the semiconductor chip is electrically connected with the frame pin, and the plastic package body wraps the semiconductor chip, the antenna module, the base island, the first bonding wire and part of the frame pin. The packaging structure of the chip and the antenna module is novel in structure, and the built-in and good electrical isolation of the antenna module are realized; a direct wire bonding mode is adopted to realize the connection between the chip and the antenna module, so that the packaging cost can be reduced, and the requirements of high-frequency signal transmission and complex peripheral wiring design can be met; and the antenna module is fixed on the base island in a gluing manner, so that the production consistency can be improved.

The invention relates to a method for forming a semiconductor structure. The forming method of the semiconductor structure comprises the following steps that a substrate is provided, the substrate comprises an array area and a peripheral area, and the array area comprises a plurality of active columns which are arranged at intervals; forming a dielectric layer covering the array region and the peripheral region, an isolation layer covering the side wall and the top surface of the dielectric layer in the peripheral region, and a covering layer covering the isolation layer, wherein the width of the dielectric layer in the first direction is 40-100 nm; removing a part of the dielectric layer in the array region, and removing the covering layer in the peripheral region to expose the active columns; forming a conductive material layer covering the array region and the peripheral region; and removing part of the conductive material layer in the array region and all the conductive material layer in the peripheral region to form a conductive layer electrically connected with the active column. The manufacturing cost of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved.

The embodiment of the invention provides a fault detection method, device and equipment and a medium, which are applied to an inverter system, the inverter system comprises at least two relay groups, the relay groups are connected in series, any relay group comprises at least two relays, and the relay groups are connected in series. The at least two relays are respectively arranged on different power supply lines of the inverter system; the method comprises the following steps: respectively sending driving signals to relays in each relay group; and generating a fault detection result of each relay based on the input side phase voltage sampling value and the output side phase voltage sampling value of each relay. And the fault detection accuracy is improved.

This invention provides a frequency-to-analog safety barrier, comprising a voltage conversion circuit, a transformer coil drive circuit, a transformer, a first AC voltage rectification and filtering circuit, a frequency signal processing circuit, a NAMUR signal processing circuit, an NPNPNP signal processing circuit, a frequency processing circuit, an MCU control circuit, a TTL output interface, an isolation chip, a square wave processing circuit, a filtering circuit, a DC output circuit, and an alarm relay. The voltage conversion circuit is connected to the transformer via the transformer coil drive circuit. The transformer supplies power to the hazardous and safe zones via the first AC voltage rectification and filtering circuit. Multiple intrinsically safe terminals in the hazardous zone are connected to the frequency processing circuit via three signal processing circuits. The frequency processing circuit outputs to the MCU control circuit. The MCU output sequentially passes through the TTL interface, the isolation chip, the square wave processing circuit, and the filtering circuit to the DC output circuit. This invention achieves frequency signal to analog quantity conversion and safety isolation, increasing system stability.

The utility model discloses a semiconductor device which comprises a substrate, a plurality of wire structures, a dielectric layer, a plurality of plug structures, a plurality of gap walls and a barrier layer. The substrate includes a plurality of active regions and a plurality of shallow trench isolations. The lead structures extend on the substrate in parallel and are staggered with the active region and the shallow trench isolation. The dielectric layer is disposed on the substrate and includes a composite layer structure between the substrate and a portion of the wire structure. The spacer is disposed on a sidewall of the wire structure. The barrier layer includes a first portion disposed on the gap wall and a second portion extending into the composite layer structure. Therefore, the semiconductor device has more optimized component structure and efficiency, thereby improving operation performance.

The invention belongs to the technical field of converters, and discloses a Sepic power factor correction converter which comprises a conversion circuit, the conversion circuit comprises a port L and a port N. The port L is connected with one end of a capacitor C201 and one end of an inductor L21, the other end of the capacitor C201 is connected with one end of a capacitor C244, the other end of the inductor L21 is connected with a drain electrode of an MOS tube Q15, a negative end of a diode D57 and one end of a capacitor C277, and the other end of the capacitor C277 is connected with a negative end of a diode D57. The other end of the capacitor C277 is connected with one end of an inductor L17 and a pin 1 of a transformer T4, and a source electrode of the MOS tube Q15 is connected with a source electrode of the MOS tube Q14, a positive end of a diode D57, a positive end of a diode D58, the other end of the inductor L17, one end of an inductor L20, a pin 2 of the transformer T4 and a pin 3 of the transformer T4. The circuit has the advantages of being complete in protection function, high in circuit reliability, simple in software control and low in cost.