181results about How to "Improve electrical isolation" patented technology

A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side walls is substantially perpendicular to a planar surface of the substrate. The thickness of the electrode is used to control the size of the active region created within the chalcogenide alloy structure. Additional memory cells can be created along rows and columns to form a memory matrix. The individual memory cells are accessed through address lines and address circuitry created during the formation of the memory cells. A computer can thus read and write data to particular non-volatile memory cells within the memory matrix.

The invention provides a flexible piezoresistive touch sensor array and a preparation method thereof. The sensor array comprises N*N separated piezoresistive layers and a coplanar electrode layer. The piezoresistive layers are arranged on the coplanar electrode layer. Each piezoresistive layer comprises an upper finger pressing layer, a middle sensitive layer and a bottom sensitive layer, wherein the three layers are each provided with a micro pyramid; the coplanar electrode layer comprises a polymer electrode substrate and N*N gold electrode pairs located on the polymer electrode substrate. The piezoresistive layers adopt polymer films with the micro pyramid, and due to the three-layer structure, the sensitivity of the sensor at the low-voltage region can be greatly improved. In addition, in order to overcome the defect that a traditional touch sensor is large in crosstalk due to a sandwiched structure, the coplanar electrode layer is adopted, all electrodes are located on the same plane, each piezoresistive layer is attached to the corresponding electrode pair, the piezoresistive units are completely separated, and the sensitivity and anti-interference capacity of the sensor are effectively improved.

An electrical interface device (10) for towing, operable to facilitate releasably coupling one or more electrical subsystems of a towing vehicle (12) and a towed vehicle, and including associated modular, removable circuitry (24). The circuitry (24) may provide overload, short-circuit, and reverse connection protection and power signal filtering. Alternative or additional circuitry may be added to support other functionality, including interfacing a brake control subsystem. Circular receptacle and flat plug connectors (20,22) are provided to accommodate without modification a variety of electrical connectors. Covers (32,33) are also provided to protect unused connectors from adverse environmental conditions.

A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are implanted into the substrate in regions directly below the isolation trench after partially filling the trench with the dielectric material. The dielectric along the sidewalls of the trenches can serve as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. The dielectric along the sidewalls of the trenches serves as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. After the ions are implanted in the substrate below the trenches, the remainder of the trench can be filled with the same or another dielectric material. The trench isolation technique can be used to fabricate memory, logic and imager devices which can exhibit reduced current leakage and/or reduced optical cross-talk.

An inductance element (1) comprises a core (2) having a multilayer body (6) composed of magnetic alloy thin ribbons (5) and an insulating coating layer (7) which covers the peripheral surface of the multilayer body without being bonded thereto, and a coil (4) wound around the core (2). The magnetic alloy thin ribbons (5) are stacked in a non-adhered state or with a flexible insulating adhesive layer therebetween. Having such a structure, the inductance element can stably attain good characteristics even when it is small-sized or made short.

By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.

The invention relates to a circuit for eliminating noise of a switching power supply. The circuit comprises a transformer, a primary winding of the transformer is connected with an alternating current input end, a secondary winding is connected with a direct current output end, and the circuit further comprises at least one group of symmetrical Y capacitors, wherein a first Y capacitor in the group of the symmetrical Y capacitors is respectively connected with the positive input end of the alternating current input end and the negative output end of the direct current output end, and a second Y capacitor is respectively connected with the negative input end of the alternating current input end and the negative output end of the direct current output end. By arranging the symmetrical Y capacitors, not only can the purpose of eliminating the noise be achieved, but also the characteristics of high efficiency and good EMC (electromagnetic compatibility) performance can be realized in comparison with the prior art. In addition, the circuit for eliminating the noise has the advantages that the volume of the switching power supply can reduced and the cost and process are reduced in comparison with a 3Pin input structure in the prior art; and furthermore, the circuit has universal practicability in strong plug-in connection type power supplies.

A power module for converting direct current to alternating current comprising a semiconductor switching circuit device, a substrate onto which the switching circuit device is physically and electrically coupled without wirebonds, a plurality of leadframe terminals physically and electrically coupled to the substrate, and a cover including an opening exposing a bottom side of the substrate and including a wall portion oriented generally orthogonally relative to the substrate with at least some of the leadframe terminals projecting outwardly from the wall portion. The leadframe terminals projecting outwardly from the wall portion may include an affixed portion coupled to the substrate and an extending segment lying in a plane above the affixed portion with the extending segment projecting outwardly from the wall portion and the cover encapsulating the affixed portion whereby the extending segment is spaced from a plane defined by the bottom side of the substrate.

An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.

A method for forming a shallow trench isolation (STI) structure with improved electrical isolation performance including providing a semiconductor substrate including an overlying silicon oxide layer on the semiconductor substrate and a hardmask layer on the silicon oxide layer; dry etching in a first etching process to form a patterned hardmask opening for etching an STI opening; dry etching in a second etching process the semiconductor substrate to form an upper portion of an STI opening to form a polymer layer along sidewall portions of the STI opening; and, dry etching in a third etching process the STI opening to form rounded bottom corners and rounded top corners.

The invention relates to a patterned ceramic layer printed circuit substrate for optical and electronic devices. The patterned ceramic layer printed circuit substrate comprises a metal substrate, wherein a voltage-withstanding ceramic layer is formed on the metal substrate; on the voltage-withstanding ceramic layer, by using a PVD (physical vapor deposition) method, a patterned high heat-conducting ceramic layer is deposited through a baffle plate, and multiple heat-conducting isolation bases are formed; and a metal circuit layer is formed on every heat-conducting isolation base. The patterned ceramic layer printed circuit substrate for optical and electronic devices has a metal substrate in a relatively large size, can accommodate multiple optical and/or electronic devices, and is provided with good electrical isolation and thermal isolation between the multiple optical and/or electronic devices.

A connector includes a multi-port shield configured to reduce EMI. A housing is positioned inside the shield and includes one or more projections extending from a first face, the projections aligned with each port. A vertical wall is provided on the first face of the housing. Apertures in the vertical wall are aligned with the projections. The vertical wall helps reduce the amount of EMI generated by the connector.

A dome resonator (11) includes a resonator circuit (70) that excites and/or receives radio frequency magnetic resonance signals that emanate from a region of interest (14). The resonator circuit (70) includes multiple longitudinal conductive elements (110) that are coupled at a first end (80) and a second end (82) and tapered from the first end (80) to the second end (82). A resonator circuit support (74) is coupled to and supports the resonator circuit (70). A shield (76) is coupled to the resonator circuit support (74) and electrically isolates the resonator circuit (70) from a surrounding environment.

A lossless equalization controller and a control method belong to the technical field of battery equalization control. The controller comprises a battery pack formed by a plurality of cells, an equalization switch control module, an equalization power control module, an equalization power transformation module, an equalization charging control module, a system power supply module and a master control module, wherein the system power supply module supplies power to the equalization switch control module, the equalization charging control module and the master control module. The controller has the advantages of rapid equalization speed, safe and reliable equalization process, low cost and easy promotion and application. The control method includes detecting battery equalization degree, equalizing laggard cells in the battery pack when the battery equalization degree is equal to or greater than 0.3%, detecting system fault, clearing system fault and other detection steps. The equalization precision is high, and the equalization process is safe and reliable.

The invention discloses a mining high-voltage frequency converter with an explosion-proof type. The frequency converter comprises a phase-shifting transformer unit explosion-proof box and a power unit explosion-proof box; a phase-shifting isolation transformer and a heat radiation system are arranged in the phase-shifting transformer unit explosion-proof box; and a plurality of sets of power units, a control unit and a heat radiation system are arranged in the power unit explosion-proof box, wherein the plurality of sets of power units are in series connection. A high-tension side of the phase-shifting isolation transformer is in series connection with a three phase high voltage power network; the plurality of sets of power units are respectively connected with a low tension side of the phase-shifting isolation transformer; and the power units and the control unit are connected by a fiber. According to the invention, all assembling combination surfaces of the phase-shifting transformer unit explosion-proof box and the power unit explosion-proof box are constructed into sealing structures, so that an external environment is isolated from the phase-shifting transformer unit explosion-proof box and the power unit explosion-proof box; therefore, it can be avoided that corresponding chain explosions happen at high-risk occasions including a coal mine and the like and an explosion-proof effect is good. Besides, a control signal is transmitted by a fiber, so that an electrical isolation capability and an anti-electromagnetic interference performance are good.

A surgical jaw instrument having two jaw pieces mounted at the distal end section of a shaft for relative reciprocal displacement, whereby at each displaced jaw piece a sliding rod is fastened at an incline to the axis of the shaft, to which a displaceable sliding element can be connected parallel to the axis of the shaft in such a way that upon displacement of the sliding element, the jaw pieces are relatively reciprocally displaced wherein a second sliding element is mounted at the first sliding element, diametrically opposed relative to the sliding rod.

A semiconductor device and a formation method therefor are disclosed. The formation method for the semiconductor device comprises the steps of providing a substrate including a first region and a second region; forming a groove including a first part and a second part in the substrate; forming a first barrier layer at the bottom of the first part and the surface of the side wall of the groove, wherein the first barrier layer captures lattice vacancy defects or interstitial atom defects in the substrate; forming a second barrier layer at the bottom of the second part and the surface of the side wall of the groove, wherein the second barrier layer captures lattice vacancy defects or interstitial atom defects in the substrate, and defect types captured by the first barrier layer and the second barrier layer are different; forming dielectric layers for filling the grooves; forming a first well region in the first region substrate; forming a second well region in the second region substrate, wherein the doping types of the second well region and the first well region are opposite. According to the semiconductor device and the formation method therefor, the diffusion of the doping ions in the first well region and the second well region can be effectively prevented to endow the semiconductor device with a good electrical isolation performance.

A workpiece chuck includes a thermal plate assembly which includes both heating and cooling capability. The heating element can be a resistive heater in a coiled configuration disposed in a plane. The cooling can be performed via a cooling fluid circulated through cooling tubes which are also disposed in a coiled configuration in a plane. The plane of the heating element and the cooling tubes can be the same plane, and that plane can be a center plane of the thermal plate assembly. By locating the heating and cooling in the same plane, uniform heating and cooling are achieved. Also, by locating the heating element and cooling tubes in the center of the thermal plate, distortions such as doming and dishing in the thermal plate are eliminated such that the wafer can be held extremely flat on the chuck. The heating element and cooling tubes are coiled in an interleaved fashion to provide uniform heating and cooling while allowing them to simultaneously occupy the same plane.

A monolithically integrated VCSEL and photodetector, and a method of manufacturing the same, are disclosed for applications where the VCSEL and photodetector require separate operation such as duplex serial data communications applications. A first embodiment integrates a VCSEL with an MSM photodetector on a semi-insulating substrate. A second embodiment builds layers of a p-i-n photodiode on top of layers forming a VCSEL using a standard VCSEL process. The p-i-n layers are etched away in areas where VCSELs are to be formed and left where photodetectors are to be formed. The VCSELs underlying the photodetectors are inoperable, and serve to recirculate photons which are not initially absorbed back into the photodetector. The transmit and receive pairs are packaged into a single package for interface to multifiber ferrules. The distance between the devices is precisely defined photolithographically, thereby making alignment easier. In a further alternate embodiment, a FET is coupled to the p-i-n photodiode to form an integrated detector preamplifier along with the VCSEL transmitter all on the same optical reference plane.

The invention discloses a multi-channel isolated high-speed intelligent transmitting-receiving device and method for a power electronic system. The device comprises transmitting units, receiving units and isolated transmission mediums. Each transmitting unit comprises a data sampling and signal conditioning module, an A/D (Analog/Digital) conversion module, a transmitting main control unit and a transmitting unit signal conversion module; each receiving unit comprises a receiving unit signal conversion module, a receiving unit signal conditioning module, a receiving main control unit and a memory output module. The device can perform digital coding on multi-channel analog sampling and switch sampling, and transmits through the isolated transmission mediums; each receiving unit can be connected with a plurality of the transmitting units for simultaneously decoding. The multi-channel isolated high-speed intelligent transmitting-receiving device has the advantages of prominent high-reliable electrical isolation performance, instantaneity and intelligent performance.