13results about How to "Improve electrical isolation" patented technology

The invention relates to the technical field of electric energy routers, in particular to a power distribution area flexible mutual aid system based on an electric energy router, and the system is characterized in that a DC bus in a flexible mutual aid device is connected with an external power distribution area through a plurality of bidirectional DC / AC ports, and is used for completing electrical coupling and power intercommunication; the plurality of bidirectional DC / AC ports are connected with the direct current bus in parallel, the direct current bus is connected with an energy storage port and a photovoltaic port, the energy storage port is communicated with an external energy storage device, the photovoltaic port is communicated with an external photovoltaic device, and the flexible mutual aid device is communicated with an external power grid dispatching through a controller. According to the invention, normalized flexible interconnection between feeder lines is realized through the flexible mutual aid device, potential safety hazards caused by frequent displacement of a conventional switch based on an interconnection switch are avoided, the control flexibility and rapidity of the power distribution network are improved, and the power distribution network has the advantages of open-loop operation and closed-loop operation at the same time.

The invention discloses a semiconductor device, a preparation method, a chip and electronic equipment, and relates to the technical field of semiconductors, the semiconductor device comprises a plurality of high-electron-mobility transistors and isolation grooves, the isolation grooves are arranged between adjacent first high-electron-mobility transistors and second high-electron-mobility transistors, and the first high-electron-mobility transistors and the second high-electron-mobility transistors are adjacent to the first high-electron-mobility transistors and the second high-electron-mobility transistors. The isolation groove at least penetrates through the layer where the ohmic contact layers of the high-electron-mobility transistors are located, the ohmic contact layers of the first high-electron-mobility transistor and the second high-electron-mobility transistor are separated, and electrical isolation is achieved. Moreover, a film layer is arranged between the bottom wall of the isolation groove and the substrate, the film layer is also arranged between the barrier layer and the substrate, the film layer below the isolation groove comprises an ion implantation region, and the ohmic contact layer is further electrically isolated. Therefore, the isolation groove and the ion implantation region are mutually combined to realize electrical isolation, the isolation difficulty of a subsequent device is effectively reduced, isolation high-temperature failure is avoided, and the isolation stability of the device is improved.

The application relates to a high-voltage pulse electric field ablation device and method, and belongs to the technical field of medical instruments, which solves the problem of long pulse edge and pulse width generated by an existing high-voltage fast switch. The device comprises a high-voltage output module, a capacitor and a control unit. The high-voltage output module comprises a first branch, an additional branch and a second branch which are connected in parallel between a direct-current high-voltage power supply and a grounding end in sequence. The first branch comprises first and second power switches which are connected in series. The second branch comprises fifth and sixth power switches which are connected in series. The additional branch comprises third and fourth power switches which are connected in series. The capacitor is connected between a first node between the first and second power switches and a second node between the third and fourth power switches. The first to sixth power switches are opened and closed to generate a bipolar high-voltage pulse with picosecond or nanosecond rising and falling edges and nanosecond pulse width. The amplitude, rising time, falling time, frequency, pulse width, positive and negative pulse time difference and pulse number of the pulse can be adjusted. The device realizes super-fast pulse rising and falling edges and super-short pulse width.

The application discloses a three-dimensional memory device, comprising a substrate, a stack structure arranged on the substrate, and a memory string structure penetrating through the stack structure. The stack structure comprises a plurality of conductive layers and a plurality of dielectric layers arranged alternately. The memory string structure comprises a conductive pillar and a memory layer between the conductive pillar and the stack structure and surrounding the conductive pillar, wherein the memory layer comprises a plurality of first protrusions respectively filled in a plurality of first recesses at the junctions of the conductive layers and the dielectric layers. The application can improve the electrical isolation between memory cells and reduce the signal interference problem between adjacent memory cells during writing or reading.

This disclosure provides a method for fabricating a laser chip. An electrically isolated layer group comprising a first N-type InP layer, a second N-type InP layer, and a first active layer are sequentially grown on a substrate. A second active layer is grown outside a first position of the first active layer. First and second electrically isolated layers and a conductive layer are grown at the interface between the first and second active layers. Second and third P-type InP layers and a contact layer are sequentially grown on the first active layer, the conductive layer, and the second active layer. A second position of the contact layer is etched down to the third P-type InP layer. Both the first and second contact layers are etched down to the first N-type InP layer. A passivation layer is grown and etched down to the first and second contact layers and the first N-type InP layer. Positive and negative electrodes are grown. In this disclosure, the substrate is conductive, avoiding the problem of charge accumulation on the substrate surface leading to internal electric field distortion. The electrically isolated layer group prevents current from flowing from the second N-type InP layer into the substrate. The first N-type InP layer is conductive, enabling the positive and negative electrodes to conduct.

The application relates to a DNA self-assembly nano-floating gate type 3D NAND structure, which comprises a substrate, a periodic stack structure arranged on the substrate, the stack structure comprising a plurality of first insulating medium layers and nano-floating gate storage structures alternately stacked, a plurality of through holes penetrating through the stack structure, a center channel layer being arranged on the side wall of the through hole, and a center insulating medium layer being filled in the center channel layer; wherein the nano-floating gate storage structure comprises a tunneling medium layer contacting the center channel layer, a blocking medium layer wrapping the outside of the tunneling medium layer, and a gate word line metal located outside the blocking medium layer, and a carbon nanotube floating gate layer is arranged in the tunneling medium layer. The structure can significantly improve the storage density and size miniaturization ability, and greatly reduce the working voltage and driving power consumption.

A memory structure and a method for forming the same, wherein the memory structure includes: a substrate; a plurality of isolation layers located within the substrate; a plurality of floating gate structures located on the substrate, the isolation layers being located between adjacent floating gate structures; a barrier layer located on the surface of the floating gate structures; and a control gate located on the substrate, the control gate covering the plurality of floating gate structures, wherein a cavity is formed within the control gate between adjacent floating gate structures. The cavity within the control gate between adjacent floating gate structures increases the dielectric constant between adjacent floating gate structures, thereby improving the electrical isolation between adjacent floating gate structures and reducing crosstalk between adjacent floating gate structures.

The utility model discloses a packaging structure for a chip, which comprises an electric connection limiting frame, an electric connection clamping groove is arranged in the electric connection limiting frame, the electric connection clamping groove is arranged in four inner walls, the outer part of the electric connection clamping groove is communicated with a plurality of electric connection jacks, and the plurality of electric connection jacks are respectively arranged in four side walls of the electric connection limiting frame. Through the combination of the electric connection limiting frame and the lamination limiting frame, the modular packaging of the integrated chip is realized, the design facilitates the installation, replacement and expansion of the integrated chip, the flexibility and maintainability of the packaging are improved, the multi-layer lamination of the integrated chip can be realized through the increase and decrease of the lamination limiting frame, and the packaging efficiency is improved. The structural design is suitable for application scenes needing high integration, the packaging density and the space utilization rate are effectively improved, the connecting lines are etched in the connecting pole pieces, customized design can be carried out according to the connecting requirements of different types of integrated chips, and the compatibility and adaptability of the packaging structure to different chips are improved through the design.

This invention provides a frequency-to-analog safety barrier, comprising a voltage conversion circuit, a transformer coil drive circuit, a transformer, a first AC voltage rectification and filtering circuit, a frequency signal processing circuit, a NAMUR signal processing circuit, an NPNPNP signal processing circuit, a frequency processing circuit, an MCU control circuit, a TTL output interface, an isolation chip, a square wave processing circuit, a filtering circuit, a DC output circuit, and an alarm relay. The voltage conversion circuit is connected to the transformer via the transformer coil drive circuit. The transformer supplies power to the hazardous and safe zones via the first AC voltage rectification and filtering circuit. Multiple intrinsically safe terminals in the hazardous zone are connected to the frequency processing circuit via three signal processing circuits. The frequency processing circuit outputs to the MCU control circuit. The MCU output sequentially passes through the TTL interface, the isolation chip, the square wave processing circuit, and the filtering circuit to the DC output circuit. This invention achieves frequency signal to analog quantity conversion and safety isolation, increasing system stability.

The application relates to the technical field of solar cells, and provides a back contact cell, a cell assembly and a photovoltaic system. In the back contact cell, a groove is formed on a third region of a silicon substrate, the groove further comprises a first connecting region between the groove and a first region, a first doped layer is located on the first region, a second doped layer is located on a second region, and a third doped layer is located on the first connecting region. The third doped layer comprises a first body part and a first transition part between the first body part and the first doped layer and the first body part and the first doped layer. The doping concentration of a first doped element in the first doped layer is greater than or equal to 100 times the doping concentration of the first doped element in the first body part. In this way, the carrier recombination rate of the region near the groove can be reduced while achieving an excellent insulation isolation effect, the surface recombination loss is reduced, and the efficiency of the back contact cell is improved.

The embodiments of the present disclosure disclose a memory, a manufacturing method thereof and a memory system. The memory has a first region and a second region, and comprises: a first semiconductor layer comprising a first part and a second part arranged side by side along a first direction; wherein the first part is located in the first region, and the second part is located in the second region; along a second direction, the length of the first part is less than the length of the second part; each memory cell comprises a first transistor; wherein the first transistor is located in the first region, and the channel of the first transistor extends along the second direction; a peripheral circuit located in the second region and coupled to the memory cell array, comprising: at least two second transistors; at least one isolation structure penetrating through the second part along the second direction and located between two adjacent second transistors, for electrically isolating the two adjacent second transistors; wherein along the second direction, the length of the isolation structure is greater than the length of the channel of the first transistor.

The laser chip fabrication method and laser chip disclosed herein include a light-emitting region and an electro-absorption modulation region. The P-InP layer includes a first region, a second region, and a third region, with a second active region located below the third region. The first and second regions are exposed to the implanted ion beam, forming a first and a second electrically isolated region. The third region, protected by a mask, remains conductive, forming a first P-InP body layer. During ion implantation, the first and second metal layers act as masks for the first P-InP body layer, intercepting ion implantation and preventing ions from penetrating deep into the first P-InP body layer, thus maintaining its conductivity. The narrow linewidths of the first and second metal layers reduce the ion implantation width of the first P-InP body layer, resulting in a narrower linewidth first P-InP body layer, which is beneficial for improving the modulation rate and modulation bandwidth of the electro-absorption modulation region.