Double-depth shallow channel isolation groove and preparation method thereof

Abstract

The invention provides a double-depth shallow channel isolation groove and a preparation method thereof. The preparation method of the double-depth shallow channel isolation groove comprises the following steps: providing a substrate, and sequentially forming a hard mask layer and a graphical first photoresist layer on the substrate; taking the graphical first photoresist layer as a mask, etchingto form a first opening and a second opening, and then removing the first photoresist layer; forming a graphical second photoresist layer on the hard mask layer; taking the graphical second photoresist layer and hard mask layer as masks, etching to form a first part of a second isolation groove, and then removing the second photoresist layer; taking the hard mask layer as a mask, and etching to form the second part and the first isolation groove of the second isolation groove so that the first isolation groove of a photosensitive region and the second isolation groove of a logic region are formed at the same time. Thus, the electrical performance of the photosensitive device is improved, the STI electrical isolation performance is also improved, the process difficulty is reduced, and the process window is expanded.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a double-depth shallow trench isolation trench and a preparation method thereof. Background technique [0002] The shallow trench isolation (STI, Shallow Trench Isolation) process is one of the key processes in the formation of CMOS devices. As the device size continues to shrink, the thickness of the photoresist is limited, and the etching depth of STI is not greatly reduced. The photoresist cannot meet the thickness requirement of the STI etching mask layer, so after the 130nm technology node, the silicon nitride hard mask process is widely used in the prior art for STI etching. [0003] At the same time, CIS (CMOS Image Sensor, CMOS image sensor) products based on advanced technology platforms (<65nm) are currently hot spots in the field of chip manufacturing. Since the CIS chip has both a photosensitive area (Pixel) and a surrounding logic area (Logic), so that ...

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Problems solved by technology

[0004] However, in the traditional process of forming a double-depth STI structure, the performance of STI electrical isolation is low, and the electrical performance of the subsequently formed photosensitive device is poor.

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