310 results about "Channel isolation" patented technology

Two operation channels CH1 and CH2 of a bidirectional photothyristor chip 31 are disposed away from each other so as not to intersect with each other. In between a P-gate diffusion region 23 on the left-hand side and a P-gate diffusion region 23′ on the right-hand side on an N-type silicon substrate, and in between the CH1 and the CH2, a channel isolation region 29 comprised of an oxygen doped semi-insulating polycrystalline silicon film 35a doped with phosphorus is formed. Consequently, a silicon interface state (Qss) in the vicinity of the channel isolation region 29 on the surface of the N-type silicon substrate increases, so that holes or minority carriers in the N-type silicon substrate are made to disappear in the region. This makes it possible to prevent such commutation failure that when a voltage of the inverted phase is applied to the CH2 side at the point of time when the CH1 is turned off, the CH2 is turned on without incidence of light, and this allows a commutation characteristic to be enhanced.

A data center cooling solution providing techniques for using baffles, doors and roof sections to prevent warm air from being entrained into a cold aisle in a data center, wherein the data center generally contains an air cooling system and a raised floor structure. The raised floor structure is configured to deliver cool air into the data center through a plurality of grates and perforated tiles in the floor. Electronic equipment racks are disposed around the grates and perforated tiles, such that the front faces of the equipment racks face the grates and perforated tiles. A collection of baffles, doors or roof sections inhibit the mixing of the cool air delivered by the air cooling system and the warm air exhausted by the electronic equipment.

Selectable attenuators are used in the reference and test paths of a VNA, with attenuation automatically inserted or deleted when the Device Under Test (DUT) attenuation reaches predetermined thresholds. Attenuation in the reference channel is removed when the signal in the test channel is sufficient to overcome the leakage of the reference channel. Additionally, attenuation is removed from the test channel when the reference channel has a high attenuation inserted to further increase the difference between the leakage reference signal and the reduced test channel signal thus allowing lower isolation requirements on the two (or more) receiving channels.

The invention combines systems and methods for heat containment and cold air isolation for managing airflow and temperature in data centers. The data center contains at least two rows of cabinets containing heat-generating equipment and arranged to form a cold aisle and a hot aisle. The data center system includes panels or doors at both ends of the cold aisle and an optional cover over the cold aisle to inhibit cooled air supplied by an air conditioning system from exiting the cold aisle and inhibit air warmed by the heat-generating components from entering the cold aisle. A chimney coupled to the top, rear, or top and rear of the cabinets is configured to exhaust the warmed air into a region above the rows of cabinets. The chimneys may be ducted to a plenum or suspended ceiling or to the intake of the air conditioning system. Baffles and / or fans may be included in the chimneys, ducts, and / or plenums to control the air pressure. The invention may also include one or more data center air conditioning units, and each air conditioning unit may be configured to service one or more rows of cabinets. Alternatively, or in addition, cool air may be supplied by the building's air conditioning system.

The present invention provides for an interface mechanism in a bio-separation instrument that makes interface connections to a multi-channel cartridge. The interface mechanism precisely positions the cartridge in relation to the support elements in the instrument (e.g., high-voltage, gas pressure, incident radiation and detector), and makes automated, reliable and secured alignments and connections between various components in the cartridge and the support elements in the supporting instrument. The interface mechanism comprises pneumatically or electromechanically driven actuators for engaging support elements in the instrument to components on the cartridge. After the cartridge has been securely received by the interface mechanism, the connection sequence is initiated. The interface provides separate high voltage and optical connections for each separation channel in the cartridge, thus providing channel-to-channel isolation from cross talk both electrically and optically.

Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.

One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Non-volatile storage in which program disturb is reduced by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.

The invention is applied to the field of serial port communication, and provides an automatic switching circuit for an RS232 interface and an RS485 interface and a serial port liquid crystal display module. The automatic switching circuit comprises a first photoelectric isolation circuit, a second photoelectric isolation circuit, a serial port state detection circuit, a power control circuit, a data transmission and reception control circuit, an RS485 transceiver and a common channel isolation circuit. In the embodiment of the invention, when the automatic switching circuit adopts a common data display channel for the RS232 interface and the RS485 interface to communicate with a master control micro control unit (MCU), and the common channel is completely isolated, so that the problem of mutual interference of the common channel is solved; the serial port state detection circuit judges the current working conditions of the RS232 interface and the RS485 interface, and is matched with the power control circuit to timely cut off power supplied to the RS485 interface, so that the problem of possible interference when the RS232 interface and the RS485 interface are simultaneously connected can be solved; and in addition, a photoelectric isolation method is adopted to prevent surge and lightning, so that the automatic switching circuit can be well applied to industrial application places.

The invention discloses a multi-channel sinusoidal signal generator and a method for generating multi-channel sinusoidal signals. By the adoption of the multi-channel sinusoidal signal generator and the method for generating the multi-channel sinusoidal signals, the sinusoidal signals of tens of or hundreds of channels can be directly generated, and the amplitude, the frequency, and the initial phase of each signal can be digitally set; synchronization of the signals of all channels or signals of a plurality of channels can be achieved, and phase difference can be set between every two same-frequency signals. A waveform generation circuit is composed of a single programmable logic device and multiple analog units. Each analog unit is controlled by an amplitude control signal, a phase frequency control signal and a public fundamental frequency square signal. At least 2N+1 control lines, for driving the N channel analog units, of the programmable logic device are arranged. According to the multi-channel sinusoidal signal generator, a storage, a DAC and an analog multiplier are not applied to the waveform generation circuit, and only one programmable logic device, N analog multi-channel switches, N four-operational-amplifiers and N dual-operation-amplifiers are adopted, so that the hardware cost is low, and an analog circuit is simple. The multi-channel sinusoidal signal generator and the method for generating the multi-channel sinusoidal signals are suitable for application occasions requiring one or more characteristics such as a large number of channels, channel synchronization, and channel isolation.

The invention provides a router fault-tolerant method based on fault channel separation detection in a NoC. A fault channel separation detection technology is used for detecting the channel fault in a router, so that fault detection does not influence normal data transmission; a Buffer with a recovery pointer is used for temporarily storing transmitted data and for retransmitting wrong data in a fault channel so as to reduce the fault-tolerant spending of the router; meanwhile, a redundancy channel is additionally arranged to be used for transmitting the data in a permanent fault channel. According to the router fault-tolerant method based on fault channel separation detection in the NoC, a low hardware cost is used, normal data transmission can be conducted during fault detection, so that network delay is lowered, and the network throughput is improved.

A process for preparing shallow channel isolation (STI) structure includes such steps as providing substrate, generating pad oxide layer and mask layer on the substrate, removing part of pad oxide layer, mask layer and substrate to form a channel in the substrate, chemical gas-phase deposition by high-density plasma with high etching / deposition ratio to depositing insulating layer, depositing again with low etching / deposition ratio, removing the insulating layer except the channel, and removing mask layer and oxide layer.

The invention discloses a detecting structure, a forming method and a detecting method. The detecting structure comprises a plurality of polygon active areas, a shallow channel isolation structure, an ion mixing area, a gate oxide layer, a polycrystalline silicon layer, a dielectric layer, a first conducting plug, a second conducting plug, a first metal layer and a second metal layer, wherein the polygon active areas are positioned in a first area of a semiconductor substrate; the shallow channel isolation structure is positioned in the first area of the semiconductor substrate and is formed surrounding the active areas; the ion mixing area is positioned in a second area of the semiconductor substrate; the gate oxide layer covers the active area and the shallow channel isolation structure; the polycrystalline silicon layer is positioned on the surface of the gate oxide layer; the dielectric layer covers the semiconductor substrate and the polycrystalline silicon layer; the first conducting plug is positioned on the surface of the polycrystalline silicon layer; the second conducting plug is positioned on the surface of the ion mixing layer, and the first metal layer and the second metal layer are positioned on the surface of the dielectric layer. According to the detecting structure disclosed by the invention, whether a corner of the active area of the detecting structure is damaged or not can be detected by measuring the puncture voltage of the gate oxide layer for one time, and thus whether a corner of an active area of a to-be-detected semiconductor device is damaged or not can be judged.