Semiconductor relay module, comprising: a first
semiconductor relay (10), including a first input circuit (11) and a first output circuit (12); a second
semiconductor relay (20), including a second input circuit (21) and a second output circuit (22); a third
semiconductor relay (30), including a third input circuit (31) and a third output circuit (32); a fourth semiconductor relay(40), including a fourth input circuit (41) and a fourth output circuit (42); a fifth semiconductor relay (50), including a fifth input circuit (51) and a fifth output circuit (52); a sixth semiconductor relay (60), including a sixth input circuit (61) and a sixth output circuit (52); a
package (70) designed to accommodate the first
solid-state relay (10), the second
solid-state relay (20) and the third
solid-state relay (30) in the
package (70); a first input terminal (71), a second input terminal (72) and a third input terminal (73) arranged in the
package (70), wherein the first input terminal (71), the second input terminal (72) and the third input terminal (73) are each partially exposed to the outside of the package (70); a first output terminal (81), a second output terminal (82), a third output terminal (83), a fourth output terminal (84) and a fifth output terminal (85) arranged in the package (70), wherein the first output terminal (81), the second output terminal (82), the third output terminal (83), the fourth output terminal (84) and the fifth output terminal (85) are each partially exposed to the outside of the package (70); a first connecting line (80) for connecting the first output circuit (12) and the second output circuit (22) in the package (70), a second connecting line (86) for connecting the fourth output circuit (42) and the fifth output circuit (52) in the package (70), wherein the first input circuit (11) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the second input circuit (21) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the third input circuit (31) is connected to the first input terminal (71) or the second input terminal (72) in the package (70), wherein the third input circuit (31) is connected to the first input terminal (71) in the package (70), wherein the fourth input circuit (41) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the fifth input circuit (51) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the sixth input circuit (61) is connected to the first input terminal (71) or the second input terminal (72) in the package (70), wherein the sixth input circuit (61) is connected to the third input terminal (73) in the package (70), wherein the first output circuit (12) is connected to the first output terminal (81) and the first connecting line (80) in the package (70), wherein the second output circuit (22) is connected to the second output terminal (82) and the first connecting line (80) in the package (70), wherein the third output circuit (32) is connected to the third output terminal (83) and the first connecting line (80) in the package (70), wherein the fourth output circuit (42) is connected to the fourth output terminal (84) and the second connecting line (86) in the package (70), the fifth output circuit (52) is connected to the fifth output terminal (85) and the second connecting line (86) in the package (70); and the sixth output circuit (62) is connected to the third output terminal (83) and the second connecting line (86) in the package (70); wherein in a first state in which current flows through the first input terminal (71) and the second input terminal (72) without flowing through the third input terminal (73), the first output circuit (12) and the second output circuit (22) are designed to be switched on, the third output circuit (32) is designed to be switched off, the first output terminal (81) and the second output terminal (82) are designed to be electrically connected to each other, and the first connecting line (80) and the third output terminal (83) are designed to be electrically disconnected from each other, and wherein in a second state in which current flows through the third input terminal (73) without flowing through the first input terminal (71) and the second input terminal (72), the first output circuit (12) and the second output circuit (22) are designed to be switched off, the third output circuit (32) is designed to be switched on, the first output terminal (81) and the second output terminal (82) are designed to be electrically disconnected from each other, and the first connecting line (80) and the third output terminal (83) are designed to be electrically connected to each other.