5results about How to "Avoid parasitic effects" patented technology

The invention relates to a high-power microwave amplitude limiting protection circuit with high power capacity, and belongs to the field of strong electromagnetic pulse protection. The three-level PIN pair transistor amplitude limiting circuit and the eight-order hairpin type microstrip filter circuit are carried on the dielectric substrate, the first blocking capacitor is connected between the input end of the amplitude limiting protection circuit and the three-level PIN pair transistor amplitude limiting circuit, and the second blocking capacitor is connected between the three-level PIN pair transistor amplitude limiting circuit and the eight-order hairpin type microstrip filter circuit. The output end of the amplitude limiting protection circuit is connected with the eight-order hairpin type microstrip filter circuit. The invention has the advantages of large power capacity, small peak leakage, small starting limit level and low amplitude limiting level, can effectively suppress interference signals coupled into the receiving end of the wireless communication equipment by high-power microwaves, and improves the anti-interference capability of the wireless communication equipment under the radiation of the high-power microwaves.

The invention provides a transistor circuit and a manufacturing method thereof, and belongs to the field of semiconductor devices. The transistor circuit includes: a first transistor and a second transistor; the first transistor and the second transistor comprise a common substrate, and a channel layer and a barrier layer which are sequentially stacked on the substrate; the barrier layer is provided with a groove extending into the channel layer; the first transistor further comprises a first dielectric layer, a first source electrode, a first drain electrode and a first grid electrode; the second transistor further comprises a second dielectric layer, a second source electrode, a second drain electrode and a second grid electrode; the first dielectric layer covers the bottom of the groove, the second dielectric layer is located on the barrier layer, and the first source electrode, the first drain electrode, the second source electrode and the second drain electrode penetrate through the barrier layer and are connected with the channel layer; the groove is located between the first source electrode and the first drain electrode, and the second dielectric layer is located between the second source electrode and the second drain electrode; the first gate is located in the groove, the second gate is located on the second dielectric layer, the first source is electrically connected with the second gate, and the first drain is electrically connected with the second source.

The application relates to a full GaN power electronic monolithic integrated circuit and a preparation method thereof, which comprises, from bottom to top, an insulating composite substrate, an AlN layer, a Si layer, a GaN / AlGaN buffer layer, a GaN layer and an AlGaN layer; a 2DEG layer is formed between the GaN layer and the AlGaN layer; the AlGaN layer is etched, a p-GaN layer is grown; a p-GaN layer gate portion is etched and filled with a passivation layer, and a gate metal is grown; source metal and drain metal are respectively grown on both sides of the p-GaN layer gate area; a deep groove is arranged between a driving circuit and a low-voltage tube, between a high-voltage tube and the low-voltage tube, and a medium is filled in the deep groove; and the full GaN power electronic monolithic integrated circuit is obtained through a top via and an interconnection process. The application can realize high efficiency and low power consumption, low parasitic effect, and reduce leakage current and switching loss.

The invention relates to a non-switching composite dual-mode large dynamic reconfigurable power amplifier and electronic equipment. The amplifier comprises an input end dual-mode reconfigurable switching unit, an output end dual-mode reconfigurable switching unit, a high-power amplifier and a low-power amplifier, wherein the target states of the input end dual-mode reconfigurable switching unit and the output end dual-mode reconfigurable switching unit are equivalently simulated by controlling the grid voltage and the drain voltage of the high-power amplifier and the low-power amplifier, the power of the radio frequency input is amplified to obtain the radio frequency output, and the target states comprise the opening state and the closing state. Under the condition that a switch structure is not adopted, composite dual-mode reconfiguration of frequency reconfiguration and power reconfiguration is achieved, and insertion loss and parasitic effect caused by introduction of a switch in the prior art are avoided.

The invention provides a high-voltage bidirectional PNP electrostatic protection device and a preparation method thereof. The high-voltage bidirectional PNP electrostatic protection device comprises a P-type substrate, an N-type buried layer in the P-type substrate and a bidirectional PNP device structure on the N-type buried layer, the bidirectional PNP device structure comprises a first P-type epitaxial layer, a first high-voltage N well, a second P-type epitaxial layer, a first P-type well arranged in the first P-type epitaxial layer, a first N-type well arranged in the first P-type epitaxial layer, the first high-voltage N well and the second P-type epitaxial layer, and a second P-type well arranged in the second P-type epitaxial layer, wherein the first P-type epitaxial layer, the first high-voltage N well and the second P-type epitaxial layer are sequentially laid on the N-type buried layer. The M P + injection regions are sequentially arranged in the first P-type well at intervals; the M P + injection regions are sequentially arranged in the second P-type well at intervals; m is a natural number greater than or equal to 2. The bidirectional ESD protection circuit is suitable for a high-voltage port needing bidirectional ESD protection, the single-direction conduction resistance is low, the ESD current discharge capacity is high, and the layout area and the bare chip cost are saved; and the parasitic effect is also reduced.