Dielectrically isolated integrated circuit extending wafer and preparation method thereof

A dielectric isolation and integrated circuit technology, applied in the field of dielectric isolation epitaxial wafers and its preparation, can solve the problems of parasitic radiation resistance, poor isolation performance, and no performance, and achieve shortening of high temperature time, high temperature resistance and radiation resistance Performance improvement, the effect of improving circuit performance
CN101425522AInactive Publication Date: 2009-05-06TIANSHUI HUATIAN MICROELECTRONICS
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
TIANSHUI HUATIAN MICROELECTRONICS
Publication Date
2009-05-06
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention mainly relates to a dielectric isolation epitaxial wafer and a preparation method thereof. The N-shaped / P-shaped dielectric isolation integrated circuit epitaxial wafer comprises N-shaped / P-shaped monocrystalline silicon (1) with backing material. A sandwich oxide layer (2) is arranged on the monocrystalline silicon (1). The invention is mainly characterized in that the dielectric isolation epitaxial wafer further comprises an N-shaped / P-shaped silicon epitaxial layer (6); a buried layer (3) is arranged in the silicon epitaxial layer (6); the silicon epitaxial layer (6) is divided into mutually-insulating isolation blocks by silicon dioxide (5), polysilicon (4) and the sandwich oxide layer (2). The invention also discloses a preparation method of the N-shaped / P-shaped dielectric isolation integrated circuit epitaxial wafer. The preparation method comprises the following steps: preparing a silicon chip on an insulating body, preparing the buried layer with low resistance, extending outwardly, notching, growing the silicon dioxide and the polysilicon, and polishing. Because the high temperature time is shortened greatly during the preparation, the invention has the advantages of more complete crystal structure and more accurate process control, and can be used for manufacturing circuits with high performance and special requirements.
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Description

Technical field:

[0001] The invention mainly relates to a dielectric isolation epitaxial wafer and a preparation method thereof. It belongs to the technical field of integrated circuits. Background technique:

[0002] In the manufacture of bipolar analog and digital integrated circuits, a monolithic PN junction isolation epitaxial wafer method is generally used. Except for the vertical PNP tube of the output substrate, the other PNP tubes can only be made into horizontal PNP tubes, and the performance is not as good as that of vertical PNP tubes. In the case of higher reliability requirements and harsher working environment conditions, the circuits manufactured by the PN junction isolation epitaxy method are limited to a certain extent, and the performance of the analog integrated circuits manufactured by the dielectric isolation epitaxial wafer is obviously better than the former. With the development of human beings to deep space exploration, the requirements for radiati...

Claims

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