62 results about "Junction depth" patented technology

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The invention belongs to the technical field of solar cell manufacturing, and provides a step temperature cycle propulsion boron diffusion process and application thereof. The boron diffusion technology comprises the steps that a silicon wafer is placed in boron diffusion equipment, pre-oxidation, pre-deposition and stepped temperature circulation boron diffusion propelling are sequentially carried out on the silicon wafer, and the stepped temperature circulation boron diffusion propelling procedure comprises an initial stage, a middle stage and a final stage which are sequentially carried out. A circulation mode of heating oxygen-free boron expansion and pushing junction and then cooling oxygen-filled boron expansion and pushing junction is adopted in each stage for multiple times of circulation, and the heating temperature and the cooling temperature of each stage are optimized, so that a boron expansion doping layer is formed on the surface of the silicon wafer. According to the boron diffusion process, the oxidation temperature can be reduced, the concentric circle defect can be eliminated, the junction depth and the surface doping concentration of boron diffusion doping can be increased, the uniformity of boron diffusion doping can be improved, the FF, Jsc, Uoc and Eta of the battery can be further improved, the thermal budget can be reduced, and the service life of equipment can be prolonged.

The invention belongs to the related technical field of semiconductor doping, and discloses a method for acquiring a second harmonic signal of non-uniform ion implantation doping concentration and an application of the second harmonic signal of the non-uniform ion implantation doping concentration. Determining refractive indexes and absorption coefficients of different depth positions of the ion implantation doping sample under a specific laser wavelength based on an optical property distribution model in the ion implantation doping sample; s2, calculating fundamental frequency light electric field distribution in the doped sample based on the obtained refractive index and absorption coefficient; s3, calculating the polarization intensity and effective second-order polarizability of the non-uniform doped ion implantation sample based on the simplified bond hyperpolarizability model and the fundamental frequency photoelectric field distribution; and S4, calculating far-field second harmonics of the corresponding layers at a predetermined observation angle based on the obtained polarization intensity or effective second-order polarizability of each layer, and carrying out integration on the far-field second harmonics corresponding to all layers to obtain the total intensity of the second harmonics of junction depth far-field radiation. According to the invention, the problem that the measurement sensitivity and repeatability are reduced is solved.

The invention discloses a planar SiC MOS (Metal Oxide Semiconductor) gate-controlled thyristor device based on an epitaxial surface and a manufacturing method thereof, effectively avoids the problem of using a triple ion implantation process traditionally by ingeniously introducing an n-type epitaxial layer, and utilizes the advantages of high growth speed, low material defect, good process stability and the like of an epitaxial growth technology to improve the performance of the device. The semiconductor layer with lower surface defect density can be obtained, the mobility of channel carriers is effectively improved, and the working performance of the device is improved. By introducing the n-type epitaxial region, the separation design of the p-type ion implantation well region and the n-type ion implantation well region is realized, the doping concentration can be controlled more accurately by the surface structure of the epitaxial layer, and the deeper junction depth of the p-type ion implantation well region and the deeper base region width of the n-type ion implantation well region can be controlled and realized. The design difficulty that the ion implantation junction depth of the device needs to exceed 1 [mu] m is reduced, and the problem that the original lattice structure of the material is damaged by SiC high-temperature ion implantation is avoided.

The invention discloses a Schottky diode and a preparation method thereof, the Schottky diode comprises a heavily doped N-type substrate layer and a lightly doped N-type epitaxial layer formed on the upper surface of the heavily doped N-type substrate layer, the upper part of the lightly doped N-type epitaxial layer is provided with a groove structure, the groove structure is filled with doped polycrystalline silicon, the doped polycrystalline silicon is polycrystalline silicon doped with P-type impurities, and the doped polycrystalline silicon is doped with P-type impurities. Doped polycrystalline silicon is used as a solid phase diffusion source, and solid phase diffusion is carried out on the doped polycrystalline silicon to diffuse P-type impurities to the lightly doped N-type epitaxial layer, so that P-type regions are formed on the side wall and the bottom of the groove structure. According to the Schottky diode and the preparation method thereof, the P-type region is formed on the side wall and the bottom of the groove structure, the P-type region and the lightly doped N-type epitaxial layer form the depletion region, a good three-dimensional heat dissipation channel is formed, the heat dissipation burden is reduced, the P-type region is formed through solid-phase diffusion, and compared with ion implantation, the junction depth is easier to control.

The application provides a method for detecting the effective junction depth of a tellurium-cadmium-mercury chip PN junction, and belongs to the technical field of semiconductors. The method comprises the following steps: selecting a tellurium-cadmium-mercury chip which has been formed through an ion implantation and annealing junction process and has been passivated; dividing the ion implantation area of the tellurium-cadmium-mercury chip into multiple regions, removing the passivation layer in each region and part of the ion implantation area below the passivation layer, and forming multiple contact holes arranged in a preset depth gradient; growing a metal electrode on each contact hole; measuring the voltage-current curve of each metal electrode at different etching depths; and determining the corresponding PN junction depth as the effective junction depth of the tellurium-cadmium-mercury chip when the voltage-current curve changes from a Schottky curve to a linear curve. The application is the same as the original chip manufacturing process of tellurium-cadmium-mercury, can be applied to the process production process of a tellurium-cadmium-mercury infrared detector, and can monitor the effective junction depth of the tellurium-cadmium-mercury after ion implantation in real time.

Structures and formation methods of a semiconductor device are provided. The method includes forming a first dummy gate structure across a first fin in a first transistor region of a semiconductor substrate and a second dummy gate structure across a second fin in a second transistor region of the semiconductor substrate. The method also includes selectively introducing atomic or ionic species into the second fin on opposite sides of the second dummy gate structure and etching portions of the first and second fins, so as to form first and second recesses. Each recess is in the respective fin on a side of the respective dummy gate structure. The first recess has a different depth than the second recess. The method further includes forming first and second source / drain features in the first and second recesses, respectively.

This invention discloses a method, substrate, and system for detecting laser beam-induced current in the PN junction region profile of an InGaAs photodetector, belonging to the field of semiconductor optoelectronic device characterization technology. The method includes: cleaving a chip with completed front-side processing along the natural cleavage surface of InP to obtain a smooth profile; fixing the chip with the profile facing upwards onto a composite sapphire bonding substrate, and extracting electrodes through conductive silver paste and ultrasonic bonding; performing a two-dimensional step-scan of the profile using a 900-1100nm laser, simultaneously acquiring photocurrent signals to obtain a two-dimensional photocurrent distribution map of the profile; and quantitatively extracting junction depth, lateral diffusion width, and uniformity parameters based on the photocurrent peak position. This invention can directly obtain the longitudinal two-dimensional electrical activity distribution of the PN junction region, effectively avoiding interference between the surface passivation layer and the InP cap layer, and achieving a visual assessment of junction depth, lateral diffusion, and defects, providing a realistic and efficient detection method for device process optimization.

According to the silicon-based PIN photodiode, the manufacturing method and the electronic device provided by the invention, the FZ single crystal is adopted as the substrate, and the doped region is formed in an ion implantation and annealing mode, so that the junction depth and the concentration can be effectively controlled. And thinning the silicon wafer by adopting a Taiko back thinning process. The photosensitive area adopts a shallow junction and deep junction combined structure, the shallow junction can increase the blue light absorption rate, and the deep junction forms ohmic contact. The anti-reflection layer adopts a silicon dioxide and silicon nitride double-layer structure, so that the surface stress of silicon / silicon nitride can be effectively relieved, and the reliability is improved. The cut-off region N + and the back N + can reduce dark current, and back metallization can form a back cathode.

The invention discloses a channel mobility testing method, a channel mobility testing structure and a manufacturing method of the channel mobility testing structure. The channel mobility test method comprises the following steps: providing a semiconductor device; determining the resistance between the source electrode and the drain electrode of each semiconductor device by applying a test voltage to the source electrode, the drain electrode and the gate electrode structure of at least two different semiconductor devices; wherein the junction depths of the JFET regions of at least part of the semiconductor devices in the at least two different semiconductor devices are different; the junction depth of the JFET region is the size of the JFET region in the direction from the first surface to the second surface; and determining the channel mobility of the semiconductor device according to the resistance between the source electrode and the drain electrode of each semiconductor device and the junction depth of the JFET region of each semiconductor device. According to the embodiment of the invention, the measurement of the channel field effect mobility can be realized, the measurement mode is simple, and the measurement efficiency is high.

The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device based on a SiC material and a manufacturing process of the semiconductor device. The device comprises an N + type SiC substrate, an N-type composite buffer layer which is arranged on the substrate and has a concentration gradient, an N-type drift region which is arranged on the buffer layer, and an active region which is composed of a first conduction type region and a second conduction type ion implantation region. The innovation lies in that a composite buffer layer structure is adopted to effectively suppress dynamic avalanche and optimize the reverse recovery characteristic, and meanwhile, a composite structure of a junction termination extension region and a field limiting ring with shallower junction depth is integrated in a terminal region, so that the process complexity is simplified on the premise of ensuring high breakdown voltage. According to the manufacturing process, impurity activation of the active region and the terminal region is synchronously completed through two times of ion implantation and one time of high-temperature annealing, and the manufacturing process is completely compatible with an existing SiC plane process platform. The device realizes excellent compromise between reverse recovery charge and forward voltage drop, and has the characteristics of superspeed, soft recovery, low loss and high reliability.

The invention relates to the field of photo-transistors, in particular to a high-CTR and high-speed photo-transistor based on layout optimization and a manufacturing method thereof.The high-CTR and high-speed photo-transistor comprises a semiconductor substrate, and an N-type epitaxial layer, a P-type base region and an N-type emitter region are sequentially formed on the semiconductor substrate; the P-type base region comprises a photoelectric sensing region and a base electrode main body which are independently arranged, the photoelectric sensing region is used for receiving optical signals and generating current carriers, the base electrode main body and the N-type emission region form a PN junction, and the node depth and the doping concentration of the base electrode main body can be independently adjusted according to beta value design requirements; the photoelectric sensing area and the base electrode main body are independently arranged, the section depth and the doping concentration of the base electrode main body can be flexibly adjusted according to beta value design, the problem that the section depth of a base electrode in a traditional shared structure is limited by photoelectric conversion efficiency is avoided, CTR is obviously improved, parameter stability is higher, and production efficiency is improved.

The application relates to the technical field of semiconductors, in particular to a SiC JFET device with improved avalanche capability and a manufacturing method thereof. The source region and the gate region are simultaneously arranged in a groove, and the depth of the second-type doped region of the source region is different from that of the second-type doped region of the gate region, wherein the junction depth of the second-type doped region of the source region is deeper than that of the second-type doped region of the gate region, so that the maximum electric field is at the junction edge of the second-type doped region of the source region in the off state, thereby making the avalanche current enter the source electrode through the ohmic contact of the source region without passing through the gate electrode, and the reliability of the avalanche is ensured.

The present disclosure relates to a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: forming a hard mask on a main surface of a wafer; performing active region photolithography and etching, and removing the hard mask at a position where a field oxide layer needs to be formed; forming the field oxide layer; forming a patterned photoresist layer on the main surface, wherein the photoresist layer covers a position where no drift region needs to be formed; and performing drift region implantation by using the photoresist layer as an implantation blocking layer, wherein ions implanted during drift region implantation pass through the hard mask and the field oxide layer and enter the wafer. In the present disclosure, during drift region implantation, the implanted ions at the edge of the field oxide layer are blocked by using the hard mask, so as to avoid excessive PN junction depth and excessively high ion doping concentration at this position. Rapid depletion of the implanted ions in a JFET region at this position is achieved, thereby reducing the electric field strength at this position, and optimizing and improving the voltage withstand and reliability of the device.

The application relates to a semiconductor device structure and a preparation method thereof, which comprises the following steps: a substrate structure; an epitaxial structure of a first conductive type on the front surface of the substrate structure; a groove structure comprising a first groove and a second groove; a first ion implantation region of a second conductive type in the epitaxial structure and below the bottom of the first groove; a second ion implantation region of the second conductive type in the epitaxial structure and below the bottom of the second groove; an ohmic contact layer on the bottom of the first groove; and a first electrode in the first groove, in the second groove and on the exposed surface of the epitaxial structure away from the substrate structure. The semiconductor device structure of the application adopts a groove type structure, solves the problem of shallow ion implantation depth of the second conductive type in the epitaxial structure, increases the junction depth of a PN junction, improves the shielding capacity of the PN junction to the electric field of a Schottky contact surface during reverse blocking, and improves the reverse recovery speed.

An insulated gate bipolar transistor and a preparation method thereof, and an electronic device. The insulated gate bipolar transistor includes: a drift region; an electrode structure on one side of the drift region; and an electric field stop layer arranged on one side of the drift region away from the electrode structure. The electric field stop layer includes a first sublayer and a second sublayer laminated together. The first sublayer is arranged close to the drift region. A junction depth of the first sublayer is greater than a junction depth of the second sublayer. A peak value of a doping concentration of the first sublayer is less than a peak value of a doping concentration of the second sublayer. A slope of a doping concentration curve of the first sublayer is less than a slope of a doping concentration curve of the second sublayer.

The application provides a TOPCon cell, comprising: a single crystal silicon wafer; an inner expansion layer arranged on the back surface of the single crystal silicon wafer; a doped polysilicon layer arranged below the inner expansion layer; the doped polysilicon layer comprises: a first doped polysilicon region and a second doped polysilicon region, the doping concentration of the first doped polysilicon region is higher than that of the second doped polysilicon region; the inner layer comprises: a first inner expansion region and a second inner expansion region, the position of the first inner expansion region corresponds to the position of the first doped polysilicon region, and the junction depth of the first inner expansion region is greater than that of the second inner expansion region. The TOPCon cell provided by the application has a specific structure, which can ensure the thickness and concentration of the doped polysilicon in the metal contact area, avoid the destruction of the tunneling oxide layer in the slurry sintering process, reduce the recombination current and the contact resistance, and at the same time, reduce the light parasitic absorption of the non-metal area, especially the free carrier absorption.

A pixel includes a semiconductor substrate, a photodiode region, a floating diffusion region, and a dielectric layer. The substrate has a top surface that forms a trench, the trench is lined by the dielectric layer, and has a trench depth relative to a planar region of the top surface. The photodiode region is in the substrate and includes a bottom photodiode portion under the trench and a top photodiode portion adjacent the trench, the top photodiode portion abutting the bottom photodiode portion and extending toward the planar region to a photodiode depth that is less than the trench depth. The floating diffusion region is adjacent the trench and has a junction depth that is less than the trench depth. A top region of the dielectric layer is between the planar region and the junction depth. A bottom region of the dielectric layer is between the photodiode depth and the trench depth and is thicker than the top region.

The invention provides a three-dimensional magnetic field monitoring device and a manufacturing method thereof. The device comprises a horizontal Hall device arranged in a semiconductor substrate, at least one vertical Hall device and an isolation structure for isolating the horizontal Hall device and the vertical Hall device. Wherein the active region of the horizontal Hall device is a first doped region with a first conduction type, the active region of the vertical Hall device is a second doped region with the same conduction type, and the junction depth of the second doped region is greater than that of the first doped region. The invention further discloses a corresponding manufacturing method. The three-dimensional magnetic field monitoring module which is high in performance, low in noise and good in isolation can be economically and efficiently integrated on a single chip without adding additional photoetching steps by ingeniously utilizing the existing doping layers with different depths in a standard BCD process platform, and the three-dimensional magnetic field monitoring module has the advantages of being good in process compatibility, low in cost and high in integration degree.

The application discloses a metal silicide forming method, which comprises the following steps: providing a substrate, forming a gate dielectric layer on the substrate, forming a gate electrode on the gate dielectric layer, forming a side wall on the periphery of the gate electrode, and forming a heavily doped region in the substrate on both sides of the side wall; forming a first metal layer by sputtering deposition through a first target material, the first target material comprising nickel and platinum, and the first metal layer covering the exposed areas of the substrate, the gate dielectric layer, the gate electrode and the side wall; forming a second metal layer on the first metal layer by sputtering deposition through a second target material, the second target material comprising nickel and platinum, and the content of platinum in the second target material being higher than that in the first target material; and performing heat treatment to form metal silicide in the gate electrode and the heavily doped region. The first metal layer and the second metal layer are sequentially deposited on the substrate, the content of platinum in the target material used for depositing the first metal layer is less than that in the target material used for depositing the second metal layer, the silicon loss and the junction depth are reduced, and the reliability and yield of the device are improved.

This invention provides a method for treating the surface of silicon carbide, comprising growing an oxide layer on the surface of a silicon carbide substrate; depositing a doped layer on the oxide layer surface using an atomic layer deposition apparatus; and vacuum annealing the silicon carbide substrate containing the doped layer and oxide layer at a set vacuum level using an annealing furnace. This significantly reduces the interface state density between silicon carbide and the oxide layer, thereby improving the inversion channel electron mobility of silicon carbide power devices and avoiding any impact on the performance of the silicon carbide power devices. This invention uses an annealing furnace to perform high-temperature annealing on the silicon carbide substrate containing the doped layer and oxide layer, avoiding the introduction of new impurities during the annealing process, reducing defects in the oxide layer, improving the quality of the oxide layer, and simultaneously allowing precise control of the junction depth of phosphorus atom diffusion through temperature and time.

The invention belongs to the field of power semiconductors, and particularly relates to an asymmetric GCT chip which comprises a P + transparent emission anode, an N-base region, a P base region, a P + base region and an N + emission region partially embedded in the P + base region, or an N'buffer layer is arranged between the P + transparent emitting anode region and the N-base region; the center of the N + emitter region is provided with a groove, and the groove is filled with a cathode metal layer and is led out. According to the asymmetric GCT chip provided by the invention, a comb structure with a groove is adopted, under the same chip size, the effective area of a cathode is increased, the doping concentration of a P + base region below an N + emitter region is reduced, the opening performance of the chip is improved, the junction depth of a J3 junction is basically kept unchanged, and the turn-off capability is not reduced while the through-current capability is improved.

The invention relates to a semiconductor device, in particular to a high-reliability groove-type silicon carbide field effect transistor device and a preparation process thereof.The device comprises drain electrode metal and an N-type drain electrode, an N-type epitaxial layer is arranged on the N-type drain electrode to serve as a drift region of the device, a longitudinal groove is formed in the upper surface of the N-type epitaxial layer, and an insulating medium is arranged in the longitudinal groove; the periphery of the longitudinal groove is wrapped by a P-type well region, the P-type well region is located in the N-type epitaxial layer, metal silicide is arranged at the bottom of the longitudinal groove, the metal silicide makes contact with the P-type well region and is further connected with grid metal, a heavily-doped N-type source electrode and source electrode metal are further arranged on the surface of the N-type epitaxial layer, the source electrode metal makes contact with the metal silicide located on the upper surface of the N-type source electrode, and the P-type well region is located in the N-type epitaxial layer. A P-type buried layer is further arranged in the N-type epitaxial layer, and the junction depth of the P-type buried layer is larger than that of the P-type well region. According to the invention, the pinch-off voltage of the device cannot be gradually increased along with the increase of the leakage voltage, and the stability of the device under various voltages is improved.

The invention provides an ion implantation depth measuring method and device, and belongs to the field of semiconductor manufacturing. The method provided by the invention comprises the following steps: determining a first duration; determining a first etching time length and a second etching time length according to the first time length; performing etching for a second etching duration, and determining a first etching rate of the dielectric layer; performing etching for a first etching time length and a second etching time length, and determining the thickness change of the dielectric layer under each etching time length; according to the thickness change of the dielectric layer under each etching duration, determining whether the etching process corresponding to each etching duration corresponds to two different types of etching; if yes, the thickness of the injection layer is determined, and if not, the step of determining the first etching duration and the second etching duration according to the first duration is executed again. According to the technical field of semiconductor manufacturing, the method for measuring the junction depth by detecting the etching rate change caused by ion implantation solves the problems of high cost and low efficiency of the traditional technology.

The invention provides a preparation method and equipment of a battery emitter, relates to the field of semiconductor or photovoltaic material processing, and solves the technical problem of low battery efficiency caused by non-uniform temperature of the edge and the center of a silicon wafer in a traditional boron junction pushing process. The preparation method of the battery emitter comprises the following steps: under a heating condition, depositing a borosilicate glass layer on one side of an N-type silicon wafer in a first direction; under the condition of continuous cooling, protective gas is introduced into the process chamber, so that boron atoms in the borosilicate glass layer are pushed to enter the part, close to the borosilicate glass layer, of the N-type silicon wafer. As part of heat in the center of the N-type silicon wafer needs to be transmitted outwards through the edge, the cooling speed of the edge is higher than that of the center, the difference between the edge temperature and the center temperature is reduced, the speeds of boron atoms pushing junctions to the edge and the center are closer, the distribution difference of boron impurities in the edge and the center is reduced, the junction depth is more uniform, and the junction quality is improved. And the battery efficiency is improved.

This invention provides a method for achieving high sheet resistance uniformity in boron diffusion for TOPCon solar cells. The method includes sequential steps such as wafer loading, heating, vacuuming, pre-oxygenation, multi-step power supply, variable-temperature multi-step junction pushing, variable-pressure annealing, re-pressure, and wafer unloading. The variable-temperature multi-step junction pushing includes sequential oxygen-free and oxygen-containing junction pushing. The temperature of oxygen-free junction pushing is lower than that of oxygen-containing junction pushing, the time of oxygen-free junction pushing is shorter than that of oxygen-containing junction pushing, the furnace pressure during oxygen-free junction pushing is lower than that during oxygen-containing junction pushing, and the oxygen flow rate during oxygen-containing junction pushing is 18000-23000 sccm. This invention improves the uniformity of boron content distribution by introducing a variable-temperature multi-step junction pushing process that combines oxygen-free followed by oxygen-containing junction pushing with multi-step power supply and variable-pressure annealing. This results in a P+ emitter with lower surface doping concentration and shallower junction depth, while significantly improving the sheet resistance uniformity after boron diffusion, achieving high sheet resistance uniformity under high sheet resistance targets.

The application provides a kind of double-doped layer TOPCon cell structure and preparation method thereof, it is related to cell processing preparation technical field.The double-doped TOPCon cell structure includes monocrystalline silicon wafer, diffusion layer, passivation layer, front surface anti-reflection layer, front surface metal electrode are sequentially arranged in the front surface of monocrystalline silicon wafer, and tunneling layer, doped polysilicon layer, back surface anti-reflection layer and back surface metal electrode are sequentially arranged in the back surface of monocrystalline silicon wafer, the doped layer includes the first diffusion doped layer located in the front surface of silicon wafer and the second epitaxial doped layer between the first diffusion doped layer and the front surface metal electrode.The application overcomes the deficiencies of prior art, can guarantee the thickness of P-type doped layer of metal contact area, effectively shield metal area recombination, and reduce metal area contact resistance;At the same time, it can reduce the doping concentration and junction depth of non-metal area, reduce Auger recombination and parasitic light absorption of non-metal area;Therefore, it can effectively improve the conversion efficiency of TOPCon cell.

The application provides a manufacturing method of a high-voltage planar thyristor, which is surrounded by an extended junction at the edge of the four sides of a front P-type base region, the diameter of the extended circle is different, and gradually decreases away from the front P-type base region, so that the doping concentration continuously and linearly decreases along the front P-type base region to the edge direction, and the gradually reduced doping concentration also gradually reduces the junction depth, which can effectively improve the main junction electric field, thereby reducing the size of the terminal and reducing the chip area; and a composite passivation film is formed on the front of the silicon wafer, which has a shielding effect on the applied electric field, avoids surface breakdown, improves the reverse voltage resistance, and is not easy to crack, so that the performance of the thyristor product is more superior.

The invention discloses a solar cell and a preparation method thereof, and a photovoltaic module, the solar cell comprises a silicon substrate and a PN junction layer arranged on the surface of the silicon substrate, the PN junction layer is provided with a first suede structure, the first suede structure comprises a first spire area and a first tower bottom area, and the junction depth D1 of the first spire area is greater than or equal to the junction depth D2 of the first tower bottom area. According to the invention, carrier recombination can be reduced, and the photoelectric conversion efficiency of the solar cell can be effectively improved.

The application relates to a solar cell, a preparation method thereof and a photovoltaic module. The preparation method of the solar cell comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface arranged oppositely; forming a first tunnel layer and a first doped semiconductor layer in a stack on the first surface; the first doped semiconductor layer is located on the side of the first tunnel layer away from the semiconductor substrate; adopting a microwave annealing process to activate the doped elements in the first doped semiconductor layer, and forming a first inner extension layer in the semiconductor substrate and connected with the first tunnel layer; and forming a first electrode in ohmic contact with the first doped semiconductor layer on the side of the first doped semiconductor layer away from the semiconductor substrate. The application can make the junction depth of the first inner extension layer shallower, is beneficial to reducing the recombination of carriers, and improves the conversion efficiency and stability of the solar cell.