9 results about "Junction depth" patented technology

This invention discloses a method, substrate, and system for detecting laser beam-induced current in the PN junction region profile of an InGaAs photodetector, belonging to the field of semiconductor optoelectronic device characterization technology. The method includes: cleaving a chip with completed front-side processing along the natural cleavage surface of InP to obtain a smooth profile; fixing the chip with the profile facing upwards onto a composite sapphire bonding substrate, and extracting electrodes through conductive silver paste and ultrasonic bonding; performing a two-dimensional step-scan of the profile using a 900-1100nm laser, simultaneously acquiring photocurrent signals to obtain a two-dimensional photocurrent distribution map of the profile; and quantitatively extracting junction depth, lateral diffusion width, and uniformity parameters based on the photocurrent peak position. This invention can directly obtain the longitudinal two-dimensional electrical activity distribution of the PN junction region, effectively avoiding interference between the surface passivation layer and the InP cap layer, and achieving a visual assessment of junction depth, lateral diffusion, and defects, providing a realistic and efficient detection method for device process optimization.

The application relates to a semiconductor device structure and a preparation method thereof, which comprises the following steps: a substrate structure; an epitaxial structure of a first conductive type on the front surface of the substrate structure; a groove structure comprising a first groove and a second groove; a first ion implantation region of a second conductive type in the epitaxial structure and below the bottom of the first groove; a second ion implantation region of the second conductive type in the epitaxial structure and below the bottom of the second groove; an ohmic contact layer on the bottom of the first groove; and a first electrode in the first groove, in the second groove and on the exposed surface of the epitaxial structure away from the substrate structure. The semiconductor device structure of the application adopts a groove type structure, solves the problem of shallow ion implantation depth of the second conductive type in the epitaxial structure, increases the junction depth of a PN junction, improves the shielding capacity of the PN junction to the electric field of a Schottky contact surface during reverse blocking, and improves the reverse recovery speed.

This invention provides a method for achieving high sheet resistance uniformity in boron diffusion for TOPCon solar cells. The method includes sequential steps such as wafer loading, heating, vacuuming, pre-oxygenation, multi-step power supply, variable-temperature multi-step junction pushing, variable-pressure annealing, re-pressure, and wafer unloading. The variable-temperature multi-step junction pushing includes sequential oxygen-free and oxygen-containing junction pushing. The temperature of oxygen-free junction pushing is lower than that of oxygen-containing junction pushing, the time of oxygen-free junction pushing is shorter than that of oxygen-containing junction pushing, the furnace pressure during oxygen-free junction pushing is lower than that during oxygen-containing junction pushing, and the oxygen flow rate during oxygen-containing junction pushing is 18000-23000 sccm. This invention improves the uniformity of boron content distribution by introducing a variable-temperature multi-step junction pushing process that combines oxygen-free followed by oxygen-containing junction pushing with multi-step power supply and variable-pressure annealing. This results in a P+ emitter with lower surface doping concentration and shallower junction depth, while significantly improving the sheet resistance uniformity after boron diffusion, achieving high sheet resistance uniformity under high sheet resistance targets.

A solar cell includes: an N-type silicon wafer, where a front surface of the N-type silicon wafer is provided with a doped region containing boron, the doped region is divided into a lightly doped region and a heavily doped region, a boron concentration of the lightly doped region is less than a boron concentration of the heavily doped region, a junction depth of the lightly doped region is less than a junction depth of the heavily doped region; a passivation layer and a first anti-reflection layer that are sequentially stacked on the front surface of the N-type silicon wafer. An area of a surface of the first anti-reflection layer corresponding to the heavily doped region is provided with an electrode. The electrode extends through the first anti-reflection layer and the passivation layer, and is in an ohmic contact with the heavily doped region.

The application provides a PN junction preparation method of a solar cell and the solar cell, and relates to the technical field of solar photovoltaics. The method is applied to a textured surface of a silicon wafer, and comprises the following steps: first diffusion of a dopant on the textured surface, wherein the dopant is different from the conductive type of the silicon wafer; oxidation of the textured surface after the first diffusion to obtain an oxide layer; second diffusion of the dopant on the oxide layer, so that the dopant remains in the oxide layer; and pushing the diffused dopant in the oxide layer, so that in the two diffusion processes on the textured surface of the silicon wafer, more dopant enters the silicon wafer from the top of the peak in the first diffusion, and less dopant enters the silicon wafer from the bottom of the valley, and the second diffusion is opposite, so that the total amount of the dopant entering different positions of the silicon wafer is relatively average, and the junction depth uniformity of the PN junction of the silicon wafer is effectively ensured.

This application relates to the field of semiconductor silicon wafer manufacturing technology, and particularly to a boron-aluminum diffusion source and its preparation method. A boron-aluminum diffusion source has a metal impurity content of <20 ppm and a sodium ion content of <15 ppm. The components of the boron-aluminum diffusion source include 15-35% silicate ester, 2-5% water, 25-35% lower alcohols, 25-35% ethers, 2-12% boron source, 5-20% aluminum source, 0.01-1% acid, and 0.01-0.5% dispersant. The preparation method includes: 1) mixing and dissolving the boron source, aluminum source, and ether; 2) mixing the silicate ester with water for hydrolysis and condensation; and 3) blending. This application controls the metal impurity content in the boron-aluminum diffusion source to <20 ppm, and the sodium content to <15 ppm, which can effectively improve the TRR value of the chip's electrical parameters. Controlling the metal impurity content and sodium content in the boron-aluminum diffusion source can also improve the problem of uneven and rough film formation during the baking process, resulting in a product with lower sheet resistance and PN junction depth dispersion.

The application provides a metal-oxide semiconductor field effect transistor and a preparation method thereof. The metal-oxide semiconductor field effect transistor comprises an active region and a terminal region. A first field limiting ring and a second field limiting ring are prepared in an epitaxial layer located in the terminal region. The doping concentration of the doping ions in the second field limiting ring is greater than the doping concentration of the doping ions in the first field limiting ring. The junction depth of the second field limiting ring is less than the junction depth of the first field limiting ring. The second field limiting ring is set as a shallow-junction high-doping-concentration field limiting ring relative to the first field limiting ring, and the corresponding field oxide layer is set, so that the fixed charges and movable charges in the terminal region field oxide layer can be effectively shielded, the terminal region depletion layer is prevented from shrinking, the reliability of the device in a high-voltage scene is improved, the device withstand voltage is improved in combination with the first field ring, and the operation performance and operation stability of the device are simultaneously improved.

This invention discloses a TOPCon battery and its fabrication method, belonging to the field of TOPCon battery technology. It includes a monocrystalline silicon wafer with a tunneling layer, a doped polycrystalline silicon layer, a back anti-reflection layer, and a back metal electrode sequentially disposed on its back side from the inside out. The doped polycrystalline silicon layer includes a first doped polycrystalline silicon region and a second doped polycrystalline silicon region. The first doped polycrystalline silicon region is in contact with the back metal electrode and is disposed on the surface of a groove. The tunneling oxide layer is relatively thin, and the inward junction depth is greater than that of the second doped polycrystalline silicon region. This effectively prevents electrode metal from penetrating into the junction region, reduces metal recombination current, and improves the battery's open-circuit voltage. Furthermore, the first doped polycrystalline silicon region has a larger contact area with the printing paste, reducing the battery's contact resistance. Simultaneously, the groove prevents the printing paste from widening outward, ensuring a high grid line aspect ratio, reducing grid line resistance, and thus improving the battery's fill factor.