121 results about "Junction depth" patented technology

The invention discloses a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes a substrate having opposing front and back surfaces. A main junction region, a terminal region and a field cut-off region are sequentially arranged in the position, close to the front surface, of the substrate in the first direction parallel to the front surface. At least one groove is formed in the position, close to the field stop region, in the terminal region, a field limiting ring is formed in the terminal region, at least one part of the field limiting ring surrounds the groove, and the junction depth of the field limiting ring with the groove surrounded therein is larger than that of the field limiting ring with no groove surrounded therein. According to the semiconductor device, the groove structure is arranged in the terminal region, so that the ion implantation depth can be increased, and a deeper junction depth can be formed subsequently. The deeper junction depth can reduce the surface peak electric field intensity, the peak electric field intensity is transferred from the surface to a silicon body, and the curvature radius of the terminal P-type injection region is increased, so that the effect of increasing the breakdown voltage of the terminal structure is achieved.

The invention discloses a solar single-crystal efficient TOPCon + SE battery piece ultrahigh sheet resistance diffusion process which mainly comprises a front boron process, an SE process and a rear oxidation process, and the front boron process comprises high-temperature oxidation before diffusion and a diffusion process composed of three-step diffusion and heating propulsion. According to the invention, a layer of SiO2 can be coated on the surface of the silicon wafer through high-temperature oxidation before diffusion and is used as an anti-reflection film layer; the PN junction is prepared by adopting a step-by-step diffusion method, so that the advantage of good junction uniformity can be realized, boron can be uniformly distributed on the surface of a silicon wafer through a specific boron diffusion method, and meanwhile, boron elements can be better deposited on the surface of the silicon wafer through variable-temperature diffusion and propulsion; by adding the SE process, the square resistance can reach 700-800 ohms, the junction depth in the grid line area is deeper, the increase of ohms becomes better, the cell center recombination is reduced due to the lower surface concentration, and the open-circuit voltage of the cell is improved; and the post-oxidation process has an annealing effect and can repair lattice damage and the like.

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The invention relates to the technical field of semiconductors, in particular to a SiC JEFT device capable of improving the avalanche capability and a manufacturing method thereof, a source region and a gate region are arranged in a groove at the same time, and the depth of a second type doping region of the source region is different from that of a second type doping region of the gate region; wherein the junction depth of the second-type doped region of the source region is deeper than that of the second-type doped region of the gate region, so that the maximum electric field is located at the junction edge of the second-type doped region of the source region in a turn-off state, an avalanche current enters the source electrode through ohmic contact of the source region and does not pass through the gate electrode any more, and the reliability of avalanche is ensured.

The invention provides a main junction modulation fast recovery diode chip and a preparation method thereof, and relates to the technical field of semiconductors. The preparation method of the main junction modulation fast recovery diode chip comprises the following steps: providing an epitaxial wafer, and forming a main junction window and a cut-off ring window on a first surface of the epitaxial wafer by adopting a photoetching process; first nonmetal is injected into the main junction window and the cut-off ring window respectively, and diffusion junction pushing is carried out; forming a field limiting ring window on the first surface of the epitaxial wafer by adopting a photoetching process; and second nonmetal is injected into the main junction window and the field limiting ring window respectively and diffusion junction pushing is carried out so as to realize junction depth distribution of the main junction shallow ring junction depth. According to the preparation method of the main junction modulation fast recovery diode chip, the junction depth distribution of the main junction shallow ring junction depth can be generated on the premise of saving one-time photoetching, the withstand voltage, the through-current capability, the surge level and the preparation efficiency of the main junction modulation fast recovery diode chip can be improved, and the manufacturing cost of the main junction modulation fast recovery diode chip is reduced.

The invention relates to a method and a device for detecting substrate defects. The method for detecting the substrate defects comprises the following steps: providing a substrate to be detected, wherein the substrate to be detected comprises a top surface and a bottom surface which are oppositely distributed along a first direction; forming a plurality of test structures arranged at intervals along a second direction, each test structure comprising PN junctions located in the to-be-tested substrate, and the PN junctions in at least two test structures having different junction depths; acquiring a plurality of reverse bias leakage currents corresponding to the plurality of test structures respectively; and judging whether at least one reverse bias leakage current of which the order of magnitude is higher than the order of magnitude of other reverse bias leakage currents exists in the plurality of reverse bias leakage currents, and if so, determining that defects exist in the substrate to be detected. According to the invention, the operation of defect detection in the to-be-detected substrate is simplified, the to-be-detected substrate is prevented from being damaged, and the defect detection efficiency is effectively improved.

The embodiment of the invention provides an N-type TOPCon battery and a preparation method thereof, and in the preparation method of the N-type TOPCon battery provided by the embodiment of the invention, after boron diffusion and laser doping, a silicon wafer is oxidized by adopting mixed gas of oxygen and water vapor, so that the oxidation rate is increased, the process temperature can be effectively reduced, the process time can be effectively shortened, and the production efficiency of the N-type TOPCon battery is improved. The doping concentration of boron atoms on the surface of the silicon wafer is remarkably reduced, impurity recombination is reduced, the open voltage of the cell is improved, the boron atom doping junction depth can be reduced, the short-wave light response in sunlight is improved, and the current is improved; in addition, the reduction of the oxidation temperature also reduces the generation of silicon substrate and boron-oxygen defect compound pairs, and reduces the blackening defect of concentric rings.

The invention belongs to the technical field of solar cell manufacturing, and provides a step temperature cycle propulsion boron diffusion process and application thereof. The boron diffusion technology comprises the steps that a silicon wafer is placed in boron diffusion equipment, pre-oxidation, pre-deposition and stepped temperature circulation boron diffusion propelling are sequentially carried out on the silicon wafer, and the stepped temperature circulation boron diffusion propelling procedure comprises an initial stage, a middle stage and a final stage which are sequentially carried out. A circulation mode of heating oxygen-free boron expansion and pushing junction and then cooling oxygen-filled boron expansion and pushing junction is adopted in each stage for multiple times of circulation, and the heating temperature and the cooling temperature of each stage are optimized, so that a boron expansion doping layer is formed on the surface of the silicon wafer. According to the boron diffusion process, the oxidation temperature can be reduced, the concentric circle defect can be eliminated, the junction depth and the surface doping concentration of boron diffusion doping can be increased, the uniformity of boron diffusion doping can be improved, the FF, Jsc, Uoc and Eta of the battery can be further improved, the thermal budget can be reduced, and the service life of equipment can be prolonged.

The invention belongs to the related technical field of semiconductor doping, and discloses a method for acquiring a second harmonic signal of non-uniform ion implantation doping concentration and an application of the second harmonic signal of the non-uniform ion implantation doping concentration. Determining refractive indexes and absorption coefficients of different depth positions of the ion implantation doping sample under a specific laser wavelength based on an optical property distribution model in the ion implantation doping sample; s2, calculating fundamental frequency light electric field distribution in the doped sample based on the obtained refractive index and absorption coefficient; s3, calculating the polarization intensity and effective second-order polarizability of the non-uniform doped ion implantation sample based on the simplified bond hyperpolarizability model and the fundamental frequency photoelectric field distribution; and S4, calculating far-field second harmonics of the corresponding layers at a predetermined observation angle based on the obtained polarization intensity or effective second-order polarizability of each layer, and carrying out integration on the far-field second harmonics corresponding to all layers to obtain the total intensity of the second harmonics of junction depth far-field radiation. According to the invention, the problem that the measurement sensitivity and repeatability are reduced is solved.

The invention relates to the technical field of semiconductors, and discloses a PN junction material carrier concentration and mobility test method and application. The test method comprises the following steps: carrying out a Hall test on an N-type substrate to obtain the carrier concentration n and mobility mu n of the N-type substrate; p-type ions are doped on the N-type substrate to form a P-on-N structure sample, the sample is subjected to a Hall test, and the Hall coefficient Rh and the resistivity rho are measured; corroding the P-on-N structure sample by the corrosive liquid to form an inclined table surface, and measuring the corrosion depth h; determining the junction depth by using an IV curve, and obtaining the thickness dp of a P layer and the thickness dn of an N-type layer; and substituting into a calculation formula to obtain the P-type carrier concentration p and the P-type carrier mobility mu p. According to the PN junction material testing method, the concentration and mobility of bipolar carriers of electrons and holes can be effectively tested, the testing method is simple, errors are small, and the problems that the P-type concentration cannot be measured due to inaccurate carrier measurement, the testing process is tedious and the like can be effectively solved.

The invention discloses a solar cell boron emitter and a preparation method and application thereof, and belongs to the field of solar cells, after a monocrystalline silicon wafer is selected, cleaned and textured, a first BSG layer, a silicon oxide mask layer and a second BSG layer are sequentially deposited on the front surface of the silicon wafer, and then annealing treatment is carried out; wherein the boron atom concentration of the first BSG layer is lower than that of the second BSG layer, and the oxygen atom concentration of the first BSG layer is higher than that of the second BSG layer. The BSG layer with low-concentration boron atoms and high-concentration oxygen atoms, the silicon oxide mask layer and the BSG layer with high-concentration boron atoms and low-concentration oxygen atoms are sequentially deposited on the silicon wafer, and after annealing treatment, the surface of the formed boron emitter has high boron doping concentration and can be in better contact with a metal electrode; and meanwhile, the junction depth of the boron emitter is relatively shallow, defects caused by internal boron doping can be repaired due to existence of high-concentration oxygen atoms, and compounding of a silicon substrate is reduced.

The invention discloses a boron diffusion manufacturing process method, which comprises the following steps of: after a boron diffusion window is formed, pre-growing or depositing a layer of sacrificial silicon oxide insulating dielectric film on the surface of a silicon wafer, depositing boron on the surface of the silicon wafer at high temperature, and further forming a layer of silicon oxide insulating dielectric film containing high-concentration boron on the surface of the silicon wafer during boron deposition, and removing the high-concentration silicon oxide insulating dielectric film by wet etching, and partially or completely removing the pre-grown or deposited sacrificial silicon oxide insulating dielectric film, and then propelling boron deposited on the surface of silicon to a required junction depth position at a high temperature, and forming required impurity distribution. The method can prevent formation of difficult-to-etch silicon oxide after high-temperature propulsion, can inhibit precipitation of high-concentration boron, and can be widely applied to manufacturing of power semiconductor chips such as Schottky diodes, fast recovery diodes, rectifier diodes and the like and photovoltaic diodes.

The invention discloses a planar SiC MOS (Metal Oxide Semiconductor) gate-controlled thyristor device based on an epitaxial surface and a manufacturing method thereof, effectively avoids the problem of using a triple ion implantation process traditionally by ingeniously introducing an n-type epitaxial layer, and utilizes the advantages of high growth speed, low material defect, good process stability and the like of an epitaxial growth technology to improve the performance of the device. The semiconductor layer with lower surface defect density can be obtained, the mobility of channel carriers is effectively improved, and the working performance of the device is improved. By introducing the n-type epitaxial region, the separation design of the p-type ion implantation well region and the n-type ion implantation well region is realized, the doping concentration can be controlled more accurately by the surface structure of the epitaxial layer, and the deeper junction depth of the p-type ion implantation well region and the deeper base region width of the n-type ion implantation well region can be controlled and realized. The design difficulty that the ion implantation junction depth of the device needs to exceed 1 [mu] m is reduced, and the problem that the original lattice structure of the material is damaged by SiC high-temperature ion implantation is avoided.

The invention discloses a Schottky diode and a preparation method thereof, the Schottky diode comprises a heavily doped N-type substrate layer and a lightly doped N-type epitaxial layer formed on the upper surface of the heavily doped N-type substrate layer, the upper part of the lightly doped N-type epitaxial layer is provided with a groove structure, the groove structure is filled with doped polycrystalline silicon, the doped polycrystalline silicon is polycrystalline silicon doped with P-type impurities, and the doped polycrystalline silicon is doped with P-type impurities. Doped polycrystalline silicon is used as a solid phase diffusion source, and solid phase diffusion is carried out on the doped polycrystalline silicon to diffuse P-type impurities to the lightly doped N-type epitaxial layer, so that P-type regions are formed on the side wall and the bottom of the groove structure. According to the Schottky diode and the preparation method thereof, the P-type region is formed on the side wall and the bottom of the groove structure, the P-type region and the lightly doped N-type epitaxial layer form the depletion region, a good three-dimensional heat dissipation channel is formed, the heat dissipation burden is reduced, the P-type region is formed through solid-phase diffusion, and compared with ion implantation, the junction depth is easier to control.

The present invention provides a stacked doping source structure, a related high-quality emitter and a preparation method therefor. The stacked doping source structure comprises a nanometer silicon oxide layer, a doped silicon oxide layer, and a doping source layer that are stacked on the front surface of a crystalline silicon substrate; the doped silicon oxide layer is doped with boron or phosphorus atoms; the material of the doping source layer is selected from among one of boron / phosphorus-doped amorphous silicon, carbon-doped boron / phosphorus-doped amorphous silicon, nitrogen-doped boron / phosphorus-doped amorphous silicon, and carbon-nitrogen co-doped boron / phosphorus-doped amorphous silicon. According to the present invention, a front doping source is composed of nanometer silicon oxide, doped silicon oxide, and boron / phosphorus-doped amorphous silicon, so that the doping source structure has both a strong laser absorption capability and high boron / phosphorus concentration, thereby being conducive to reducing the laser power and illumination time required by the laser doped selective emitter technology, reducing surface recombination without losing a junction depth and sheet resistance, improving the passivation effect, and thus further prompting the improvement of the cell efficiency.

The application provides a method for detecting the effective junction depth of a tellurium-cadmium-mercury chip PN junction, and belongs to the technical field of semiconductors. The method comprises the following steps: selecting a tellurium-cadmium-mercury chip which has been formed through an ion implantation and annealing junction process and has been passivated; dividing the ion implantation area of the tellurium-cadmium-mercury chip into multiple regions, removing the passivation layer in each region and part of the ion implantation area below the passivation layer, and forming multiple contact holes arranged in a preset depth gradient; growing a metal electrode on each contact hole; measuring the voltage-current curve of each metal electrode at different etching depths; and determining the corresponding PN junction depth as the effective junction depth of the tellurium-cadmium-mercury chip when the voltage-current curve changes from a Schottky curve to a linear curve. The application is the same as the original chip manufacturing process of tellurium-cadmium-mercury, can be applied to the process production process of a tellurium-cadmium-mercury infrared detector, and can monitor the effective junction depth of the tellurium-cadmium-mercury after ion implantation in real time.

Structures and formation methods of a semiconductor device are provided. The method includes forming a first dummy gate structure across a first fin in a first transistor region of a semiconductor substrate and a second dummy gate structure across a second fin in a second transistor region of the semiconductor substrate. The method also includes selectively introducing atomic or ionic species into the second fin on opposite sides of the second dummy gate structure and etching portions of the first and second fins, so as to form first and second recesses. Each recess is in the respective fin on a side of the respective dummy gate structure. The first recess has a different depth than the second recess. The method further includes forming first and second source / drain features in the first and second recesses, respectively.

This invention discloses a method, substrate, and system for detecting laser beam-induced current in the PN junction region profile of an InGaAs photodetector, belonging to the field of semiconductor optoelectronic device characterization technology. The method includes: cleaving a chip with completed front-side processing along the natural cleavage surface of InP to obtain a smooth profile; fixing the chip with the profile facing upwards onto a composite sapphire bonding substrate, and extracting electrodes through conductive silver paste and ultrasonic bonding; performing a two-dimensional step-scan of the profile using a 900-1100nm laser, simultaneously acquiring photocurrent signals to obtain a two-dimensional photocurrent distribution map of the profile; and quantitatively extracting junction depth, lateral diffusion width, and uniformity parameters based on the photocurrent peak position. This invention can directly obtain the longitudinal two-dimensional electrical activity distribution of the PN junction region, effectively avoiding interference between the surface passivation layer and the InP cap layer, and achieving a visual assessment of junction depth, lateral diffusion, and defects, providing a realistic and efficient detection method for device process optimization.

According to the silicon-based PIN photodiode, the manufacturing method and the electronic device provided by the invention, the FZ single crystal is adopted as the substrate, and the doped region is formed in an ion implantation and annealing mode, so that the junction depth and the concentration can be effectively controlled. And thinning the silicon wafer by adopting a Taiko back thinning process. The photosensitive area adopts a shallow junction and deep junction combined structure, the shallow junction can increase the blue light absorption rate, and the deep junction forms ohmic contact. The anti-reflection layer adopts a silicon dioxide and silicon nitride double-layer structure, so that the surface stress of silicon / silicon nitride can be effectively relieved, and the reliability is improved. The cut-off region N + and the back N + can reduce dark current, and back metallization can form a back cathode.

The invention provides a Hall device and a manufacturing method thereof, and the manufacturing method comprises the steps: firstly, defining a region of a functional layer region of the Hall device on the surface of a high-resistance substrate through a photoetching technology, then carrying out the N-type and P-type ion implantation of the high-resistance substrate at the same time, and carrying out the high-temperature long-time thermal process, a uniform N-type doped device main function layer region and a P-type doped auxiliary function region located at the bottom of the device main function layer region are formed in a high-resistance substrate, and finally a well region and a first heavily doped region located in the well region are formed respectively. According to the invention, no extra photomask needs to be added, the photomask is injected by using the traditional Hall device function layer, N-type and P-type foreign ions are injected at the same time, the junction depth of the Hall device function layer is ensured to be less than or equal to 1.5 microns by adjusting the injection energy and dosage of the two foreign ions, the N-type foreign ions are adjusted to be injected with low doping concentration, the carrier mobility is improved, and the performance of the Hall device is improved. The sensitivity of the Hall device is improved, and the manufacturing difficulty of the shallow junction Hall device is reduced.

The invention discloses a channel mobility testing method, a channel mobility testing structure and a manufacturing method of the channel mobility testing structure. The channel mobility test method comprises the following steps: providing a semiconductor device; determining the resistance between the source electrode and the drain electrode of each semiconductor device by applying a test voltage to the source electrode, the drain electrode and the gate electrode structure of at least two different semiconductor devices; wherein the junction depths of the JFET regions of at least part of the semiconductor devices in the at least two different semiconductor devices are different; the junction depth of the JFET region is the size of the JFET region in the direction from the first surface to the second surface; and determining the channel mobility of the semiconductor device according to the resistance between the source electrode and the drain electrode of each semiconductor device and the junction depth of the JFET region of each semiconductor device. According to the embodiment of the invention, the measurement of the channel field effect mobility can be realized, the measurement mode is simple, and the measurement efficiency is high.

The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device based on a SiC material and a manufacturing process of the semiconductor device. The device comprises an N + type SiC substrate, an N-type composite buffer layer which is arranged on the substrate and has a concentration gradient, an N-type drift region which is arranged on the buffer layer, and an active region which is composed of a first conduction type region and a second conduction type ion implantation region. The innovation lies in that a composite buffer layer structure is adopted to effectively suppress dynamic avalanche and optimize the reverse recovery characteristic, and meanwhile, a composite structure of a junction termination extension region and a field limiting ring with shallower junction depth is integrated in a terminal region, so that the process complexity is simplified on the premise of ensuring high breakdown voltage. According to the manufacturing process, impurity activation of the active region and the terminal region is synchronously completed through two times of ion implantation and one time of high-temperature annealing, and the manufacturing process is completely compatible with an existing SiC plane process platform. The device realizes excellent compromise between reverse recovery charge and forward voltage drop, and has the characteristics of superspeed, soft recovery, low loss and high reliability.

The present invention discloses a method for improving chipping edge of dicing, comprising the following steps: Step 1: Wafer preparation: Select MCZ silicon single crystal wafer, 5-inch crystal orientation <111> , resistivity 5.0‑6.5Ω / cm, thickness 220μm±10%; Step 2: Slice road doping: Phosphorus liquid source deposition is performed under the conditions of furnace temperature 1120°C, oxygen 2L / min, nitrogen 3L / min, and source-carrying nitrogen 1.2L / min; Phosphorus source advancement is performed under the conditions of furnace temperature 1140°C, oxygen 2.5L / min, and nitrogen 4L / min; Four-probe test is used to test the diffusion block resistance of 0.6Ω±10%, and the junction depth is 12μm±10%. In the present invention, a high-concentration impurity doping process is performed on the scribe road area to make the scribe road "loose", thereby reducing the severity of scribe edge collapse and the resulting lattice damage, and improving the scribe quality of the wafer.

The invention relates to the field of photo-transistors, in particular to a high-CTR and high-speed photo-transistor based on layout optimization and a manufacturing method thereof.The high-CTR and high-speed photo-transistor comprises a semiconductor substrate, and an N-type epitaxial layer, a P-type base region and an N-type emitter region are sequentially formed on the semiconductor substrate; the P-type base region comprises a photoelectric sensing region and a base electrode main body which are independently arranged, the photoelectric sensing region is used for receiving optical signals and generating current carriers, the base electrode main body and the N-type emission region form a PN junction, and the node depth and the doping concentration of the base electrode main body can be independently adjusted according to beta value design requirements; the photoelectric sensing area and the base electrode main body are independently arranged, the section depth and the doping concentration of the base electrode main body can be flexibly adjusted according to beta value design, the problem that the section depth of a base electrode in a traditional shared structure is limited by photoelectric conversion efficiency is avoided, CTR is obviously improved, parameter stability is higher, and production efficiency is improved.

The application relates to the technical field of semiconductors, in particular to a SiC JFET device with improved avalanche capability and a manufacturing method thereof. The source region and the gate region are simultaneously arranged in a groove, and the depth of the second-type doped region of the source region is different from that of the second-type doped region of the gate region, wherein the junction depth of the second-type doped region of the source region is deeper than that of the second-type doped region of the gate region, so that the maximum electric field is at the junction edge of the second-type doped region of the source region in the off state, thereby making the avalanche current enter the source electrode through the ohmic contact of the source region without passing through the gate electrode, and the reliability of the avalanche is ensured.

The invention relates to a P-type double-injection fast recovery diode device structure and a manufacturing method thereof in the technical field of semiconductor discrete power devices, the fast recovery diode device structure comprises an N-type substrate, the N-type substrate comprises an N + substrate layer and an N-epitaxial layer formed on the N + substrate layer, the N-epitaxial layer is provided with an active region and a terminal region, and the terminal region is provided with a first electrode and a second electrode. The field limiting ring in the terminal region is subjected to P-type injection and P + type injection twice, the depth of the second P-type ion injection is smaller than the depth of the first P-type ion injection, the concentration of the second P-type ion injection is larger than the concentration of the first P-type ion injection, and the area of the second P-type ion injection is smaller than the area of the first P-type ion injection, so that the pressure resistance of the device is improved; p-of the main junction anode region in the active region and P-of the terminal region are injected at the same time, so that junction depths between the active region and the terminal region are kept flush, the voltage withstanding uniformity of the device is improved, and the reliability and the avalanche capability of the device are improved.

The present invention discloses a floating field-limiting ring power device based on dielectric positioning and a preparation method thereof, which includes a device main body, a high-K dielectric trench region, and a P-type floating field-limiting ring; the device main body includes an N-type doped semiconductor drift region; the high-K dielectric trench regions are arranged equidistantly at the top center of the semiconductor drift region, and each high-K dielectric trench region includes a groove and a high-K dielectric filled in the groove; an active layer located between the high-K dielectric trench regions forms a semiconductor island region; the semiconductor island region is formed into a P-type floating field-limiting ring through P-type doping, and the junction depth of the P-type floating field-limiting ring is greater than the depth of the high-K dielectric trench region. The groove is a strip-shaped groove, a mesh groove, a rectangular groove, or the like. The P-type floating field-limiting ring of the present invention is positioned based on the dielectric groove, which can reduce process steps such as masking. The high-K dielectric deposited in the groove can effectively modulate the surface electric field and avoid the influence of surface charges on the P-type floating field-limiting ring, thereby improving the breakdown voltage. At the same time, the concentration of the drift region is increased, and the on-resistance of the device is reduced.

The present disclosure relates to a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: forming a hard mask on a main surface of a wafer; performing active region photolithography and etching, and removing the hard mask at a position where a field oxide layer needs to be formed; forming the field oxide layer; forming a patterned photoresist layer on the main surface, wherein the photoresist layer covers a position where no drift region needs to be formed; and performing drift region implantation by using the photoresist layer as an implantation blocking layer, wherein ions implanted during drift region implantation pass through the hard mask and the field oxide layer and enter the wafer. In the present disclosure, during drift region implantation, the implanted ions at the edge of the field oxide layer are blocked by using the hard mask, so as to avoid excessive PN junction depth and excessively high ion doping concentration at this position. Rapid depletion of the implanted ions in a JFET region at this position is achieved, thereby reducing the electric field strength at this position, and optimizing and improving the voltage withstand and reliability of the device.

The application relates to a semiconductor device structure and a preparation method thereof, which comprises the following steps: a substrate structure; an epitaxial structure of a first conductive type on the front surface of the substrate structure; a groove structure comprising a first groove and a second groove; a first ion implantation region of a second conductive type in the epitaxial structure and below the bottom of the first groove; a second ion implantation region of the second conductive type in the epitaxial structure and below the bottom of the second groove; an ohmic contact layer on the bottom of the first groove; and a first electrode in the first groove, in the second groove and on the exposed surface of the epitaxial structure away from the substrate structure. The semiconductor device structure of the application adopts a groove type structure, solves the problem of shallow ion implantation depth of the second conductive type in the epitaxial structure, increases the junction depth of a PN junction, improves the shielding capacity of the PN junction to the electric field of a Schottky contact surface during reverse blocking, and improves the reverse recovery speed.

An insulated gate bipolar transistor and a preparation method thereof, and an electronic device. The insulated gate bipolar transistor includes: a drift region; an electrode structure on one side of the drift region; and an electric field stop layer arranged on one side of the drift region away from the electrode structure. The electric field stop layer includes a first sublayer and a second sublayer laminated together. The first sublayer is arranged close to the drift region. A junction depth of the first sublayer is greater than a junction depth of the second sublayer. A peak value of a doping concentration of the first sublayer is less than a peak value of a doping concentration of the second sublayer. A slope of a doping concentration curve of the first sublayer is less than a slope of a doping concentration curve of the second sublayer.