31 results about "Junction depth" patented technology

The invention discloses a planar SiC MOS (Metal Oxide Semiconductor) gate-controlled thyristor device based on an epitaxial surface and a manufacturing method thereof, effectively avoids the problem of using a triple ion implantation process traditionally by ingeniously introducing an n-type epitaxial layer, and utilizes the advantages of high growth speed, low material defect, good process stability and the like of an epitaxial growth technology to improve the performance of the device. The semiconductor layer with lower surface defect density can be obtained, the mobility of channel carriers is effectively improved, and the working performance of the device is improved. By introducing the n-type epitaxial region, the separation design of the p-type ion implantation well region and the n-type ion implantation well region is realized, the doping concentration can be controlled more accurately by the surface structure of the epitaxial layer, and the deeper junction depth of the p-type ion implantation well region and the deeper base region width of the n-type ion implantation well region can be controlled and realized. The design difficulty that the ion implantation junction depth of the device needs to exceed 1 [mu] m is reduced, and the problem that the original lattice structure of the material is damaged by SiC high-temperature ion implantation is avoided.

This invention discloses a method, substrate, and system for detecting laser beam-induced current in the PN junction region profile of an InGaAs photodetector, belonging to the field of semiconductor optoelectronic device characterization technology. The method includes: cleaving a chip with completed front-side processing along the natural cleavage surface of InP to obtain a smooth profile; fixing the chip with the profile facing upwards onto a composite sapphire bonding substrate, and extracting electrodes through conductive silver paste and ultrasonic bonding; performing a two-dimensional step-scan of the profile using a 900-1100nm laser, simultaneously acquiring photocurrent signals to obtain a two-dimensional photocurrent distribution map of the profile; and quantitatively extracting junction depth, lateral diffusion width, and uniformity parameters based on the photocurrent peak position. This invention can directly obtain the longitudinal two-dimensional electrical activity distribution of the PN junction region, effectively avoiding interference between the surface passivation layer and the InP cap layer, and achieving a visual assessment of junction depth, lateral diffusion, and defects, providing a realistic and efficient detection method for device process optimization.

According to the silicon-based PIN photodiode, the manufacturing method and the electronic device provided by the invention, the FZ single crystal is adopted as the substrate, and the doped region is formed in an ion implantation and annealing mode, so that the junction depth and the concentration can be effectively controlled. And thinning the silicon wafer by adopting a Taiko back thinning process. The photosensitive area adopts a shallow junction and deep junction combined structure, the shallow junction can increase the blue light absorption rate, and the deep junction forms ohmic contact. The anti-reflection layer adopts a silicon dioxide and silicon nitride double-layer structure, so that the surface stress of silicon / silicon nitride can be effectively relieved, and the reliability is improved. The cut-off region N + and the back N + can reduce dark current, and back metallization can form a back cathode.

The application relates to a semiconductor device structure and a preparation method thereof, which comprises the following steps: a substrate structure; an epitaxial structure of a first conductive type on the front surface of the substrate structure; a groove structure comprising a first groove and a second groove; a first ion implantation region of a second conductive type in the epitaxial structure and below the bottom of the first groove; a second ion implantation region of the second conductive type in the epitaxial structure and below the bottom of the second groove; an ohmic contact layer on the bottom of the first groove; and a first electrode in the first groove, in the second groove and on the exposed surface of the epitaxial structure away from the substrate structure. The semiconductor device structure of the application adopts a groove type structure, solves the problem of shallow ion implantation depth of the second conductive type in the epitaxial structure, increases the junction depth of a PN junction, improves the shielding capacity of the PN junction to the electric field of a Schottky contact surface during reverse blocking, and improves the reverse recovery speed.

The application provides a TOPCon cell, comprising: a single crystal silicon wafer; an inner expansion layer arranged on the back surface of the single crystal silicon wafer; a doped polysilicon layer arranged below the inner expansion layer; the doped polysilicon layer comprises: a first doped polysilicon region and a second doped polysilicon region, the doping concentration of the first doped polysilicon region is higher than that of the second doped polysilicon region; the inner layer comprises: a first inner expansion region and a second inner expansion region, the position of the first inner expansion region corresponds to the position of the first doped polysilicon region, and the junction depth of the first inner expansion region is greater than that of the second inner expansion region. The TOPCon cell provided by the application has a specific structure, which can ensure the thickness and concentration of the doped polysilicon in the metal contact area, avoid the destruction of the tunneling oxide layer in the slurry sintering process, reduce the recombination current and the contact resistance, and at the same time, reduce the light parasitic absorption of the non-metal area, especially the free carrier absorption.

A pixel includes a semiconductor substrate, a photodiode region, a floating diffusion region, and a dielectric layer. The substrate has a top surface that forms a trench, the trench is lined by the dielectric layer, and has a trench depth relative to a planar region of the top surface. The photodiode region is in the substrate and includes a bottom photodiode portion under the trench and a top photodiode portion adjacent the trench, the top photodiode portion abutting the bottom photodiode portion and extending toward the planar region to a photodiode depth that is less than the trench depth. The floating diffusion region is adjacent the trench and has a junction depth that is less than the trench depth. A top region of the dielectric layer is between the planar region and the junction depth. A bottom region of the dielectric layer is between the photodiode depth and the trench depth and is thicker than the top region.

The application discloses a metal silicide forming method, which comprises the following steps: providing a substrate, forming a gate dielectric layer on the substrate, forming a gate electrode on the gate dielectric layer, forming a side wall on the periphery of the gate electrode, and forming a heavily doped region in the substrate on both sides of the side wall; forming a first metal layer by sputtering deposition through a first target material, the first target material comprising nickel and platinum, and the first metal layer covering the exposed areas of the substrate, the gate dielectric layer, the gate electrode and the side wall; forming a second metal layer on the first metal layer by sputtering deposition through a second target material, the second target material comprising nickel and platinum, and the content of platinum in the second target material being higher than that in the first target material; and performing heat treatment to form metal silicide in the gate electrode and the heavily doped region. The first metal layer and the second metal layer are sequentially deposited on the substrate, the content of platinum in the target material used for depositing the first metal layer is less than that in the target material used for depositing the second metal layer, the silicon loss and the junction depth are reduced, and the reliability and yield of the device are improved.

The invention belongs to the field of power semiconductors, and particularly relates to an asymmetric GCT chip which comprises a P + transparent emission anode, an N-base region, a P base region, a P + base region and an N + emission region partially embedded in the P + base region, or an N'buffer layer is arranged between the P + transparent emitting anode region and the N-base region; the center of the N + emitter region is provided with a groove, and the groove is filled with a cathode metal layer and is led out. According to the asymmetric GCT chip provided by the invention, a comb structure with a groove is adopted, under the same chip size, the effective area of a cathode is increased, the doping concentration of a P + base region below an N + emitter region is reduced, the opening performance of the chip is improved, the junction depth of a J3 junction is basically kept unchanged, and the turn-off capability is not reduced while the through-current capability is improved.

The invention provides an ion implantation depth measuring method and device, and belongs to the field of semiconductor manufacturing. The method provided by the invention comprises the following steps: determining a first duration; determining a first etching time length and a second etching time length according to the first time length; performing etching for a second etching duration, and determining a first etching rate of the dielectric layer; performing etching for a first etching time length and a second etching time length, and determining the thickness change of the dielectric layer under each etching time length; according to the thickness change of the dielectric layer under each etching duration, determining whether the etching process corresponding to each etching duration corresponds to two different types of etching; if yes, the thickness of the injection layer is determined, and if not, the step of determining the first etching duration and the second etching duration according to the first duration is executed again. According to the technical field of semiconductor manufacturing, the method for measuring the junction depth by detecting the etching rate change caused by ion implantation solves the problems of high cost and low efficiency of the traditional technology.

The invention provides a preparation method and equipment of a battery emitter, relates to the field of semiconductor or photovoltaic material processing, and solves the technical problem of low battery efficiency caused by non-uniform temperature of the edge and the center of a silicon wafer in a traditional boron junction pushing process. The preparation method of the battery emitter comprises the following steps: under a heating condition, depositing a borosilicate glass layer on one side of an N-type silicon wafer in a first direction; under the condition of continuous cooling, protective gas is introduced into the process chamber, so that boron atoms in the borosilicate glass layer are pushed to enter the part, close to the borosilicate glass layer, of the N-type silicon wafer. As part of heat in the center of the N-type silicon wafer needs to be transmitted outwards through the edge, the cooling speed of the edge is higher than that of the center, the difference between the edge temperature and the center temperature is reduced, the speeds of boron atoms pushing junctions to the edge and the center are closer, the distribution difference of boron impurities in the edge and the center is reduced, the junction depth is more uniform, and the junction quality is improved. And the battery efficiency is improved.

This invention provides a method for achieving high sheet resistance uniformity in boron diffusion for TOPCon solar cells. The method includes sequential steps such as wafer loading, heating, vacuuming, pre-oxygenation, multi-step power supply, variable-temperature multi-step junction pushing, variable-pressure annealing, re-pressure, and wafer unloading. The variable-temperature multi-step junction pushing includes sequential oxygen-free and oxygen-containing junction pushing. The temperature of oxygen-free junction pushing is lower than that of oxygen-containing junction pushing, the time of oxygen-free junction pushing is shorter than that of oxygen-containing junction pushing, the furnace pressure during oxygen-free junction pushing is lower than that during oxygen-containing junction pushing, and the oxygen flow rate during oxygen-containing junction pushing is 18000-23000 sccm. This invention improves the uniformity of boron content distribution by introducing a variable-temperature multi-step junction pushing process that combines oxygen-free followed by oxygen-containing junction pushing with multi-step power supply and variable-pressure annealing. This results in a P+ emitter with lower surface doping concentration and shallower junction depth, while significantly improving the sheet resistance uniformity after boron diffusion, achieving high sheet resistance uniformity under high sheet resistance targets.

The application provides a kind of double-doped layer TOPCon cell structure and preparation method thereof, it is related to cell processing preparation technical field.The double-doped TOPCon cell structure includes monocrystalline silicon wafer, diffusion layer, passivation layer, front surface anti-reflection layer, front surface metal electrode are sequentially arranged in the front surface of monocrystalline silicon wafer, and tunneling layer, doped polysilicon layer, back surface anti-reflection layer and back surface metal electrode are sequentially arranged in the back surface of monocrystalline silicon wafer, the doped layer includes the first diffusion doped layer located in the front surface of silicon wafer and the second epitaxial doped layer between the first diffusion doped layer and the front surface metal electrode.The application overcomes the deficiencies of prior art, can guarantee the thickness of P-type doped layer of metal contact area, effectively shield metal area recombination, and reduce metal area contact resistance;At the same time, it can reduce the doping concentration and junction depth of non-metal area, reduce Auger recombination and parasitic light absorption of non-metal area;Therefore, it can effectively improve the conversion efficiency of TOPCon cell.

The invention discloses a solar cell and a preparation method thereof, and a photovoltaic module, the solar cell comprises a silicon substrate and a PN junction layer arranged on the surface of the silicon substrate, the PN junction layer is provided with a first suede structure, the first suede structure comprises a first spire area and a first tower bottom area, and the junction depth D1 of the first spire area is greater than or equal to the junction depth D2 of the first tower bottom area. According to the invention, carrier recombination can be reduced, and the photoelectric conversion efficiency of the solar cell can be effectively improved.

The invention discloses a Hall device and a manufacturing method thereof. The device comprises a substrate and an isolation structure, and an active region pattern with a rotational symmetry structure is defined; a deep active region formed by diffusion of the side wall of the deep trench is arranged in the deep trench, and a connecting well region for guiding carriers to go deep, symmetrically distributed contact regions and a surface isolation region are arranged on the surface layer of the deep trench. According to the invention, an ultra-deep active region (15-25 [mu] m) is realized through a deep groove and a side wall diffusion process, and the sensitivity of the device is remarkably improved; x-direction and Y-direction magnetic fields can be monitored at the same time by using a rotational symmetric structure, and offset voltage is effectively eliminated in cooperation with a rotating current method, so that the problems of low sensitivity and difficulty in offset voltage correction caused by junction depth of an existing vertical Hall device are solved.

A solar cell includes: an N-type silicon wafer, where a front surface of the N-type silicon wafer is provided with a doped region containing boron, the doped region is divided into a lightly doped region and a heavily doped region, a boron concentration of the lightly doped region is less than a boron concentration of the heavily doped region, a junction depth of the lightly doped region is less than a junction depth of the heavily doped region; a passivation layer and a first anti-reflection layer that are sequentially stacked on the front surface of the N-type silicon wafer. An area of a surface of the first anti-reflection layer corresponding to the heavily doped region is provided with an electrode. The electrode extends through the first anti-reflection layer and the passivation layer, and is in an ohmic contact with the heavily doped region.

The application provides a PN junction preparation method of a solar cell and the solar cell, and relates to the technical field of solar photovoltaics. The method is applied to a textured surface of a silicon wafer, and comprises the following steps: first diffusion of a dopant on the textured surface, wherein the dopant is different from the conductive type of the silicon wafer; oxidation of the textured surface after the first diffusion to obtain an oxide layer; second diffusion of the dopant on the oxide layer, so that the dopant remains in the oxide layer; and pushing the diffused dopant in the oxide layer, so that in the two diffusion processes on the textured surface of the silicon wafer, more dopant enters the silicon wafer from the top of the peak in the first diffusion, and less dopant enters the silicon wafer from the bottom of the valley, and the second diffusion is opposite, so that the total amount of the dopant entering different positions of the silicon wafer is relatively average, and the junction depth uniformity of the PN junction of the silicon wafer is effectively ensured.

This application relates to the field of semiconductor silicon wafer manufacturing technology, and particularly to a boron-aluminum diffusion source and its preparation method. A boron-aluminum diffusion source has a metal impurity content of <20 ppm and a sodium ion content of <15 ppm. The components of the boron-aluminum diffusion source include 15-35% silicate ester, 2-5% water, 25-35% lower alcohols, 25-35% ethers, 2-12% boron source, 5-20% aluminum source, 0.01-1% acid, and 0.01-0.5% dispersant. The preparation method includes: 1) mixing and dissolving the boron source, aluminum source, and ether; 2) mixing the silicate ester with water for hydrolysis and condensation; and 3) blending. This application controls the metal impurity content in the boron-aluminum diffusion source to <20 ppm, and the sodium content to <15 ppm, which can effectively improve the TRR value of the chip's electrical parameters. Controlling the metal impurity content and sodium content in the boron-aluminum diffusion source can also improve the problem of uneven and rough film formation during the baking process, resulting in a product with lower sheet resistance and PN junction depth dispersion.

The application provides a metal-oxide semiconductor field effect transistor and a preparation method thereof. The metal-oxide semiconductor field effect transistor comprises an active region and a terminal region. A first field limiting ring and a second field limiting ring are prepared in an epitaxial layer located in the terminal region. The doping concentration of the doping ions in the second field limiting ring is greater than the doping concentration of the doping ions in the first field limiting ring. The junction depth of the second field limiting ring is less than the junction depth of the first field limiting ring. The second field limiting ring is set as a shallow-junction high-doping-concentration field limiting ring relative to the first field limiting ring, and the corresponding field oxide layer is set, so that the fixed charges and movable charges in the terminal region field oxide layer can be effectively shielded, the terminal region depletion layer is prevented from shrinking, the reliability of the device in a high-voltage scene is improved, the device withstand voltage is improved in combination with the first field ring, and the operation performance and operation stability of the device are simultaneously improved.

An LDMOS transistor can include: a semiconductor region; a body region of a second doping type, wherein the body region extends from an upper surface of the semiconductor region to an interior of the semiconductor region; a source region of a first doping type and a body contact region of the second doping type, where the source region extends from an upper surface of the body region to an interior of the body region; a drain region of the first doping type, wherein the drain region is located in the semiconductor region; a source electrode that is in contact with the body contact region and the source region; and where a junction depth of the body contact region is greater than a junction depth of the source region.

The invention provides a metal-oxide semiconductor field effect transistor and a preparation method thereof, the metal-oxide semiconductor field effect transistor in the method comprises an active region and a terminal region, and a first field limiting ring and a second field limiting ring are prepared in an epitaxial layer located in the terminal region. The doping concentration of doped ions in the second field limiting ring is larger than that of doped ions in the first field limiting ring, the junction depth of the second field limiting ring is smaller than that of the first field limiting ring, and the second field limiting ring is arranged to be a shallow-junction high-doping-concentration field limiting ring relative to the first field limiting ring and is arranged corresponding to the field oxide layer. Fixed charges and movable charges in a terminal region field oxide layer can be effectively shielded, shrinkage of a terminal region depletion layer is avoided, the operation reliability of the device in a high-voltage scene is improved, the voltage resistance of the device is improved in combination with the first field effect ring, and the operation performance and the operation stability of the device are improved at the same time.

The invention relates to a low-junction capacitance symmetric transient voltage suppressor diode and a preparation method thereof. The preparation method comprises the steps of silicon wafer cleaning, N-type doping, oxidation, photoetching, oxide layer removal, slotting corrosion, passivation, surface corrosion, electrode manufacturing, metal stripping and cutting. Wherein in the N-type doping step, POCl3 is used as a gas-phase phosphorus source, double-sided synchronous diffusion is carried out on a silicon wafer, and a shallow junction N-type region with the junction depth of 1.5-3.0 microns is formed; in the oxidation step, the silicon wafer with the shallow junction N-type region is subjected to high-temperature oxidation in an oxygen-containing atmosphere, phosphorus atoms are driven to be redistributed from the surface to the inside, a doping section with the phosphorus concentration gradually changing from the surface of the silicon wafer to the inside is formed, and a surface oxidation layer is synchronously grown. According to the preparation method disclosed by the invention, the junction capacitance is reduced, and the symmetry, the response speed and the pulse endurance capability of the bidirectional transient voltage suppression diode are improved by improving the doping uniformity.

This invention discloses a TOPCon battery and its fabrication method, belonging to the field of TOPCon battery technology. It includes a monocrystalline silicon wafer with a tunneling layer, a doped polycrystalline silicon layer, a back anti-reflection layer, and a back metal electrode sequentially disposed on its back side from the inside out. The doped polycrystalline silicon layer includes a first doped polycrystalline silicon region and a second doped polycrystalline silicon region. The first doped polycrystalline silicon region is in contact with the back metal electrode and is disposed on the surface of a groove. The tunneling oxide layer is relatively thin, and the inward junction depth is greater than that of the second doped polycrystalline silicon region. This effectively prevents electrode metal from penetrating into the junction region, reduces metal recombination current, and improves the battery's open-circuit voltage. Furthermore, the first doped polycrystalline silicon region has a larger contact area with the printing paste, reducing the battery's contact resistance. Simultaneously, the groove prevents the printing paste from widening outward, ensuring a high grid line aspect ratio, reducing grid line resistance, and thus improving the battery's fill factor.

This invention discloses a stepped cathode-emitter reverse blocking double-ended solid-state thyristor and its fabrication method. The double-ended solid-state thyristor has a four-layer PNPN structure, with Al electrodes on both the cathode and anode sides; the N on the cathode side... + The emitter has a stepped structure with n steps. Along the direction from the first step to the nth step, the junction depth increases with each step, and the concentration gradually decreases at the deeper junction. The emitter P on the anode side... + Doping concentration of 1×10 14 cm ‑3 ~1×10 21 cm ‑3 The depth is 35μm to 100μm, and there are tens of thousands of short-circuit points with diameters of 200μm to 300μm on the cathode side; when n is 3, the doping concentration of the first step is 1×10. 19 cm ‑3 ~1×10 21 cm ‑3 The junction depth is 12μm to 20μm, and the doping concentration of the second-stage step is 1×10⁻⁶. 17 cm ‑3 ~1×10 21 cm ‑3 Its junction depth is 17μm to 25μm, and the doping concentration of the third step is 8×10⁻⁶. 16 cm ‑3 ~1×10 21 cm ‑3 The junction depth is 21μm to 29μm. The stepped cathode-emitter RBDT increases the voltage drop at the nth step cathode by diffusing the cathode-emitter n times. This increases the turn-on area of ​​the RBDT chip under the same dv / dt trigger pulse, thereby increasing the di / dt withstand capability of the RBDT chip.

The utility model is applicable to the technical field of semiconductors, and provides a terminal structure of a high-voltage MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which comprises a highly-doped N-type substrate, a lowly-doped N-type drift region and a cellular region, and a core assembly is arranged in the cellular region; the terminal protection area surrounds the periphery of the cellular area; a plurality of grooves are formed in the terminal protection area, the grooves are filled with insulating materials, and the insulating materials are of gradient structures which are gradually thickened from the bottoms of the grooves to the tops of the grooves; according to the utility model, the optimization of electric field distribution and the double improvement of high-efficiency current transmission are realized, the low-doped N-type drift region is combined with the insulating material groove with the gradually thickened gradient structure in the terminal protection region, the electric field concentration is effectively reduced, the breakdown risk is avoided, and in addition, the service life of the terminal protection region is prolonged. The arrangement of the slowly changing junction P-type well region ensures the efficient transmission of current in the device, and through the smooth change of the doping concentration and the junction depth, the smooth transition electric field distribution is formed at the edge of the device, and the breakdown possibility is further reduced.

The invention discloses a boron diffusion process, which is improved on the basis of the boron diffusion process of the existing N-type TOPCON battery, and comprises the following steps of: before diffusion, spin-coating mask liquid on a non-metal region through patterning, and realizing gradient doping of the non-metal region and a metal region after boron diffusion; the non-metal contact area spin-coating mask liquid prevents boron atoms from diffusing to a non-designated area in the high-temperature diffusion process, and the problems that due to the fact that the deposition time of the non-metal contact area is too long, the boron atoms are excessively deposited on the surface of a silicon wafer, the surface boron concentration is too high, the junction depth is large, the concentration is too high, and over-doping is formed after follow-up diffusion driving are solved; excessive boron atom diffusion can be blocked, the surface boron concentration is reduced, the recombination rate is reduced, and the battery efficiency is improved.

The application relates to a semiconductor device and a preparation method thereof, wherein a nanosheet stack part of the semiconductor device comprises: a nanosheet stack part arranged on a substrate; wherein the nanosheet stack part comprises: a plurality of nanosheet-formed stacks, the nanosheets being formed of a semiconductor material; the nanosheet-formed stacks constitute a plurality of conductive channels; a surrounding gate surrounding the nanosheet stack part; and a source-drain region (SD) being a lightly-doped and steep source-drain extension region (SDE) at the junction with the nanosheet stack part. The application forms the SDE doping through an inclined ion injection after inner sidewall etching and before source-drain selective epitaxy, and then forms the SDE region which is steep, uniformly distributed and with a precisely controllable lateral junction depth after source-drain annealing, so that the effective channel length is effectively controlled and a complex in-situ doping epitaxy process is avoided.

The invention provides a method for improving the reliability of a laterally diffused metal oxide semiconductor. The method comprises the following steps: providing a P-type semiconductor substrate; defining a drift region and a well region in the substrate; carrying out ion implantation by adopting a P-type heavily doped element to define a P-type body region; defining a gate structure on the surface of the substrate; and defining a source-drain contact region. According to the invention, heavily doped elements such as indium, aluminum and the like are adopted to replace boron to carry out P-type body region injection, and the junction depth and transverse diffusion are effectively controlled and the length of a drift region is maintained by utilizing the low diffusion capability and steep doping characteristics of the elements; meanwhile, the surface electric field peak value is reduced, the electric field distribution is optimized, the hot carrier injection problem is relieved, and the reliability service life of the LDMOS device is remarkably prolonged.

The invention provides a shield gate transistor and a preparation method thereof, a chip and electronic equipment, and relates to the technical field of semiconductors, and the shield gate transistor comprises a substrate and an epitaxial layer located at the first side of the substrate; a first conductive type body region; the first conductive type body region is formed in the epitaxial layer from one side, deviating from the substrate, of the epitaxial layer; a second conductive type heavily doped region and a trench gate structure; the second conductive type heavily doped region is formed in the first conductive type body region from one side, deviating from the substrate, of the first conductive type body region; the trench gate structure is at least formed in the first conductive type body region from one side, deviating from the substrate, of the first conductive type body region; wherein the doping concentration in the second conductive type heavily doped region and / or the junction depth of the PN junction in the second conductive type heavily doped region are / is changed in a gradient manner along the extension direction of the trench gate structure. According to the technical scheme, the starting risk of the parasitic triode is low, and the saturation current density of the device is reduced.