95 results about "Junction depth" patented technology

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The invention belongs to the technical field of solar cell manufacturing, and provides a step temperature cycle propulsion boron diffusion process and application thereof. The boron diffusion technology comprises the steps that a silicon wafer is placed in boron diffusion equipment, pre-oxidation, pre-deposition and stepped temperature circulation boron diffusion propelling are sequentially carried out on the silicon wafer, and the stepped temperature circulation boron diffusion propelling procedure comprises an initial stage, a middle stage and a final stage which are sequentially carried out. A circulation mode of heating oxygen-free boron expansion and pushing junction and then cooling oxygen-filled boron expansion and pushing junction is adopted in each stage for multiple times of circulation, and the heating temperature and the cooling temperature of each stage are optimized, so that a boron expansion doping layer is formed on the surface of the silicon wafer. According to the boron diffusion process, the oxidation temperature can be reduced, the concentric circle defect can be eliminated, the junction depth and the surface doping concentration of boron diffusion doping can be increased, the uniformity of boron diffusion doping can be improved, the FF, Jsc, Uoc and Eta of the battery can be further improved, the thermal budget can be reduced, and the service life of equipment can be prolonged.

The invention belongs to the related technical field of semiconductor doping, and discloses a method for acquiring a second harmonic signal of non-uniform ion implantation doping concentration and an application of the second harmonic signal of the non-uniform ion implantation doping concentration. Determining refractive indexes and absorption coefficients of different depth positions of the ion implantation doping sample under a specific laser wavelength based on an optical property distribution model in the ion implantation doping sample; s2, calculating fundamental frequency light electric field distribution in the doped sample based on the obtained refractive index and absorption coefficient; s3, calculating the polarization intensity and effective second-order polarizability of the non-uniform doped ion implantation sample based on the simplified bond hyperpolarizability model and the fundamental frequency photoelectric field distribution; and S4, calculating far-field second harmonics of the corresponding layers at a predetermined observation angle based on the obtained polarization intensity or effective second-order polarizability of each layer, and carrying out integration on the far-field second harmonics corresponding to all layers to obtain the total intensity of the second harmonics of junction depth far-field radiation. According to the invention, the problem that the measurement sensitivity and repeatability are reduced is solved.

The invention discloses a solar cell boron emitter and a preparation method and application thereof, and belongs to the field of solar cells, after a monocrystalline silicon wafer is selected, cleaned and textured, a first BSG layer, a silicon oxide mask layer and a second BSG layer are sequentially deposited on the front surface of the silicon wafer, and then annealing treatment is carried out; wherein the boron atom concentration of the first BSG layer is lower than that of the second BSG layer, and the oxygen atom concentration of the first BSG layer is higher than that of the second BSG layer. The BSG layer with low-concentration boron atoms and high-concentration oxygen atoms, the silicon oxide mask layer and the BSG layer with high-concentration boron atoms and low-concentration oxygen atoms are sequentially deposited on the silicon wafer, and after annealing treatment, the surface of the formed boron emitter has high boron doping concentration and can be in better contact with a metal electrode; and meanwhile, the junction depth of the boron emitter is relatively shallow, defects caused by internal boron doping can be repaired due to existence of high-concentration oxygen atoms, and compounding of a silicon substrate is reduced.

The invention discloses a planar SiC MOS (Metal Oxide Semiconductor) gate-controlled thyristor device based on an epitaxial surface and a manufacturing method thereof, effectively avoids the problem of using a triple ion implantation process traditionally by ingeniously introducing an n-type epitaxial layer, and utilizes the advantages of high growth speed, low material defect, good process stability and the like of an epitaxial growth technology to improve the performance of the device. The semiconductor layer with lower surface defect density can be obtained, the mobility of channel carriers is effectively improved, and the working performance of the device is improved. By introducing the n-type epitaxial region, the separation design of the p-type ion implantation well region and the n-type ion implantation well region is realized, the doping concentration can be controlled more accurately by the surface structure of the epitaxial layer, and the deeper junction depth of the p-type ion implantation well region and the deeper base region width of the n-type ion implantation well region can be controlled and realized. The design difficulty that the ion implantation junction depth of the device needs to exceed 1 [mu] m is reduced, and the problem that the original lattice structure of the material is damaged by SiC high-temperature ion implantation is avoided.

The invention discloses a Schottky diode and a preparation method thereof, the Schottky diode comprises a heavily doped N-type substrate layer and a lightly doped N-type epitaxial layer formed on the upper surface of the heavily doped N-type substrate layer, the upper part of the lightly doped N-type epitaxial layer is provided with a groove structure, the groove structure is filled with doped polycrystalline silicon, the doped polycrystalline silicon is polycrystalline silicon doped with P-type impurities, and the doped polycrystalline silicon is doped with P-type impurities. Doped polycrystalline silicon is used as a solid phase diffusion source, and solid phase diffusion is carried out on the doped polycrystalline silicon to diffuse P-type impurities to the lightly doped N-type epitaxial layer, so that P-type regions are formed on the side wall and the bottom of the groove structure. According to the Schottky diode and the preparation method thereof, the P-type region is formed on the side wall and the bottom of the groove structure, the P-type region and the lightly doped N-type epitaxial layer form the depletion region, a good three-dimensional heat dissipation channel is formed, the heat dissipation burden is reduced, the P-type region is formed through solid-phase diffusion, and compared with ion implantation, the junction depth is easier to control.

The present invention provides a stacked doping source structure, a related high-quality emitter and a preparation method therefor. The stacked doping source structure comprises a nanometer silicon oxide layer, a doped silicon oxide layer, and a doping source layer that are stacked on the front surface of a crystalline silicon substrate; the doped silicon oxide layer is doped with boron or phosphorus atoms; the material of the doping source layer is selected from among one of boron / phosphorus-doped amorphous silicon, carbon-doped boron / phosphorus-doped amorphous silicon, nitrogen-doped boron / phosphorus-doped amorphous silicon, and carbon-nitrogen co-doped boron / phosphorus-doped amorphous silicon. According to the present invention, a front doping source is composed of nanometer silicon oxide, doped silicon oxide, and boron / phosphorus-doped amorphous silicon, so that the doping source structure has both a strong laser absorption capability and high boron / phosphorus concentration, thereby being conducive to reducing the laser power and illumination time required by the laser doped selective emitter technology, reducing surface recombination without losing a junction depth and sheet resistance, improving the passivation effect, and thus further prompting the improvement of the cell efficiency.

The application provides a method for detecting the effective junction depth of a tellurium-cadmium-mercury chip PN junction, and belongs to the technical field of semiconductors. The method comprises the following steps: selecting a tellurium-cadmium-mercury chip which has been formed through an ion implantation and annealing junction process and has been passivated; dividing the ion implantation area of the tellurium-cadmium-mercury chip into multiple regions, removing the passivation layer in each region and part of the ion implantation area below the passivation layer, and forming multiple contact holes arranged in a preset depth gradient; growing a metal electrode on each contact hole; measuring the voltage-current curve of each metal electrode at different etching depths; and determining the corresponding PN junction depth as the effective junction depth of the tellurium-cadmium-mercury chip when the voltage-current curve changes from a Schottky curve to a linear curve. The application is the same as the original chip manufacturing process of tellurium-cadmium-mercury, can be applied to the process production process of a tellurium-cadmium-mercury infrared detector, and can monitor the effective junction depth of the tellurium-cadmium-mercury after ion implantation in real time.

Structures and formation methods of a semiconductor device are provided. The method includes forming a first dummy gate structure across a first fin in a first transistor region of a semiconductor substrate and a second dummy gate structure across a second fin in a second transistor region of the semiconductor substrate. The method also includes selectively introducing atomic or ionic species into the second fin on opposite sides of the second dummy gate structure and etching portions of the first and second fins, so as to form first and second recesses. Each recess is in the respective fin on a side of the respective dummy gate structure. The first recess has a different depth than the second recess. The method further includes forming first and second source / drain features in the first and second recesses, respectively.

This invention discloses a method, substrate, and system for detecting laser beam-induced current in the PN junction region profile of an InGaAs photodetector, belonging to the field of semiconductor optoelectronic device characterization technology. The method includes: cleaving a chip with completed front-side processing along the natural cleavage surface of InP to obtain a smooth profile; fixing the chip with the profile facing upwards onto a composite sapphire bonding substrate, and extracting electrodes through conductive silver paste and ultrasonic bonding; performing a two-dimensional step-scan of the profile using a 900-1100nm laser, simultaneously acquiring photocurrent signals to obtain a two-dimensional photocurrent distribution map of the profile; and quantitatively extracting junction depth, lateral diffusion width, and uniformity parameters based on the photocurrent peak position. This invention can directly obtain the longitudinal two-dimensional electrical activity distribution of the PN junction region, effectively avoiding interference between the surface passivation layer and the InP cap layer, and achieving a visual assessment of junction depth, lateral diffusion, and defects, providing a realistic and efficient detection method for device process optimization.

According to the silicon-based PIN photodiode, the manufacturing method and the electronic device provided by the invention, the FZ single crystal is adopted as the substrate, and the doped region is formed in an ion implantation and annealing mode, so that the junction depth and the concentration can be effectively controlled. And thinning the silicon wafer by adopting a Taiko back thinning process. The photosensitive area adopts a shallow junction and deep junction combined structure, the shallow junction can increase the blue light absorption rate, and the deep junction forms ohmic contact. The anti-reflection layer adopts a silicon dioxide and silicon nitride double-layer structure, so that the surface stress of silicon / silicon nitride can be effectively relieved, and the reliability is improved. The cut-off region N + and the back N + can reduce dark current, and back metallization can form a back cathode.

The invention provides a Hall device and a manufacturing method thereof, and the manufacturing method comprises the steps: firstly, defining a region of a functional layer region of the Hall device on the surface of a high-resistance substrate through a photoetching technology, then carrying out the N-type and P-type ion implantation of the high-resistance substrate at the same time, and carrying out the high-temperature long-time thermal process, a uniform N-type doped device main function layer region and a P-type doped auxiliary function region located at the bottom of the device main function layer region are formed in a high-resistance substrate, and finally a well region and a first heavily doped region located in the well region are formed respectively. According to the invention, no extra photomask needs to be added, the photomask is injected by using the traditional Hall device function layer, N-type and P-type foreign ions are injected at the same time, the junction depth of the Hall device function layer is ensured to be less than or equal to 1.5 microns by adjusting the injection energy and dosage of the two foreign ions, the N-type foreign ions are adjusted to be injected with low doping concentration, the carrier mobility is improved, and the performance of the Hall device is improved. The sensitivity of the Hall device is improved, and the manufacturing difficulty of the shallow junction Hall device is reduced.

The invention discloses a channel mobility testing method, a channel mobility testing structure and a manufacturing method of the channel mobility testing structure. The channel mobility test method comprises the following steps: providing a semiconductor device; determining the resistance between the source electrode and the drain electrode of each semiconductor device by applying a test voltage to the source electrode, the drain electrode and the gate electrode structure of at least two different semiconductor devices; wherein the junction depths of the JFET regions of at least part of the semiconductor devices in the at least two different semiconductor devices are different; the junction depth of the JFET region is the size of the JFET region in the direction from the first surface to the second surface; and determining the channel mobility of the semiconductor device according to the resistance between the source electrode and the drain electrode of each semiconductor device and the junction depth of the JFET region of each semiconductor device. According to the embodiment of the invention, the measurement of the channel field effect mobility can be realized, the measurement mode is simple, and the measurement efficiency is high.

The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device based on a SiC material and a manufacturing process of the semiconductor device. The device comprises an N + type SiC substrate, an N-type composite buffer layer which is arranged on the substrate and has a concentration gradient, an N-type drift region which is arranged on the buffer layer, and an active region which is composed of a first conduction type region and a second conduction type ion implantation region. The innovation lies in that a composite buffer layer structure is adopted to effectively suppress dynamic avalanche and optimize the reverse recovery characteristic, and meanwhile, a composite structure of a junction termination extension region and a field limiting ring with shallower junction depth is integrated in a terminal region, so that the process complexity is simplified on the premise of ensuring high breakdown voltage. According to the manufacturing process, impurity activation of the active region and the terminal region is synchronously completed through two times of ion implantation and one time of high-temperature annealing, and the manufacturing process is completely compatible with an existing SiC plane process platform. The device realizes excellent compromise between reverse recovery charge and forward voltage drop, and has the characteristics of superspeed, soft recovery, low loss and high reliability.

The invention relates to the field of photo-transistors, in particular to a high-CTR and high-speed photo-transistor based on layout optimization and a manufacturing method thereof.The high-CTR and high-speed photo-transistor comprises a semiconductor substrate, and an N-type epitaxial layer, a P-type base region and an N-type emitter region are sequentially formed on the semiconductor substrate; the P-type base region comprises a photoelectric sensing region and a base electrode main body which are independently arranged, the photoelectric sensing region is used for receiving optical signals and generating current carriers, the base electrode main body and the N-type emission region form a PN junction, and the node depth and the doping concentration of the base electrode main body can be independently adjusted according to beta value design requirements; the photoelectric sensing area and the base electrode main body are independently arranged, the section depth and the doping concentration of the base electrode main body can be flexibly adjusted according to beta value design, the problem that the section depth of a base electrode in a traditional shared structure is limited by photoelectric conversion efficiency is avoided, CTR is obviously improved, parameter stability is higher, and production efficiency is improved.

The application relates to the technical field of semiconductors, in particular to a SiC JFET device with improved avalanche capability and a manufacturing method thereof. The source region and the gate region are simultaneously arranged in a groove, and the depth of the second-type doped region of the source region is different from that of the second-type doped region of the gate region, wherein the junction depth of the second-type doped region of the source region is deeper than that of the second-type doped region of the gate region, so that the maximum electric field is at the junction edge of the second-type doped region of the source region in the off state, thereby making the avalanche current enter the source electrode through the ohmic contact of the source region without passing through the gate electrode, and the reliability of the avalanche is ensured.

The present invention discloses a floating field-limiting ring power device based on dielectric positioning and a preparation method thereof, which includes a device main body, a high-K dielectric trench region, and a P-type floating field-limiting ring; the device main body includes an N-type doped semiconductor drift region; the high-K dielectric trench regions are arranged equidistantly at the top center of the semiconductor drift region, and each high-K dielectric trench region includes a groove and a high-K dielectric filled in the groove; an active layer located between the high-K dielectric trench regions forms a semiconductor island region; the semiconductor island region is formed into a P-type floating field-limiting ring through P-type doping, and the junction depth of the P-type floating field-limiting ring is greater than the depth of the high-K dielectric trench region. The groove is a strip-shaped groove, a mesh groove, a rectangular groove, or the like. The P-type floating field-limiting ring of the present invention is positioned based on the dielectric groove, which can reduce process steps such as masking. The high-K dielectric deposited in the groove can effectively modulate the surface electric field and avoid the influence of surface charges on the P-type floating field-limiting ring, thereby improving the breakdown voltage. At the same time, the concentration of the drift region is increased, and the on-resistance of the device is reduced.

The present disclosure relates to a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: forming a hard mask on a main surface of a wafer; performing active region photolithography and etching, and removing the hard mask at a position where a field oxide layer needs to be formed; forming the field oxide layer; forming a patterned photoresist layer on the main surface, wherein the photoresist layer covers a position where no drift region needs to be formed; and performing drift region implantation by using the photoresist layer as an implantation blocking layer, wherein ions implanted during drift region implantation pass through the hard mask and the field oxide layer and enter the wafer. In the present disclosure, during drift region implantation, the implanted ions at the edge of the field oxide layer are blocked by using the hard mask, so as to avoid excessive PN junction depth and excessively high ion doping concentration at this position. Rapid depletion of the implanted ions in a JFET region at this position is achieved, thereby reducing the electric field strength at this position, and optimizing and improving the voltage withstand and reliability of the device.

The application relates to a semiconductor device structure and a preparation method thereof, which comprises the following steps: a substrate structure; an epitaxial structure of a first conductive type on the front surface of the substrate structure; a groove structure comprising a first groove and a second groove; a first ion implantation region of a second conductive type in the epitaxial structure and below the bottom of the first groove; a second ion implantation region of the second conductive type in the epitaxial structure and below the bottom of the second groove; an ohmic contact layer on the bottom of the first groove; and a first electrode in the first groove, in the second groove and on the exposed surface of the epitaxial structure away from the substrate structure. The semiconductor device structure of the application adopts a groove type structure, solves the problem of shallow ion implantation depth of the second conductive type in the epitaxial structure, increases the junction depth of a PN junction, improves the shielding capacity of the PN junction to the electric field of a Schottky contact surface during reverse blocking, and improves the reverse recovery speed.

An insulated gate bipolar transistor and a preparation method thereof, and an electronic device. The insulated gate bipolar transistor includes: a drift region; an electrode structure on one side of the drift region; and an electric field stop layer arranged on one side of the drift region away from the electrode structure. The electric field stop layer includes a first sublayer and a second sublayer laminated together. The first sublayer is arranged close to the drift region. A junction depth of the first sublayer is greater than a junction depth of the second sublayer. A peak value of a doping concentration of the first sublayer is less than a peak value of a doping concentration of the second sublayer. A slope of a doping concentration curve of the first sublayer is less than a slope of a doping concentration curve of the second sublayer.

The application provides a TOPCon cell, comprising: a single crystal silicon wafer; an inner expansion layer arranged on the back surface of the single crystal silicon wafer; a doped polysilicon layer arranged below the inner expansion layer; the doped polysilicon layer comprises: a first doped polysilicon region and a second doped polysilicon region, the doping concentration of the first doped polysilicon region is higher than that of the second doped polysilicon region; the inner layer comprises: a first inner expansion region and a second inner expansion region, the position of the first inner expansion region corresponds to the position of the first doped polysilicon region, and the junction depth of the first inner expansion region is greater than that of the second inner expansion region. The TOPCon cell provided by the application has a specific structure, which can ensure the thickness and concentration of the doped polysilicon in the metal contact area, avoid the destruction of the tunneling oxide layer in the slurry sintering process, reduce the recombination current and the contact resistance, and at the same time, reduce the light parasitic absorption of the non-metal area, especially the free carrier absorption.

The present invention provides a semiconductor terminal structure with lateral variable doping and a preparation method thereof. The terminal structure includes an N-type semiconductor drift region, and the N-type semiconductor drift region includes a P-type semiconductor main junction, a P-type semiconductor field limiting ring, a P-type semiconductor VLD region, and an N+-type semiconductor field limiting ring. One side of the P-type semiconductor field limiting ring is connected to the P-type semiconductor VLD region, and the junction depth of the P-type semiconductor VLD region is greater than that of the P-type semiconductor main junction. Compared with the traditional semiconductor terminal structure, the present invention can achieve a more stable breakdown voltage, a lower leakage level, and a shorter terminal size, and is not easily affected by the surface fixed charges introduced by the manufacturing process line.

The invention discloses a solar cell and a photovoltaic module, and relates to the field of photovoltaic technology, doping is carried out on a light-facing surface of a semiconductor substrate to form a first semiconductor layer, and the first semiconductor layer is provided with a first region and a second region; the passivation layer at least covers one side, deviating from the semiconductor substrate, of the first semiconductor layer; a first barrier layer and a first grid line, the first grid line is conductively connected with the first barrier layer, and the first grid line and the first barrier layer are arranged on one side, departing from the semiconductor substrate, of the first region; at least a part of the first barrier layer passes through the passivation layer and is conductively connected with at least a part of the first region; the surface doping concentration of the first region is a, the surface doping concentration of the second region is b, and a / b is greater than or equal to 2 and less than or equal to 20; the junction depth of the first region is c, the junction depth of the second region is d, and c-d is larger than or equal to 0.2 micrometer and smaller than or equal to 4 micrometers. Therefore, the manufacturing cost of the solar cell is reduced while the power generation efficiency of the solar cell is ensured.

The utility model is suitable for the field of photovoltaic technology, and provides a solar cell, a cell assembly and a photovoltaic system, the solar cell comprises a silicon substrate, the silicon substrate is provided with a back surface and a front surface which are oppositely arranged; the diffusion layer is positioned in a first region on the back surface of the silicon substrate; the doping layer is positioned in a second region on the back surface of the silicon substrate, and the doping layer and the diffusion layer have opposite polarities; two opposite surfaces of the tunneling layer are respectively in contact with the diffusion layer and the doping layer; the first electrode is communicated with the diffusion layer, the second electrode is communicated with the doping layer, and the first electrode is not communicated with the doping layer; the connection depth of the first electrode extending into the diffusion layer is smaller than the connection depth of the second electrode extending into the doping layer, and the contact area of the first electrode extending into the diffusion layer is larger than the contact area of the second electrode extending into the doping layer. The hot spot risk can be reduced, the overall performance of the solar cell can be improved, and particularly the charge collection efficiency and the current transmission stability of the solar cell can be improved.

A pixel includes a semiconductor substrate, a photodiode region, a floating diffusion region, and a dielectric layer. The substrate has a top surface that forms a trench, the trench is lined by the dielectric layer, and has a trench depth relative to a planar region of the top surface. The photodiode region is in the substrate and includes a bottom photodiode portion under the trench and a top photodiode portion adjacent the trench, the top photodiode portion abutting the bottom photodiode portion and extending toward the planar region to a photodiode depth that is less than the trench depth. The floating diffusion region is adjacent the trench and has a junction depth that is less than the trench depth. A top region of the dielectric layer is between the planar region and the junction depth. A bottom region of the dielectric layer is between the photodiode depth and the trench depth and is thicker than the top region.

The invention relates to the technical field of semiconductor manufacturing. A diffusion junction depth calculation method comprises the following steps that 1, a to-be-tested sample is fixed through a grinding wheel machine clamping plate, and one side of the polishing face of the to-be-tested sample faces a grinding wheel; a testing groove is ground in the surface of the sample to be tested through a grinding wheel, the transverse end face of the testing groove is rectangular, and the longitudinal end face of the testing groove is arc-shaped; step 2, dripping a mixed solution of hydrofluoric acid and nitric acid on the surface layer of the ground test tank, and dyeing for 10-15 seconds; 3, washing the surface of the sample to be detected for 30-40 seconds by using pure water, and wiping and removing water stains on the surface of the sample by using dust-free cloth; and 4, measuring the parameter size of the vertical projection surface of the test groove under the microscope, measuring the outer diameter size of the grinding wheel, and calculating the diffusion junction depth according to the right triangle Pythagorean theorem.

The invention provides a three-dimensional magnetic field monitoring device and a manufacturing method thereof. The device comprises a horizontal Hall device arranged in a semiconductor substrate, at least one vertical Hall device and an isolation structure for isolating the horizontal Hall device and the vertical Hall device. Wherein the active region of the horizontal Hall device is a first doped region with a first conduction type, the active region of the vertical Hall device is a second doped region with the same conduction type, and the junction depth of the second doped region is greater than that of the first doped region. The invention further discloses a corresponding manufacturing method. The three-dimensional magnetic field monitoring module which is high in performance, low in noise and good in isolation can be economically and efficiently integrated on a single chip without adding additional photoetching steps by ingeniously utilizing the existing doping layers with different depths in a standard BCD process platform, and the three-dimensional magnetic field monitoring module has the advantages of being good in process compatibility, low in cost and high in integration degree.

The application discloses a metal silicide forming method, which comprises the following steps: providing a substrate, forming a gate dielectric layer on the substrate, forming a gate electrode on the gate dielectric layer, forming a side wall on the periphery of the gate electrode, and forming a heavily doped region in the substrate on both sides of the side wall; forming a first metal layer by sputtering deposition through a first target material, the first target material comprising nickel and platinum, and the first metal layer covering the exposed areas of the substrate, the gate dielectric layer, the gate electrode and the side wall; forming a second metal layer on the first metal layer by sputtering deposition through a second target material, the second target material comprising nickel and platinum, and the content of platinum in the second target material being higher than that in the first target material; and performing heat treatment to form metal silicide in the gate electrode and the heavily doped region. The first metal layer and the second metal layer are sequentially deposited on the substrate, the content of platinum in the target material used for depositing the first metal layer is less than that in the target material used for depositing the second metal layer, the silicon loss and the junction depth are reduced, and the reliability and yield of the device are improved.

This invention provides a method for treating the surface of silicon carbide, comprising growing an oxide layer on the surface of a silicon carbide substrate; depositing a doped layer on the oxide layer surface using an atomic layer deposition apparatus; and vacuum annealing the silicon carbide substrate containing the doped layer and oxide layer at a set vacuum level using an annealing furnace. This significantly reduces the interface state density between silicon carbide and the oxide layer, thereby improving the inversion channel electron mobility of silicon carbide power devices and avoiding any impact on the performance of the silicon carbide power devices. This invention uses an annealing furnace to perform high-temperature annealing on the silicon carbide substrate containing the doped layer and oxide layer, avoiding the introduction of new impurities during the annealing process, reducing defects in the oxide layer, improving the quality of the oxide layer, and simultaneously allowing precise control of the junction depth of phosphorus atom diffusion through temperature and time.

The invention belongs to the field of power semiconductors, and particularly relates to an asymmetric GCT chip which comprises a P + transparent emission anode, an N-base region, a P base region, a P + base region and an N + emission region partially embedded in the P + base region, or an N'buffer layer is arranged between the P + transparent emitting anode region and the N-base region; the center of the N + emitter region is provided with a groove, and the groove is filled with a cathode metal layer and is led out. According to the asymmetric GCT chip provided by the invention, a comb structure with a groove is adopted, under the same chip size, the effective area of a cathode is increased, the doping concentration of a P + base region below an N + emitter region is reduced, the opening performance of the chip is improved, the junction depth of a J3 junction is basically kept unchanged, and the turn-off capability is not reduced while the through-current capability is improved.