18 results about "Heterojunction bipolar transistor" patented technology

This invention relates to the field of semiconductor technology, disclosing a semiconductor structure and its fabrication method, and a heterojunction bipolar transistor, comprising: forming a germanium-silicon layer on one side of a substrate layer, and forming a polysilicon layer on the side of the germanium-silicon layer facing away from the substrate layer; patterning the substrate layer and the germanium-silicon layer to obtain a predetermined collector region based on the substrate layer and a base region based on the germanium-silicon layer; performing ion implantation on the side of the predetermined collector region facing away from the base region to form a collector region; exposing a portion of the surface of the base region on the side of the collector region; patterning the polysilicon layer to form an emitter structure; and the width of the collector region being less than or equal to the width of the emitter structure. This invention can reduce the lateral dimensions of the device, increase integration density, reduce parasitic capacitance and resistance, and also improve the reliability of the collector region, ensuring that the doping concentration distribution of the collector region is within the target range.

The present disclosure relates to bipolar transistors. The present disclosure relates to semiconductor structures, and more particularly to heterojunction bipolar transistors and methods of manufacture. The structure includes a first transistor having an inner base, an outer base, and an emitter, and a second transistor having an inner base, an outer base, and an emitter. The outer base of the first transistor and the outer base of the second transistor have a common outer base layer having a first dopant type for the first transistor and a second dopant type for the second transistor.

The application provides a heterojunction bipolar transistor and a power amplifier. The heterojunction bipolar transistor comprises a substrate and a base mesa arranged on the substrate. The base mesa comprises a collector layer and a base layer arranged on the collector layer, and the base layer comprises a first side and a second side opposite to the first side. The heterojunction bipolar transistor further comprises an emitter layer arranged on the base layer, a base electrode arranged on the substrate and connected to the base layer, a dielectric layer arranged on the base electrode, and a conductive component arranged on the dielectric layer. A first through hole is formed in the first side of the base layer in the dielectric layer, and a second through hole is formed in the second side of the base layer in the dielectric layer. The conductive component is connected to the base electrode through the first through hole and the second through hole. By adding a new signal input end to the base end to reduce the base resistance, the gain performance of the heterojunction bipolar transistor and the power amplifier at a higher operating frequency is improved.

This invention provides a heterojunction bipolar transistor and its manufacturing method. A first-conductivity InGaP emitter layer (layers 1 to m) is formed on a GaAs base layer of a second conductivity type. Each InGaP emitter layer contains In... y Ga 1‑y P, and y decreases layer by layer from the first InGaP emitter layer to the mth InGaP emitter layer, m≥3 and is an integer. This results in a gradual bandgap difference between the materials of the first to mth InGaP emitter layers and the P GaAs base layer, which effectively reduces the barrier peak at the InGaP / GaAs heterojunction, avoids the turn-on voltage Vbe from becoming high when the HBT is working, and improves the device performance.

The present disclosure relates to semiconductor structures, and more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure comprises: a sub-collector region; a collector region over the sub-collector region, the collector region having a first semiconductor material including a polysilicon material and a single crystal semiconductor material over the sub-collector region, and a second semiconductor material over the single crystal semiconductor material; a diffusion region in the first semiconductor material; an emitter region over the collector region; and a base region adjacent to the emitter region.

A semiconductor device includes a heterojunction bipolar transistor (HBT) having a collector, a base, and an emitter. The base includes a monocrystalline base layer, including silicon-germanium, on the collector, and an extrinsic base layer, including polycrystalline silicon, extending partway over the monocrystalline base layer. The base further includes a base link, including polycrystalline silicon-germanium, connecting the monocrystalline base layer to the extrinsic base layer. An emitter spacer, of dielectric material, laterally separates the emitter from the extrinsic base layer. The HBT has a spacer-extrinsic base vertical offset between a bottom of the emitter spacer and a bottom surface of the extrinsic base layer adjacent to the emitter spacer. The emitter spacer has a bottom width at a bottom of the emitter spacer. A sum of the spacer-extrinsic base vertical offset and the bottom width of the emitter spacer is greater than the thickness of the monocrystalline base layer.

The present application belongs to the technical field of heterojunction bipolar transistor, and particularly relates to a preparation method of a heterojunction bipolar transistor epitaxial wafer. The present application provides a preparation method, which is prepared in a MOCVD device, wherein the small-dish supporting gas of the MOCVD device is changed to hydrogen and nitrogen before growth of a base region, and the base region is grown after rapid cooling by 20-30 DEG C; after growth of the base region, the small-dish supporting gas is changed to argon and nitrogen, and the emitter layer is grown after rapid heating by 20-30 DEG C. The present application rapidly changes the temperature of the surface of the epitaxial wafer by changing the small-dish supporting gas, and the surface temperature of the epitaxial wafer is shown in Fig. 2, so that the rapid transformation of the temperature of the collector region and the base region, and the temperature of the base region and the emitter region is well realized, that is, the quality of the base region epitaxial layer is not affected, and the quality of the epitaxial layer interface is not affected.

A heterojunction bipolar transistor device includes a collector region, a base region, and an emitter region. The collector region has a composition of GaAs. The base region is disposed on the collector region. The emitter region is disposed on the base region and has a composition of InGaP. The base region includes a gradient layer that has a composition of In(x)Ga(1−x)As(1−y)Sb(y), where each of a value of x and a value of y gradually increases or decreases between a base-collector interface of the base region and the collector region and a base-emitter interface of the base region and the emitter region. An increasing or decreasing direction of the value of x and an increasing or decreasing direction the value of y are opposite to each other.

An electro-optic device comprising a waveguide (WG)-device configured as an electro-absorption modulator (EAM) and electronics comprising an EAM driver. The electro-optic device comprising: a semi-insulating (SI) indium phosphide (InP) substrate; an epitaxial layer stack formed on the SI:InP substrate comprising a first plurality of semiconductor layers forming InP heterojunction bipolar transistors of the electronics and a second plurality of semiconductor layers structured to form a PIN waveguide of the EAM, the PIN waveguide comprising: an n-layer structure and a p-layer structure; an i-region comprising optical material located between the n-layer structure and the p-layer structure; the n-layer structure and the p-layer structure configured to optical confine one or more modes of an optical signal configured to propagate through the i-region; and at least one of the n-layer structure and the p-layer structure comprises a mode extending layer.

The application discloses a radio frequency integrated circuit structure, a heterojunction bipolar transistor and a preparation method thereof. The radio frequency integrated circuit structure comprises a collector epitaxial layer, a base step, a surface passivation layer and a base metal. The collector epitaxial layer is provided with an active region and an isolation region. The base step is arranged on the collector epitaxial layer and located in the active region. The surface passivation layer covers the base step and the collector epitaxial layer. The surface passivation layer is provided with a first windowing position and a second windowing position. The first windowing position exposes the base step. The second windowing position exposes the collector epitaxial layer located in the isolation region. The base metal is arranged on the surface passivation layer and located on the surface and the sidewall of the base step and extends to the isolation region. The first end of the base metal forms an ohmic contact with the base step. The second end of the base metal is in contact with the collector epitaxial layer. The application can effectively improve the adhesion reliability of the base metal without significantly changing the existing device structure and standard process flow, so as to balance high performance, high reliability and process compatibility.

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a first transistor having an intrinsic base, an extrinsic base and an emitter; and a second transistor having an intrinsic base, an extrinsic base and an emitter. The extrinsic base of the first transistor and the extrinsic base of the second transistor have a common extrinsic base layer with a first dopant type for the first transistor and a second dopant type for the second transistor.

This application provides a heterojunction bipolar transistor and its fabrication method, radio frequency circuit, and communication device, relating to the field of semiconductor technology, for reducing the parasitic capacitance of the collector region. The heterojunction bipolar transistor includes a substrate, at least a portion of a collector region disposed within the substrate, an intrinsic base region, a first outer base region, a second outer base region, and an emitter region disposed on the substrate. The intrinsic base region is disposed on the substrate and contacts the collector region. The first outer base region is disposed on the substrate and located around the intrinsic base region. The emitter region is disposed on the side of the intrinsic base region away from the substrate. The second outer base region is disposed on the side of the first outer base region away from the substrate and surrounds the emitter region. The heterojunction bipolar transistor also includes a first sidewall; the first sidewall is disposed between the second outer base region and the emitter region; the first sidewall surrounds the emitter region.

This invention discloses a method, storage medium, and device for constructing a proton irradiation effect prediction model for InP heterojunction bipolar transistors (HBTs). The method includes establishing an equivalent circuit topology and characteristic prediction equations, introducing parasitic diodes and tunneling current sources to characterize the characteristic degradation caused by proton irradiation, and introducing DC and RF model parameter degradation equations to characterize the degradation of device electrical characteristics with flux. This enables the model to accurately predict various electrical characteristics of InP HBTs after proton irradiation. This invention solves the difficulty of accurately characterizing the electrical characteristics of devices after high-flux proton irradiation using the classical Agilent HBT model, providing technical support for predicting on-orbit operating characteristics and lifetime of devices, as well as for radiation-hardened design of space integrated circuits.

The present disclosure relates to semiconductor structure and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region; a collector region over the sub-collector region, the collector region having a first semiconductor material comprising polysilicon material and single crystalline semiconductor material which is over the sub-collector region, and a second semiconductor material on the single crystalline semiconductor material; diffusion regions in the first semiconductor material; an emitter region over the collector region; and a base region adjacent to the emitter region.

This application provides a heterojunction bipolar transistor and its fabrication method, radio frequency circuit, and communication device, relating to the field of semiconductor technology, for reducing the parasitic capacitance of the collector region. The heterojunction bipolar transistor includes a substrate, at least a portion of a collector region disposed within the substrate, an intrinsic base region, a first outer base region, a second outer base region, and an emitter region disposed on the substrate. The intrinsic base region is disposed on the substrate and is in contact with the collector region. The first outer base region is disposed on the substrate and is located around the intrinsic base region. The emitter region is disposed on the side of the intrinsic base region away from the substrate. The second outer base region is disposed on the side of the first outer base region away from the substrate and surrounds the emitter region.

The application relates to the technical field of semiconductor integrated circuits, and discloses a heterojunction bipolar transistor and a preparation method thereof, and a semiconductor integrated device and a preparation method thereof. The transistor comprises a first substrate layer, a collector region, a base region, an emitter region, a base, an emitter and a first conductive structure, the collector region is formed on a first surface of the first substrate layer; the base region is formed on the collector region; the emitter region is formed on part of the surface of the base region; the base and the emitter are arranged on the first surface side of the first substrate layer, the base is connected with the base region, and the emitter is connected with the emitter region; and the first conductive structure is arranged on the second surface side and electrically connected with the collector region in the vertical direction. In the application, the signal ports of the base region and the emitter region are arranged on the first surface side, the signal port of the collector region is arranged on the second surface side opposite to the first surface, carrier transmission is directly realized in the longitudinal direction, the parasitic resistance and the parasitic capacitance of the device are reduced, and the device is helpful for the wide application of the device in a high-frequency scene.

This invention discloses a heterojunction bipolar transistor and its fabrication method. The heterojunction bipolar transistor includes, from bottom to top, a substrate, a sub-collector region, a tunneling structure, a collector region, a base region, an emitter region, an emitter capping layer, and an ohmic contact layer. The tunneling structure comprises alternating layers of first and second conductivity types of ion doped layers. According to the heterojunction bipolar transistor and its fabrication method provided by this invention, by forming a tunneling structure composed of alternating layers of first and second conductivity types of ion doped layers between the sub-collector region and the collector region, an etch stop layer is no longer formed. The tunneling junction capacitance (Ctj) is connected in series with the collector junction capacitance (Cbc), reducing the equivalent capacitance and improving device performance.

This invention provides an integration process for heterojunction bipolar transistors and logic devices. The method includes: after forming the preliminary structure of the logic device, depositing an unetched second sidewall material layer and a sacrificial layer; opening a window in the heterojunction region using a first photolithography pattern and epitaxially growing a base region material layer and an emitter structure; forming a photoresist pattern using an outer base region etching mask; and simultaneously etching the sacrificial layer and the second sidewall material layer downwards while etching the base region material layer, thus simultaneously forming the outer base region structure of the heterojunction and the second sidewall structure of the logic device. This invention significantly reduces photomask costs by reusing the outer base region mask to simultaneously form the sidewalls; furthermore, the unetched sidewall material layer plays a crucial protective role for the logic device during heterojunction growth and cleaning, preventing performance degradation, and enabling efficient and low-cost integration of a high-performance heterojunction base region and logic devices.