86 results about "Heterojunction bipolar transistor" patented technology

The invention belongs to the field of semiconductor devices, and particularly discloses a gallium arsenide-based heterojunction bipolar transistor and a preparation method thereof. The GaAs-based HBT device disclosed by the invention adopts an inverted structure, and the semiconductor substrate in the processing technology is used as a conductive N-type semiconductor layer to participate in the conduction of the device; according to the technical scheme of the invention, the parasitic capacitance between the P-type GaAs base and the N-type InGaP layer of the GaAs-based HBT device is small, the contact resistance between the topmost layer in the collector region and the electrode of the collector region can be effectively reduced, the physical isolation between the adjacent GaAs-based HBT devices can be realized by etching the mesa so as to improve the isolation effect, the heat dissipation effect of the emitter region is good, and the service life of the emitter region is prolonged. And a traditional substrate through hole process is not needed, so that the process cost is saved.

A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region an intrinsic base region, and a lateral base link region disposed between and in contact with each of the extrinsic base region and an intrinsic base region. The extrinsic base region, the lateral base link region, and a portion of the intrinsic base region each may be formed on a passivation layer disposed over an isolation region and a collector region of a substrate of the semiconductor device. The extrinsic base region and a first portion of the lateral base link region may be formed from polycrystalline semiconductor material. The intrinsic base region and a second portion of the lateral base link region may be formed from monocrystalline semiconductor material. The lateral base link region may be formed after formation of the extrinsic base region and the intrinsic base region.

This invention relates to the field of semiconductor technology, disclosing a semiconductor structure and its fabrication method, and a heterojunction bipolar transistor, comprising: forming a germanium-silicon layer on one side of a substrate layer, and forming a polysilicon layer on the side of the germanium-silicon layer facing away from the substrate layer; patterning the substrate layer and the germanium-silicon layer to obtain a predetermined collector region based on the substrate layer and a base region based on the germanium-silicon layer; performing ion implantation on the side of the predetermined collector region facing away from the base region to form a collector region; exposing a portion of the surface of the base region on the side of the collector region; patterning the polysilicon layer to form an emitter structure; and the width of the collector region being less than or equal to the width of the emitter structure. This invention can reduce the lateral dimensions of the device, increase integration density, reduce parasitic capacitance and resistance, and also improve the reliability of the collector region, ensuring that the doping concentration distribution of the collector region is within the target range.

The invention provides a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors, and the preparation method of the semiconductor device comprises the steps: forming a passive device part which comprises a plurality of passive device regions; a transistor part is formed, the transistor part comprises a plurality of heterojunction bipolar transistor devices, the transistor part is connected with the passive device part, and the heterojunction bipolar transistor devices correspond to the passive device areas respectively. Through wafer-level flip bonding between the transistor part and the passive device part, corresponding interconnection between a plurality of heterojunction bipolar transistor devices and passive device structures of a plurality of passive device regions is realized, the device size is reduced, the integration level is improved, and chip miniaturization is facilitated.

Disclosed in the present disclosure are a silicon-germanium heterojunction bipolar transistor and a method for manufacturing the same, which relate to a field of semiconductor technologies. The silicon-germanium heterojunction bipolar transistor and the method for manufacturing the same of the present disclosure can achieve the purpose of exposing a part of the sidewall of the polysilicon extrinsic base region, so as to make a necessary space for subsequently growing the silicon-germanium connection base region synchronously with the silicon-germanium epitaxial intrinsic base region, and implement a recessed silicon-germanium connection base region structure which can effectively improve the device performance. In addition, the silicon-germanium heterojunction bipolar transistor of the present disclosure may be manufactured by adopting process steps with low process difficulty and complexity, and then effectively improving the repeatability, uniformity, controllability and manufacturability of the related integrated circuit process production.

This invention provides a heterojunction bipolar transistor and its formation method, comprising a base, a heterojunction interlayer dielectric layer, an emitter, and a collector. The base is located on a substrate, covered by the heterojunction interlayer dielectric layer, the emitter is located on the heterojunction interlayer dielectric layer, and the collector is located on the side of the substrate away from the base. By forming a heterojunction interlayer dielectric layer between the base and the emitter, electrons emitted from the emitter that meet a preset threshold tunnel through the heterojunction interlayer dielectric layer to enter the base, while electrons or holes that do not meet the preset threshold are blocked by the heterojunction interlayer dielectric layer. Electrons that meet the preset threshold and enter the base are transported to the collector when a reverse voltage is applied to the collector, thereby improving electron transport efficiency. Furthermore, by controlling the properties of the heterojunction interlayer dielectric layer, the current amplification coefficients of the collector and base are precisely controlled, significantly improving the stability of the current amplification coefficients of the collector and base, and ensuring stable high-frequency radio frequency performance of the heterojunction device.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

Embodiments of the present application provide a heterojunction bipolar transistor, a preparation method thereof, a radio frequency amplifier and a radio frequency module. The heterojunction bipolar transistor comprises an isolation region, the isolation region has a substrate and a semiconductor layer stacked on the substrate, the isolation region is further provided with a collector contact layer, the substrate is provided with a back hole corresponding to the collector contact layer, the back hole is provided with a first metal layer electrically connected with the collector contact layer, and the semiconductor layer is provided with an isolation groove around the collector contact layer, and the depth of the isolation groove is greater than or equal to one half of the thickness of the semiconductor layer. In this embodiment, the isolation groove is arranged around the collector contact layer corresponding to the back hole on the semiconductor layer, the leakage path of the device is isolated by the isolation groove, the risk of device leakage of the heterojunction bipolar transistor is reduced, and the product performance of the heterojunction bipolar transistor is improved.

Provided is an HBT capable of suppressing a decrease in linearity of input-output characteristics of the HBT. A collector layer, a base layer, and an emitter layer are stacked on a substrate. The collector layer includes a graded semiconductor layer whose electron affinity increases from a side close to the base layer toward a side away from the base layer. The electron affinity on an interface of the base layer on the side close to the collector layer is equal to the electron affinity on an interface of the graded semiconductor layer on the side close to the base layer.

The application provides a heterojunction bipolar transistor defect detection method, which comprises the following steps: acquiring a C-V curve and a 1 / C 2 -V curve of a heterojunction bipolar transistor at a preset voltage; determining the change of the C-V curve and the 1 / C 2 -V curve in a first preset voltage range; and controlling a C-V test module or an I-V test module of deep level transient spectroscopy to detect defects of the heterojunction bipolar transistor according to the change. The heterojunction bipolar transistor defect detection method has the beneficial effects that the different test modules of deep level transient spectroscopy can detect the defect types and defect states of the heterojunction bipolar transistor, and the internal defect properties and radiation damage mechanisms of the heterojunction bipolar transistor can be analyzed in depth.

The present application discloses a method for manufacturing a radio frequency power amplifier, a radio frequency power amplifier structure, and a radio frequency power amplifier circuit. The manufacturing method includes: providing a first wafer on which a multi-stage cascaded field effect transistor structure is formed, the first wafer being a silicon-on-insulator wafer; providing a second wafer on which a silicon-germanium heterojunction bipolar transistor structure is formed, the second wafer being a bulk silicon wafer; bonding the multi-stage cascaded field effect transistor structure and the silicon-germanium heterojunction bipolar transistor structure to form an initial power amplifier structure; forming a metal wiring structure on the initial power amplifier structure, the metal wiring structure being electrically connected to a radio frequency input end and a radio frequency output end respectively to form a radio frequency power amplifier. The corresponding structure and circuit manufactured by this manufacturing method have good radio frequency performance, relatively low manufacturing cost, and good compatibility with CMOS circuits.

The present disclosure relates to bipolar transistors. The present disclosure relates to semiconductor structures, and more particularly to heterojunction bipolar transistors and methods of manufacture. The structure includes a first transistor having an inner base, an outer base, and an emitter, and a second transistor having an inner base, an outer base, and an emitter. The outer base of the first transistor and the outer base of the second transistor have a common outer base layer having a first dopant type for the first transistor and a second dopant type for the second transistor.

The invention provides a method for extracting high-frequency characteristics of an indium-phosphorus heterojunction bipolar transistor (HBT). The method comprises the following steps: acquiring S parameter test data of InP HBTs with different sizes; extracting element parameters based on the test S parameters and the T-type small-signal equivalent circuit model of the InP HBT; obtaining a forward current gain and a unidirectional power gain under the radio frequency condition; constructing a frequency extraction model; obtaining a cut-off frequency and a maximum oscillation frequency; and constructing a geometric scalable model of the cut-off frequency and the maximum oscillation frequency based on the change rule of the cut-off frequency and the maximum oscillation frequency along with the size of the device. According to the invention, the method for extracting the cut-off frequency and the maximum oscillation frequency is defined by using the test S parameter; through testing under the multi-size and multi-bias condition, the effectiveness of the method is verified, the precision of the model is improved, and meanwhile, the time for extracting the cut-off frequency and the maximum oscillation frequency is greatly shortened.

An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a wafer, and the chiplets have interconnections to wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The wafer has at least one wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the wafer circuit to the chiplet circuit.

The invention relates to a semiconductor structure, and more particularly relates to a vertical heterojunction bipolar transistor and a manufacturing method. The structure includes: a collector region over a semiconductor substrate; a base region over the collector region; an emitter region adjacent to the base region; and an undercut structure over the semiconductor substrate and adjacent to the collector region.

The disclosure provides structures and methods to provide a discontinuous barrier film between an emitter and base of a bipolar transistor. A structure according to the disclosure includes a discontinuous barrier film vertically interposed between an emitter and a base of a heterojunction bipolar transistor. Methods of the disclosure include: forming a collector terminal within a semiconductor substrate; forming a base terminal on the collector terminal; forming a discontinuous barrier film on the base terminal; and forming an emitter terminal over the base terminal and the discontinuous barrier film to define a bipolar transistor. The discontinuous barrier film is vertically interposed between the emitter terminal and the base of the bipolar transistor.

This HBT comprises a collector layer (103) composed of a compound semiconductor formed on a substrate (101), a base layer (104) composed of a compound semiconductor formed on the collector layer (103), and an emitter layer (105) that is formed on the base layer (104) and is composed of a compound semiconductor different from that of the base layer (104). The HBT also comprises a collector electrode (111) electrically connected to the collector layer (103), a base electrode (112) formed on the base layer (104) around the emitter layer (105), and an emitter electrode (113) formed on an emitter cap layer (106). The HBT furthermore comprises an electric field application electrode (114) for applying an electric field to the collector layer (103).

The embodiment of the invention provides a heterojunction bipolar transistor and a preparation method thereof, a radio frequency module and communication equipment. The heterojunction bipolar transistor comprises a semiconductor layer; the emitter structures are arranged on the semiconductor layer at intervals, and a gap is formed between every two adjacent emitter structures in the emitter structures; the base metal comprises a first finger part which is arranged in the gap and is in contact connection with the semiconductor layer; the isolation structure comprises a first isolation structure, and the first isolation structure is filled in the gap and covers the first finger part; the isolation structure is made of an insulating material; and the emitting electrode connecting metal is arranged on one side, back to the semiconductor layer, of the plurality of emitting electrode structures and the first isolation structure, and the emitting electrode connecting metal is in contact connection with the plurality of emitting electrode structures. According to the embodiment of the invention, the distance between the emitting electrode connecting metal and the first finger part of the base electrode metal can be increased by arranging the first isolation structure, so that the effect of reducing parasitic capacitance is realized.

The invention relates to the technical field of heterojunction bipolar transistor materials, and particularly discloses a preparation method of an HBT material capable of reducing secondary passivation of an intermediate layer and the HBT material. Comprising the following steps: sequentially growing a p-GaAs: C intermediate base region layer and an n-GaInP: Si emitter region layer on the surface of an n-GaAs collector region layer by adopting an MOCVD (Metal Organic Chemical Vapor Deposition) method; growing a plurality of n-GaAs: Si thin layers on the surface of the n-GaInP: Si emitter region layer, and performing in-situ annealing in a hydrogen atmosphere after the growth of each n-GaAs: Si thin layer is finished; and continuously growing an n-GaAs / InGaAs contact layer to obtain the HBT material. According to the method, the grown multiple n-GaAs: Si thin layers are subjected to in-situ annealing, so that the H element is effectively prevented from penetrating through the growth layer to be combined with the C element in the p-GaAs: C middle base region layer, and the comprehensive performance of the HBT material is improved.

According to the non-uniform emitter structure optimization design method provided by the invention, collaborative optimization design is carried out on a non-uniform emitter contact structure based on the heat distribution characteristic in the preset working state, and differentiated configuration is carried out on the distance and length of emitter fingers and the resistance value of a ballast resistor according to high-temperature and low-temperature regions; under the action of electrothermal coupling, the current density of a high-temperature area of the device is effectively suppressed, and the conductivity of a low-temperature area is fully called, so that the current distribution and temperature field of the whole emitter junction surface are remarkably balanced, the hot spot effect and the positive feedback risk caused by the hot spot effect are fundamentally weakened, and the reliability of the device is improved. And the thermal stability, the reliability and the service life of the heterojunction bipolar transistor under a high-power working condition are greatly improved.

The application discloses an epitaxial structure of a heterojunction bipolar transistor and a preparation method thereof. The method comprises the following steps: forming an n-type doped aluminum gallium arsenide AlGaAs emitter layer on a gallium arsenide GaAs substrate in an epitaxial manner; forming a p-type doped gallium arsenide GaAs base layer on the emitter layer in an epitaxial manner; and forming an n-type doped gallium nitride GaN material collector layer on the base layer in an epitaxial manner. In the actual application of the HBT device, since the GaN material is used as the collector layer, a higher working voltage can be used, thereby being beneficial to increasing the output power of the HBT device, overcoming the power limitation of the GaAs HBT device, and better meeting the high-frequency and high-power requirements of 5G communication.

This invention belongs to the technical field of heterojunction bipolar transistors (HBTs), specifically relating to a HBT and its MOCVD epitaxial growth method. The HBT provided by this invention includes a transition layer disposed between the base region and the emitter layer. The MOCVD epitaxial growth method includes growing the transition layer on the surface of the base region using a linearly variable-temperature staged pulsed metal-organic chemical vapor deposition (MOCVD) method. During the total growth time of the linearly variable-temperature staged pulsed MOCVD method, PH3 is continuously introduced, and trimethylindium, trimethylgallium, and silane are introduced in single-cycle staged pulses. From the initial time T1 to the initial time TN, the reaction chamber temperature linearly increases from the base region growth temperature to the emitter layer growth temperature. The HBT obtained by the method provided by this invention has high gain, low sheet resistance, and high reliability.

The application provides a heterojunction bipolar transistor and a power amplifier. The heterojunction bipolar transistor comprises a substrate and a base mesa arranged on the substrate. The base mesa comprises a collector layer and a base layer arranged on the collector layer, and the base layer comprises a first side and a second side opposite to the first side. The heterojunction bipolar transistor further comprises an emitter layer arranged on the base layer, a base electrode arranged on the substrate and connected to the base layer, a dielectric layer arranged on the base electrode, and a conductive component arranged on the dielectric layer. A first through hole is formed in the first side of the base layer in the dielectric layer, and a second through hole is formed in the second side of the base layer in the dielectric layer. The conductive component is connected to the base electrode through the first through hole and the second through hole. By adding a new signal input end to the base end to reduce the base resistance, the gain performance of the heterojunction bipolar transistor and the power amplifier at a higher operating frequency is improved.

This invention relates to an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection and its fabrication method. The method includes: fabricating a nucleation layer on a substrate; fabricating a collector ohmic contact layer on the nucleation layer; fabricating an etch stop layer on the collector ohmic contact layer; fabricating a collector transition layer on the etch stop layer; fabricating a first collector region layer on the collector transition layer; fabricating a second collector region layer on the first collector region layer; fabricating a p+GaAs base region layer on the second collector region layer; fabricating an n-InGaP emitter region layer on the p+GaAs base region layer; fabricating a first cap layer on the n-InGaP emitter region layer; and fabricating a second cap layer on the first cap layer. This invention solves the performance degradation problem caused by the low conduction band and valence band energy difference and low current gain in existing devices.

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a semiconductor substrate; a collector region over the semiconductor substrate; an intrinsic base over the collector region; an electrically insulating heat dissipative material at a junction of the collector region and the intrinsic base; an extrinsic base over the intrinsic base; and an emitter region adjacent to the extrinsic base.

An optical receiver includes a monolithically integrated pin-shaped photodiode (PIN) and a transimpedance amplifier (TIA). The TIA includes an InP heterojunction bipolar transistor (HBT) made of a first plurality of layers of an epitaxial layer stack grown on an Si:InP substrate; the PIN is made of a second plurality of layers of the epitaxial layer stack. The p-type contact of the PIN is vertically connected to the input of the TIA to reduce the PIN capacitance C. PIN The TIA capacitor C TIA Can be etched to C PIN The thickness of the absorption layer, the window area and the optional mirror thickness of the PIN, the device capacitance C PIN +C TIA and the TIA’s feedback resistor R F The device parameters are optimized to specific performance specifications including sensitivity and responsivity at the operating wavelength. This design approach enables cost-effective manufacturing of integrated PIN‑TIAs for applications such as 1577 nm receivers in 10G‑PON ONUs.

This invention provides a heterojunction bipolar transistor and its manufacturing method. A first-conductivity InGaP emitter layer (layers 1 to m) is formed on a GaAs base layer of a second conductivity type. Each InGaP emitter layer contains In... y Ga 1‑y P, and y decreases layer by layer from the first InGaP emitter layer to the mth InGaP emitter layer, m≥3 and is an integer. This results in a gradual bandgap difference between the materials of the first to mth InGaP emitter layers and the P GaAs base layer, which effectively reduces the barrier peak at the InGaP / GaAs heterojunction, avoids the turn-on voltage Vbe from becoming high when the HBT is working, and improves the device performance.

The present disclosure relates to semiconductor structures, and more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure comprises: a sub-collector region; a collector region over the sub-collector region, the collector region having a first semiconductor material including a polysilicon material and a single crystal semiconductor material over the sub-collector region, and a second semiconductor material over the single crystal semiconductor material; a diffusion region in the first semiconductor material; an emitter region over the collector region; and a base region adjacent to the emitter region.

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.