161 results about "Heterojunction bipolar transistor" patented technology

An optical receiver comprises a monolithically integrated pin photodiode (PIN) and transimpedance amplifier (TIA). The TIA comprises InP heterojunction bipolar transistors (HBT) fabricated from a first plurality of layers of an epitaxial layer stack grown on a SI:InP substrate; the PIN is fabricated from a second plurality of layers of the epitaxial layer stack. The p-contact of the PIN is directly connected to the input of the TIA to reduce PIN capacitance CPIN. The TIA capacitance CTIA may be matched to CPIN. Device parameters comprising: a thickness of the absorption layer, window area, and an optional mirror thickness of the PIN; device capacitance CPIN+CTIA; and feedback resistance RF of the TIA; are optimized to performance specifications comprising a specified sensitivity and responsivity at an operational wavelength. This design approach enables cost-effective fabrication an integrated PIN-TIA, for applications such as a 1577 nm receiver for an ONU for 10G-PON.

A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration.

The invention discloses a high-linearity and high-power GaAs HBT (Heterojunction Bipolar Transistor) power amplifier with a power detection function. The high-linearity and high-power GaAs HBT power amplifier comprises a radio frequency path, a bias module and a power detection circuit, the radio frequency path is used for performing power amplification on a radio frequency signal, improving the stability and expanding the bandwidth by using a negative feedback network, and improving the overall linearity by second harmonic suppression; the bias circuit is used for providing bias voltage dynamically changing along with input power for the three-stage amplification circuit, so that the problems of linearity deterioration and current instability caused by a self-heating effect under high-power input of the GaAs HBT transistor are solved, and amplitude-amplitude distortion and amplitude-phase distortion of the power amplifier are improved; and the power detection circuit is used for outputting a direct-current voltage which is positively correlated with the output power so as to realize accurate control on the output power of the power amplifier. According to the invention, negative feedback, dynamic bias and harmonic suppression technologies are fully combined, and the overall linearity of the amplifier is effectively improved.

An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a host wafer, and the chiplets have interconnections to host wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The host wafer has at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The host wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the host wafer circuit to the chiplet circuit.

The invention belongs to the technical field of heterojunction bipolar transistors, and particularly relates to a heterojunction bipolar transistor and an MOCVD epitaxial growth method thereof. The heterojunction bipolar transistor provided by the invention comprises a transition layer arranged between a base region and an emission layer, and the MOCVD epitaxial growth method comprises the step of growing the transition layer on the surface of the base region by adopting a linear variable-temperature staged pulse metal organic chemical vapor deposition method, pH3 is continuously introduced within the total growth time of the linear variable-temperature staged pulse metal organic chemical vapor deposition method, and trimethyl indium, trimethyl gallium and silane are introduced in a single-cycle staged pulse manner; and the temperature of the reaction chamber is linearly increased from the base region growth temperature to the emission layer growth temperature within the time from the T1 initial moment to the TN initial moment. The heterojunction bipolar transistor obtained by the method provided by the invention is large in gain, low in sheet resistance and good in reliability.

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.

The invention belongs to the field of semiconductor devices, and particularly discloses a gallium arsenide-based heterojunction bipolar transistor and a preparation method thereof. The GaAs-based HBT device disclosed by the invention adopts an inverted structure, and the semiconductor substrate in the processing technology is used as a conductive N-type semiconductor layer to participate in the conduction of the device; according to the technical scheme of the invention, the parasitic capacitance between the P-type GaAs base and the N-type InGaP layer of the GaAs-based HBT device is small, the contact resistance between the topmost layer in the collector region and the electrode of the collector region can be effectively reduced, the physical isolation between the adjacent GaAs-based HBT devices can be realized by etching the mesa so as to improve the isolation effect, the heat dissipation effect of the emitter region is good, and the service life of the emitter region is prolonged. And a traditional substrate through hole process is not needed, so that the process cost is saved.

The invention discloses a heterojunction bipolar transistor, and belongs to the technical field of semiconductors. The heterojunction bipolar transistor comprises a collector electrode; the base electrode is positioned on one side of the collector electrode; the emitting electrode is positioned on one side, deviating from the collecting electrode, of the base electrode; wherein the base electrode comprises a superlattice structure, the band gap of the base electrode is smaller than the band gap of the emitter electrode, the conduction band offset between the base electrode and the emitter electrode is smaller than the target conduction band offset, and the valence band offset between the base electrode and the emitter electrode is larger than the first target valence band offset. The valence band offset between the base and the collector is greater than a second target valence band offset. The electron injection efficiency of the emitter can be improved, the overall power consumption of the device is reduced, injection of holes from the base to the collector is effectively prevented, and the performance of the device is improved.

A semiconductor device (100) includes a heterojunction bipolar transistor (HBT) (104) having a collector (106), a base, and an emitter (130). The base includes a monocrystalline base layer (124), including silicon-germanium, on the collector (106), and an extrinsic base layer (112), including polycrystalline silicon, extending partway over the monocrystalline base layer (124). The base further includes a base link (126), including polycrystalline silicon-germanium, connecting the monocrystalline base layer (124) to the extrinsic base layer (112). An emitter spacer (122), of dielectric material, laterally separates the emitter (130) from the extrinsic base layer (112). The HBT (104) has a spacer-extrinsic base vertical offset (136) between a bottom of the emitter spacer (122) and a bottom surface of the extrinsic base layer (112) adjacent to the emitter spacer (122). The emitter spacer (122) has a bottom width (138) at a bottom of the emitter spacer (122). A sum of the spacer-extrinsic base vertical offset (136) and the bottom width (138) of the emitter spacer (122) is greater than the thickness (140) of the monocrystalline base layer (124).

A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region an intrinsic base region, and a lateral base link region disposed between and in contact with each of the extrinsic base region and an intrinsic base region. The extrinsic base region, the lateral base link region, and a portion of the intrinsic base region each may be formed on a passivation layer disposed over an isolation region and a collector region of a substrate of the semiconductor device. The extrinsic base region and a first portion of the lateral base link region may be formed from polycrystalline semiconductor material. The intrinsic base region and a second portion of the lateral base link region may be formed from monocrystalline semiconductor material. The lateral base link region may be formed after formation of the extrinsic base region and the intrinsic base region.

This invention relates to the field of semiconductor technology, disclosing a semiconductor structure and its fabrication method, and a heterojunction bipolar transistor, comprising: forming a germanium-silicon layer on one side of a substrate layer, and forming a polysilicon layer on the side of the germanium-silicon layer facing away from the substrate layer; patterning the substrate layer and the germanium-silicon layer to obtain a predetermined collector region based on the substrate layer and a base region based on the germanium-silicon layer; performing ion implantation on the side of the predetermined collector region facing away from the base region to form a collector region; exposing a portion of the surface of the base region on the side of the collector region; patterning the polysilicon layer to form an emitter structure; and the width of the collector region being less than or equal to the width of the emitter structure. This invention can reduce the lateral dimensions of the device, increase integration density, reduce parasitic capacitance and resistance, and also improve the reliability of the collector region, ensuring that the doping concentration distribution of the collector region is within the target range.

The present invention provides a heterojunction bipolar transistor with a GAA structure and a preparation method thereof. The transistor is a small-size device, and mainly uses the process of a gate-all-around field effect transistor (GAAFET) to prepare a Si / SiGe heterojunction bipolar transistor. The emitter region and the base region of the structure form a fully surrounded heterogeneous emitter junction, and the base region and the collector region form a fully surrounded collector junction, which effectively increases the injection efficiency of the emitter junction and the ability of the collector region to extract carriers. For the Si / SiGe heterojunction, the carriers can be effectively controlled by adjusting the change in the band gap width of the SiGe material; by increasing the doping concentration of the SiGe base region, the device can obtain a higher Early voltage, reduce the base resistance, and weaken the large injection effect; by thinning the base region thickness, the base region transit time is greatly shortened, and the excellent performance of ultra-high frequency, ultra-high speed and low noise can be achieved.

The invention provides a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors, and the preparation method of the semiconductor device comprises the steps: forming a passive device part which comprises a plurality of passive device regions; a transistor part is formed, the transistor part comprises a plurality of heterojunction bipolar transistor devices, the transistor part is connected with the passive device part, and the heterojunction bipolar transistor devices correspond to the passive device areas respectively. Through wafer-level flip bonding between the transistor part and the passive device part, corresponding interconnection between a plurality of heterojunction bipolar transistor devices and passive device structures of a plurality of passive device regions is realized, the device size is reduced, the integration level is improved, and chip miniaturization is facilitated.

Disclosed in the present disclosure are a silicon-germanium heterojunction bipolar transistor and a method for manufacturing the same, which relate to a field of semiconductor technologies. The silicon-germanium heterojunction bipolar transistor and the method for manufacturing the same of the present disclosure can achieve the purpose of exposing a part of the sidewall of the polysilicon extrinsic base region, so as to make a necessary space for subsequently growing the silicon-germanium connection base region synchronously with the silicon-germanium epitaxial intrinsic base region, and implement a recessed silicon-germanium connection base region structure which can effectively improve the device performance. In addition, the silicon-germanium heterojunction bipolar transistor of the present disclosure may be manufactured by adopting process steps with low process difficulty and complexity, and then effectively improving the repeatability, uniformity, controllability and manufacturability of the related integrated circuit process production.

This invention provides a heterojunction bipolar transistor and its formation method, comprising a base, a heterojunction interlayer dielectric layer, an emitter, and a collector. The base is located on a substrate, covered by the heterojunction interlayer dielectric layer, the emitter is located on the heterojunction interlayer dielectric layer, and the collector is located on the side of the substrate away from the base. By forming a heterojunction interlayer dielectric layer between the base and the emitter, electrons emitted from the emitter that meet a preset threshold tunnel through the heterojunction interlayer dielectric layer to enter the base, while electrons or holes that do not meet the preset threshold are blocked by the heterojunction interlayer dielectric layer. Electrons that meet the preset threshold and enter the base are transported to the collector when a reverse voltage is applied to the collector, thereby improving electron transport efficiency. Furthermore, by controlling the properties of the heterojunction interlayer dielectric layer, the current amplification coefficients of the collector and base are precisely controlled, significantly improving the stability of the current amplification coefficients of the collector and base, and ensuring stable high-frequency radio frequency performance of the heterojunction device.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

Embodiments of the present application provide a heterojunction bipolar transistor, a preparation method thereof, a radio frequency amplifier and a radio frequency module. The heterojunction bipolar transistor comprises an isolation region, the isolation region has a substrate and a semiconductor layer stacked on the substrate, the isolation region is further provided with a collector contact layer, the substrate is provided with a back hole corresponding to the collector contact layer, the back hole is provided with a first metal layer electrically connected with the collector contact layer, and the semiconductor layer is provided with an isolation groove around the collector contact layer, and the depth of the isolation groove is greater than or equal to one half of the thickness of the semiconductor layer. In this embodiment, the isolation groove is arranged around the collector contact layer corresponding to the back hole on the semiconductor layer, the leakage path of the device is isolated by the isolation groove, the risk of device leakage of the heterojunction bipolar transistor is reduced, and the product performance of the heterojunction bipolar transistor is improved.

Provided is an HBT capable of suppressing a decrease in linearity of input-output characteristics of the HBT. A collector layer, a base layer, and an emitter layer are stacked on a substrate. The collector layer includes a graded semiconductor layer whose electron affinity increases from a side close to the base layer toward a side away from the base layer. The electron affinity on an interface of the base layer on the side close to the collector layer is equal to the electron affinity on an interface of the graded semiconductor layer on the side close to the base layer.

The application provides a heterojunction bipolar transistor defect detection method, which comprises the following steps: acquiring a C-V curve and a 1 / C 2 -V curve of a heterojunction bipolar transistor at a preset voltage; determining the change of the C-V curve and the 1 / C 2 -V curve in a first preset voltage range; and controlling a C-V test module or an I-V test module of deep level transient spectroscopy to detect defects of the heterojunction bipolar transistor according to the change. The heterojunction bipolar transistor defect detection method has the beneficial effects that the different test modules of deep level transient spectroscopy can detect the defect types and defect states of the heterojunction bipolar transistor, and the internal defect properties and radiation damage mechanisms of the heterojunction bipolar transistor can be analyzed in depth.

The present invention provides a compound semiconductor heterojunction bipolar transistor, including a structure of an emitter layer and a base layer, in which, in a GaAsHBT using pseudo-grown InGaAs for the base layer, the influence of the conduction band energy barrier generated at the interface between the emitter layer and the base layer on the characteristics of a power amplifier is reduced. In the first invention, InGaP having a CuPt-type order is used for the emitter layer. In the second invention, the p-type impurity concentration of the part of the pseudo-grown InGaAs base layer on the emitter layer side is made lower than that on the collector layer side.

A hetero-junction bipolar transistor structure and a forming method therefor, relating to the technical field of semiconductor manufacturing. The structure comprises: a substrate (200); located on the substrate (200), a collector layer (209), a base layer (208) and emission layers (205); emission electrodes (204), located on the emission layers (205); collectors (213), located on the collector layer (209); a base electrode (212), the base electrode (212) comprising a plurality of finger parts (212a), the plurality of finger parts (212a) being electrically connected to the base layer (208) separately; a passivation structure, the passivation structure exposing part of the top surfaces of the emission electrodes (204), part of the top surfaces of the collectors (213), and part of the top surfaces of the finger parts (212a) between adjacent emission layers (205); and an interconnection metal layer, the interconnection metal layer being electrically connected to the emission electrodes (204), the finger parts (212a) and the collectors (213), separately. By means of omitting the end part of the base electrode (212), the base layer (208) does not need to provide a placement position for the end part of the base electrode (212), thus effectively reducing the area of the base layer (208), and further reducing the area of a PN junction formed between the base layer (208) and the collector layer (209). The part providing placement for the end part of the base electrode (212) and not contributing to a current is removed from the base layer (208), thereby effectively improving the use efficiency of the device structure.

The present application discloses a method for manufacturing a radio frequency power amplifier, a radio frequency power amplifier structure, and a radio frequency power amplifier circuit. The manufacturing method includes: providing a first wafer on which a multi-stage cascaded field effect transistor structure is formed, the first wafer being a silicon-on-insulator wafer; providing a second wafer on which a silicon-germanium heterojunction bipolar transistor structure is formed, the second wafer being a bulk silicon wafer; bonding the multi-stage cascaded field effect transistor structure and the silicon-germanium heterojunction bipolar transistor structure to form an initial power amplifier structure; forming a metal wiring structure on the initial power amplifier structure, the metal wiring structure being electrically connected to a radio frequency input end and a radio frequency output end respectively to form a radio frequency power amplifier. The corresponding structure and circuit manufactured by this manufacturing method have good radio frequency performance, relatively low manufacturing cost, and good compatibility with CMOS circuits.

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.

The present disclosure relates to bipolar transistors. The present disclosure relates to semiconductor structures, and more particularly to heterojunction bipolar transistors and methods of manufacture. The structure includes a first transistor having an inner base, an outer base, and an emitter, and a second transistor having an inner base, an outer base, and an emitter. The outer base of the first transistor and the outer base of the second transistor have a common outer base layer having a first dopant type for the first transistor and a second dopant type for the second transistor.

The invention provides a method for extracting high-frequency characteristics of an indium-phosphorus heterojunction bipolar transistor (HBT). The method comprises the following steps: acquiring S parameter test data of InP HBTs with different sizes; extracting element parameters based on the test S parameters and the T-type small-signal equivalent circuit model of the InP HBT; obtaining a forward current gain and a unidirectional power gain under the radio frequency condition; constructing a frequency extraction model; obtaining a cut-off frequency and a maximum oscillation frequency; and constructing a geometric scalable model of the cut-off frequency and the maximum oscillation frequency based on the change rule of the cut-off frequency and the maximum oscillation frequency along with the size of the device. According to the invention, the method for extracting the cut-off frequency and the maximum oscillation frequency is defined by using the test S parameter; through testing under the multi-size and multi-bias condition, the effectiveness of the method is verified, the precision of the model is improved, and meanwhile, the time for extracting the cut-off frequency and the maximum oscillation frequency is greatly shortened.

The invention discloses a semiconductor device and a forming method thereof. The structure comprises a substrate; the heterojunction bipolar transistor device is connected to the surface of the substrate, the heterojunction bipolar transistor device comprises an emitter layer, a base layer, a plurality of collector layers and a first isolation structure located in the emitter layer and the base layer, the emitter layer is provided with a first side and a second side which are opposite to each other, and the collector layers are arranged on the first side and the second side. The base layer, the collector layer and the substrate are located on the first side, the base layer is located between the collector layer and the emitter layer, stray capacitance CBE and stray capacitance CBC can be reduced, meanwhile, a substrate material with high heat dissipation performance can be selected, and the heat dissipation capacity of the heterojunction bipolar transistor device is improved.

An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a wafer, and the chiplets have interconnections to wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The wafer has at least one wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the wafer circuit to the chiplet circuit.

The invention relates to a semiconductor structure, and more particularly relates to a vertical heterojunction bipolar transistor and a manufacturing method. The structure includes: a collector region over a semiconductor substrate; a base region over the collector region; an emitter region adjacent to the base region; and an undercut structure over the semiconductor substrate and adjacent to the collector region.

The invention belongs to the technical field of microelectronics and piezoelectric electronics, and relates to a heterojunction bipolar transistor device with a piezoelectric effect and a preparation method thereof, the heterojunction bipolar transistor device comprises a substrate, an insulating layer, an emitter region, a collector region and a metal electrode; the base is of a convex structure, the middle convex part of the base is marked as a base region, and the non-convex parts at the two ends of the base are marked as substrates; the insulating layers cover the substrates at the two ends of the substrate, and the emitter region and the collector region are located on the insulating layers at the two ends of the substrate respectively; the metal electrodes comprise a first metal electrode, a second metal electrode and a third metal electrode; the first metal electrode, the second metal electrode and the third metal electrode are respectively arranged on the collector region, the emitter region and the base region and are not in contact with one another, the emitter region and the collector region are both made of N-type ZnO, the substrate is made of silicon, and the technical effect of improving the stability and controllability of the piezoelectric effect is achieved.

The disclosure provides structures and methods to provide a discontinuous barrier film between an emitter and base of a bipolar transistor. A structure according to the disclosure includes a discontinuous barrier film vertically interposed between an emitter and a base of a heterojunction bipolar transistor. Methods of the disclosure include: forming a collector terminal within a semiconductor substrate; forming a base terminal on the collector terminal; forming a discontinuous barrier film on the base terminal; and forming an emitter terminal over the base terminal and the discontinuous barrier film to define a bipolar transistor. The discontinuous barrier film is vertically interposed between the emitter terminal and the base of the bipolar transistor.