Fabrication method of submicron gate using anisotropic etching
a technology of anisotropic etching and submicron gate, which is applied in the direction of semiconductor devices, electrical apparatus, transistors, etc., can solve the problems of increased manufacturing costs, high cost, and high exposure process requirements, and achieve the effect of reducing the distance between the base and the base resistan
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[0025] Now, a preferred embodiment of the present invention will be described in detail, with reference to the annexed drawings.
[0026] FIGS. 1 to 9 illustrate sequential steps of a submicron gate fabrication and self-alignment procedure according to an embodiment of the present invention, respectively.
[0027] FIG. 1 illustrates an essential laminated structure according to the embodiment of the present invention in which a dummy emitter is laminated on a general InP / InGaAs heterojunction bipolar transistor (HBT) structure. As shown in FIG. 1, this structure is formed by laminating InGaAs layers (12, 14, and 16), and InP layers (13 and 15) over a Fe-doped InP substrate (11) in an alternating fashion, using a laminated growth equipment such as MOCVD or MBE.
[0028] The second InP layer (15) defines an emitter region, the second InGaAs layer (14) an emitter cap region, and the third InGaAs layer (16) a base region, respectively. The first InGaAs layer (12) and the first InP layer (13) def...
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