105results about How to "Lower base resistance" patented technology

The present invention relates to semiconductor technologies, and more particularly to a bipolar junction transistor (BJT) in a CMOS base technology and methods of forming the same. The BJT includes a semiconductor substrate having an emitter region, a base having a first contact, and a collector having a second contact and a well plug; a first silicide film on the first contact; a second silicide film on the second contact; a first silicide blocking layer on or over the semiconductor substrate between the first and second silicide films, and a second silicide blocking layer on the semiconductor substrate between the first silicide film and the emitter region.

A trenched MOSFET with trenched source contact, comprising: a semiconductor region, further comprising a silicon substrate, a epitaxial layer corresponding to the drain region of the trenched MOSFET, a base layer corresponding to the body region of the trenched MOSFET, and a source layer corresponding to the source region of the trenched MOSFET; an interlayer oxide film formed on the source layer; a front metal layer formed on a upper surface of the semiconductor region; a back metal layer formed on a lower surface of the semiconductor region; a plurality of trenched gates formed to reach the epitaxial layer through the source layer and the base layer, and is covered by the interlayer oxide film; and a plurality of source contact trenches formed to reach the base layer through the interlayer oxide film and the source layer, and is covered by the front metal layer; wherein the silicon substrate, the epitaxial layer, the base layer, and the source layer are stacked in sequence; and each of the source contact trenches has a lateral contact layer at a sidewall thereof.

The invention relates to a bipolar transistor and a method for producing same. The aim of the invention is to provide a bipolar transistor and a method for producing same, which during the use of a single-process poly-silicon technology with differential epitaxis for the production of bases overcomes the disadvantages of conventional systems, so as notably further to improve the high-speed properties of a bipolar transistor, provide the most conductive connections possible between the metal contacts and the active (internal) transistor region as well as a minimized passive transistor surface, while at the same time avoiding greater process complexity and increased contact resistances. To this end a surface relief is produced in the active emitter region by a wet-chemical process. A single-process poly-silicon bipolar transistor having a base produced by epitaxis in accordance with the invention permits a reduction in external base resistance without causing a deterioration in emitter properties. Because the internal and external base regions are deposited continuously no interface problems arise during connection of the base. Base-collector capacity can also be lowered.

The invention provides a crosswise DMOS with cupped source electrode contact and a method for forming the crosswise DMOS. The crosswise DMOS comprises a cupped source electrode contact, wherein the cupped source electrode contact comprises a cupped part which longitudinally extends and penetrates the source area of the crosswise DMOS and contacts the body area,and the cupped part is electrically coupled with the source area and the body area. The crosswise DMOS not only has smaller size, but also is low in production cost.

The invention discloses a radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) component. A light dope P type buried layer and a middle dope buried layer in the light dope P type buried layer are additionally arranged under a P type channel region. The base electrode resistance of a parasitic non-protein nitrogen (NPN) pipe can be reduced, so that snapback effect is not prone to be generated. A reversed diode formed by a source electrode, the channel and the buried layer can strangulate drain-source voltage of an LDMOS and can sink extra current on a substrate. Thick gate oxide at the drain electrode end can reduce hot carrier effect, and thin gate oxide at the source electrode end can improve transconductance of the component. The invention further discloses a manufacture method of the RF LDMOS component. In process realization, the manufacture method only adds two photoetching steps in an existing process so as to be easy to implement.

A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.

A bipolar semiconductor device including a collector layer covered at a portion of an outer periphery thereof with an insulating film and having a shape extending in an upper direction and a horizontal direction, with a gap being formed between the collector layer and the insulating film, and further including a base layer and an emitter layer disposed over the collector layer, and a manufacturing method of the semiconductor device. Since the collector layer has a shape extending in a portion thereof in the upward direction and the horizontal direction, an external collector region can be deleted, and both the parasitic capacitance and the collector capacitance in the intrinsic portion attributable to the collector can be decreased and, accordingly, a bipolar transistor capable of high speed operation at a reduced consumption power can be constituted.

A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bias voltage is such as to create an accumulation layer in the base under the gate. The accumulation layer provides a low-resistance path for the transistor base current, thus reducing the base resistance of the transistor.

Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

A heat sink, wherein a plurality of heat radiation fins are mounted on a base plate to which an electron device is attached in a heat transmittable manner. The heat radiation fins are erected vertically and in parallel with each other on the reverse face of the base plate to which the electron device is contacted, and extended laterally from the base plate. The heat sink of the invention comprises a heat pipe for transporting heat between the extended portion of the heat radiation fins and the base plate.

In one illustrative example, a three terminal magnetic sensor (TTM) suitable for use in a magnetic head has a base region, a collector region, and an emitter region. A first barrier layer separates the emitter region from the base region, and a second barrier layer separates the collector region from the base region. A sensing plane is defined along sides of the base region, the collector region, and the emitter region. The base region consists of a free layer structure so as to have a relatively small thickness. A pinned layer structure is made part of the emitter region. An in-stack longitudinal biasing layer (LBL) structure which magnetically biases the free layer structure is made part of the collector region. In one variation, the emitter region has the in-stack LBL structure and the collector region has the pinned layer structure. The TTM may comprise a spin valve transistor (SVT), a magnetic tunnel transistor (MTT), or a double junction structure.

In one illustrative example, a three terminal magnetic sensor (TTM) suitable for use in a magnetic head has a base region, a collector region, and an emitter region. A first barrier layer is located between the emitter region and the base region, and a second barrier layer is located between the collector region and the base region. A sensing plane is defined along sides of the base region, the collector region, and the emitter region. The base region has a free layer structure, a pinned layer structure adjacent the first barrier layer, and a non-magnetic spacer layer located between the free layer structure and the pinned layer structure. The collector region comprises an in-stack longitudinal biasing layer (LBL) structure which magnetically biases the free layer structure, where the second barrier layer serves as a non-magnetic spacer layer for the in-stacking biasing layer structure. In one variation, the layers are inverted such that the emitter region has the in-stack LBL structure. The TTM may comprise a spin valve transistor (SVT), a magnetic tunnel transistor (MTT), or a double junction structure.

In an npn-type HBT, each of an emitter layer and a collector layer is formed of AlGaN and a base layer is formed of GaN. The emitter layer is in contact with a nitrogen polarity surface of the base layer and the collector layer is in contact with a gallium polarity surface of the base layer. An electric charge is generated at each interface due to a spontaneous polarization and a piezo polarization generated in each of the layers. Because of the electric charge, an internal field is generated so as to accelerate electrons in the base layer.