40 results about "Semiconductor alloys" patented technology

A method of manufacturing a semiconductor device and a semiconductor device. In one embodiment, a method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers alternating with a plurality of channel layers, forming a dummy gate stack over a top surface and sidewalls of the multi-layer stack, forming a first spacer on the sidewalls of the dummy gate stack, and forming a second spacer over the sidewalls of the dummy gate stack. Growing an epitaxial source / drain region extending through the plurality of sacrificial layers and the plurality of channel layers, forming a metal-semiconductor alloy region on a first portion of the epitaxial source / drain region, forming a coating on the metal-semiconductor alloy region, and during the formation of the metal-semiconductor alloy region and the coating, forming a second portion of the epitaxial source / drain region. A remaining layer is formed on the sidewalls of the first spacer, and a wet cleaning process is performed to selectively etch the remaining layer from the sidewalls of the first spacer.

An example Geiger mode avalanche photodiode includes a first semiconductor alloy forming a compositionally graded gain region configured to form a conduction band having free electrons, a valence band having free holes, and a bandgap between the valence band and the conduction band that varies in size across the graded gain region; a second semiconductor alloy forming an absorber region; and a semiconductor substrate.

A bipolar junction transistor a base over a collector, the base including a III-V ternary semiconductor alloy including first, second, and third elements. The LI-V ternary semiconductor alloy has a narrower bandgap than a binary semiconductor alloy including only the first and second elements. A ledge between an emitter and a base contact being 0.5 μm or less.

A bipolar junction transistor has a collector over a substrate and a multi-layer base structure over the collector, and an emitter over the base structure. The multi-layer base structure includes a first layer having a first III-V semiconductor alloy and a second layer having a second III-V semiconductor alloy having a different composition of elements than the first III-V semiconductor alloy. The second layer has a narrower bandgap than the first layer. The first layer is positioned between the collector and the second layer.

A bipolar junction transistor has a collector over a substrate, a base over the collector, and an emitter over the base. The base includes a III-V ternary semiconductor alloy including first, second, and third elements, and having a narrower bandgap than a binary semiconductor alloy including only the first and second elements. At least a portion of the base has a differential concentration of the third element such that a concentration of the third element at a first location in the base is greater than at a second location in the base, the second location between the first location and the collector.

A photodiode (200) comprises a carrier generating region (206) of a semiconductor having a bandgap that absorbs light (205) of a given wavelength, such that electrical charge carriers are generated therein. The photodiode further comprises a n-doped (210) and a p-doped (208) semiconductor region having respective bandgaps higher than the bandgap of the carrier generating region, the respective bandgaps being transparent to the light of the given wavelength, the n-doped and p-doped semiconductor region being along different sides of the carrier generating region. The photodiode further comprises an interface region (211) between the carrier generating region and a given doped region of the n-doped and the p-doped semiconductor region, the interface region comprising one or more of a semiconductor alloy and a semiconductor sequence that is one or more of graded and stepped in composition, selected to reduce a band offset (222) between the carrier generating region and the given doped region adjacent the interface region.

The present invention relates to a method for obtaining a doped semiconductor layer, comprising the following sequential steps: a) implanting ions of a first dopant element B and a second undoped element C of a semiconductor alloy, which is made of at least a first element A1 and a second element A2, into a first single crystal layer to amorphize the upper part of the first layer and maintain the crystal structure of the lower part of the first layer; and b) subjecting the upper part of the first layer to solid-state recrystallization annealing, thereby transforming the upper part of the first layer into a doped single crystal layer of the alloy.

The invention relates to the technical field of solar cells, and particularly discloses a crystalline silicon thermal electron solar cell and a photovoltaic module, which comprise a silicon substrate, and the silicon substrate comprises a P-type region and an n-type region positioned on one side of an illumination surface of the P-type region; the illumination surface of the silicon substrate is provided with a silver collection gate electrode, and the back side of the silicon substrate is provided with a silver extraction electrode; an Ag-Si semiconductor alloy junction is arranged at the position, corresponding to the silver collection gate electrode, in the silicon substrate, an n-type ultra-shallow diffusion layer is formed on the outer side of the Ag-Si semiconductor alloy junction, an n-P junction is formed between the n-type ultra-shallow diffusion layer and the P-type region, and the n-P junction and the n-P junction form a three-dimensional PN junction quantum well; the silver collection gate electrode and the Ag-Si semiconductor alloy structure form a contact electrode. Thermo-electron transmission is accelerated, thermo-electron extraction and utilization are realized, and the photoelectric conversion efficiency is further improved.

A photodiode comprises a carrier generating region of a semiconductor having a bandgap that absorbs light of a given wavelength, such that electrical charge carriers are generated therein. The photodiode further comprises n-doped and a p-doped semiconductor regions having respective bandgaps higher than the bandgap of the carrier generating region, the respective bandgaps being transparent to the light of the given wavelength, the n n-doped and a p-doped semiconductor regions being along different sides of the carrier generating region. The photodiode further comprises an interface region between the carrier generating region and a given doped region of n-doped and a p-doped semiconductor regions, the interface region comprising one or more of a semiconductor alloy and a semiconductor sequence that is one or more of graded and stepped in composition, selected to reduce a band offset between the carrier generating region and the given doped region adjacent the interface region.

In an embodiment, a device includes: a source / drain region adjacent a channel region; an inter-layer dielectric on the source / drain region; a source / drain contact extending through the inter-layer dielectric and into the source / drain region; a metal-semiconductor alloy region between the source / drain contact and the source / drain region, the metal-semiconductor alloy region disposed beneath a top surface of the channel region, the metal-semiconductor alloy region including a first dopant; and a contact spacer around the source / drain contact, the contact spacer including the first dopant and an amorphizing impurity.

The example relates to a method for fabricating a semiconductor structure having multiple quantum wells. The method includes: providing a substrate comprising a binary semiconductor compound having a first lattice constant; depositing at least a first layer on the substrate and a second layer in contact with the first layer to form a first stack of substantially planar semiconductor layers on the substrate, the first layer being a first semiconductor alloy comprising InP, and the second layer being a second semiconductor alloy comprising InP; depositing a third layer of the binary semiconductor compound having the first lattice constant in contact with the first stack; depositing at least a fourth layer on the third layer and a fifth layer in contact with the fourth layer to form a second stack of substantially planar semiconductor layers on the third layer, the fourth layer comprising a third semiconductor alloy containing InP, and the fifth layer comprising a fourth semiconductor alloy containing InP.

A semiconductor device and the method of forming are provided. The semiconductor device may include a first dielectric layer, a first source / drain region in the first dielectric layer, a first nanostructure on a sidewall of the first source / drain region, a first gate structure around the first nanostructure, a first conductive contact electrically connected to the first source / drain region, and a first metal-semiconductor alloy region between the first portion of the first conductive contact and the first source / drain region. A first portion of the first conductive contact may extend through the first source / drain region, and the first portion of the first conductive contact comprises a first sidewall and a second sidewall opposite the first sidewall in a cross-sectional view. A first portion of the first metal-semiconductor alloy region may be on the first sidewall and a second portion of the first metal-semiconductor alloy region may be on the second sidewall.

The application discloses a preparation method of a group IV compound epitaxial alloy thin film. It relates to the technical field of semiconductor alloy thin film growth, and comprises the following steps: placing initial silicon single crystal particles and target doped group IV metal single crystal particles with a preset atomic mole ratio on the surface of a reaction substrate; after a target vacuum degree and a target heating temperature are reached in a preparation device, the target doped group IV metal single crystal particles become a molten state, a target metal solution is obtained, the initial silicon single crystal particles are dissolved in the target metal solution, and a reaction metal solution is formed; a carrier gas and a carbon-containing reaction gas are introduced into the preparation device, the carbon-containing reaction gas contacts the surface of the reaction metal solution and is cracked to form carbon reaction atoms, the carbon reaction atoms diffuse and react in the reaction metal solution, and a group IV compound epitaxial alloy thin film is formed. Through the application, the problem that an epitaxial multi-component alloy thin film with high metal concentration, controllable composition and good crystal quality cannot be obtained in the prior art is solved.

The invention relates to a photodiode. The photodiode includes a carrier generation region of a semiconductor having a band gap that absorbs light of a given wavelength such that charge carriers are generated therein. The photodiode further includes n-doped and p-doped semiconductor regions, each of which has a higher band gap than the band gap of the carrier generation region, each of which is transparent to light of a given wavelength, the n-doped and p-doped semiconductor regions being along different sides of the carrier generation region. The photodiode further includes an interface region between the carrier generation region and a given doped region of the n-doped and p-doped semiconductor regions, the interface region including one or more of a semiconductor alloy and a semiconductor sequence that is one or more of a gradient and a step in composition, the band offset is selected to reduce band offset between the carrier generation region and a given doped region adjacent to the interface region.

Aspects of the present disclosure relate to a 3D-millimeter wave integrated circuit (3D-mmWIC configured to improve the efficiency and functionality of radio-frequency (RF) circuits through a multi-material, multi-layered architecture. These aspects can integrate silicon-based complementary metal-oxide semiconductor (CMOS) technology with other semiconductor materials, including Gallium Nitride (GaN), graphene, and / or various semiconductor alloys from the periodic table's Groups II-VI and / or III-V. The 3D-mmWIC can employ a layered structure comprising a silicon substrate, interleaved dielectric layers with embedded metal regions of varying thicknesses and lengths, a semiconductor layer, and / or additional oxide and dielectric layers. This architecture can enable the integration of multiple source, drain, and gate modules, interconnected via a sophisticated metal / oxide network. The disclosed integrated circuit architecture can provide significant advancements in RF circuit integration, offering reductions in size and cost while increasing design flexibility and performance.

InxAlyGa1-x-yN semiconductor structures having optoelectronic elements characterized by epitaxial layers having different in-plane a-lattice parameters and different InN mole fractions are disclosed. The active regions are configured to emit radiation in different wavelength ranges and are characterized by strain states within about 1% to 2% of compressive strain. The epitaxial layers are grown on patterned InxAlyGa1-x-yN seed regions on a single substrate, where the relaxed InGaN growth layers provide (0001) InxAlyGa1-x-yN growth surfaces characterized by different in-plane a-lattice parameters and different InN mole fractions. InxAlyGa1-x-yN semiconductor structures can be used in optoelectronic devices such as in light sources for illumination and in display applications.

A semiconductor device includes a barrier region and a channel region, source and drain electrodes, and a gate structure that is configured to control a conductive connection between the source and drain electrodes, wherein the barrier region comprises a first barrier layer and a second barrier layer, wherein in a central portion of the device the second barrier layer is the only layer that is disposed over the channel region, wherein in outer lateral portions of the device the first barrier layer is disposed over the channel region, wherein the first and second barrier layers are each III-V semiconductor alloys, and wherein a molar fraction of a second type III element in the central portion is higher than a molar fraction of the second type III element in the first barrier layer.

InxAlyGa1-x-yN semiconductor structures having optoelectronic elements characterized by epitaxial layers having different in-plane a-lattice parameters and different InN mole fractions are disclosed. The active regions are configured to emit radiation in different wavelength ranges and are characterized by strain states within about 1% to 2% of compressive strain. The epitaxial layers are grown on patterned InxAlyGa1-x-yN seed regions on a single substrate, where the relaxed InGaN growth layers provide (0001) InxAlyGa1-x-yN growth surfaces characterized by different in-plane a-lattice parameters and different InN mole fractions. InxAlyGa1-x-yN semiconductor structures can be used in optoelectronic devices such as in light sources for illumination and in display applications.

A method includes depositing an inter-layer dielectric (ILD) over a source / drain region; forming a contact opening through the ILD, wherein the contact opening exposes the source / drain region; forming a metal-semiconductor alloy region on the source / drain region; depositing a first layer of a conductive material on the metal-semiconductor alloy region; depositing an isolation material along sidewalls of the contact opening and over the first layer of the conductive material; etching the isolation material to expose the first layer of the conductive material, wherein the isolation material extends along sidewalls of the contact opening after etching the isolation material; and depositing a second layer of the conductive material on the first layer of the conductive material.

The present invention provides a semiconductor device structure having multiple gate terminals and a method of forming the same. The present invention provides an integrated circuit including a field effect transistor having a metal-semiconductor contact and more than one gate terminal. In the present invention, an integrated circuit of a field effect transistor having multiple gate contacts (105) is proposed, and the multiple gate contacts (105) are preferably independent. Using the same channel (101) and a common source-drain contact formed by a metal-semiconductor contact at the channel ends, the gate contacts (105) are adjacent to each other. The present invention includes a method of forming an accurate metal-semiconductor alloy contact (124) at the ends of a channel (101) below an appropriate gate (105) of a transistor having multiple gate terminals, which is compatible with the dense integration of multiple gate contacts adjacent to each other using the same channel.

The invention belongs to the technical field of alloys, and discloses a copper-barium-tin-sulfur-selenium five-element semiconductor alloy and a preparation method thereof, wherein the atomic ratio of the elements in the alloy is: copper 1.5-2, barium 0.7-1, tin 0.7-1, sulfur 1.8-2.5, selenium 2-2.5; the preparation method of the alloy comprises: according to the above atomic ratio, each weighed preparation raw material is smelted in a vacuum and protective atmosphere in stages to obtain a copper-barium-tin-sulfur semiconductor alloy; then the copper-barium-tin-sulfur semiconductor alloy and the weighed selenium particles are placed in a graphite box together, and selenization treatment is continued in a protective gas atmosphere to obtain a copper-barium-tin-sulfur-selenium five-element semiconductor alloy. The novel copper-barium-tin-sulfur five-element semiconductor alloy prepared by the invention is a P-type semiconductor, and the material can be applied to solar cells and other fields.

A light-emitting diode manufacturing method, including the successive steps of: a) forming an active layer including a stack of multiple quantum wells, each quantum well including a layer made of a semiconductor alloy; b) forming a trench for singularizing the diode, the trench crossing the active layer; and c) applying to the sides of the active layer, at the level of the lateral walls of the trench, a chemical treatment capable of etching a first component of the semiconductor alloy selectively over at least another component of the semiconductor alloy, wherein the bandgap width of the semiconductor alloy is a function of the concentration of the first component in the alloy.

A photodiode (200) comprises a carrier generating region (206) of a semiconductor having a bandgap that absorbs light (205) of a given wavelength, such that electrical charge carriers are generated therein. The photodiode further comprises a n-doped (210) and a p-doped (208) semiconductor region having respective bandgaps higher than the bandgap of the carrier generating region, the respective bandgaps being transparent to the light of the given wavelength, the n-doped and p-doped semiconductor region being along different sides of the carrier generating region. The photodiode further comprises an interface region (211) between the carrier generating region and a given doped region of the n-doped and the p-doped semiconductor region, the interface region comprising one or more of a semiconductor alloy and a semiconductor sequence that is one or more of graded and stepped in composition, selected to reduce a band offset (222) between the carrier generating region and the given doped region adjacent the interface region.

In an embodiment, a method includes: depositing a protective layer on a source / drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source / drain region; etching an opening through the protective layer, the opening exposing the source / drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source / drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.

A method includes patterning a first opening through a first dielectric layer, a first source / drain region, and a second dielectric layer to expose a second source / drain region; forming a first dielectric liner along sidewalls of the first opening, wherein the second source / drain region is exposed; forming a first metal-semiconductor alloy region in the first opening along the second source / drain region; depositing a first conductive material to fill a remainder of the first opening; patterning a second opening through the first dielectric layer to expose the first source / drain region; forming a second dielectric liner along sidewalls of the second opening, wherein the first source / drain region is exposed; forming a second metal-semiconductor alloy region in the second opening along the first source / drain region; and depositing a second conductive material to fill a remainder of the second opening.

An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers can be formed as electrically conductive layers, or can be subsequently replaced with electrically conductive layers. Memory openings can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which can optionally be partially or fully converted to silicon nitride material portions. The semiconductor material portions and / or the silicon nitride material portions can be used as discrete charge storage elements.

The utility model provides a packaging structure for improving the voltage resistance and creepage distance of a high-voltage SLIC chip, and the chip. The packaging structure comprises an LV chip, an HV chip, pins, an insulation reinforcement body, and a carrier. The LV chip and the HV chip are fixed on the surface of the carrier in an insulating manner, the pins are fixedly arranged at the periphery of the carrier, the pins are electrically connected with the LV chip through semiconductor bonding gold wires, and the pins are electrically connected with the HV chip through semiconductor bonding gold wires; the pins comprise high-voltage pins and low-voltage pins, and the distance between the high-voltage pins is larger than that between the low-voltage pins; the insulation reinforcement body is arranged between the HV chip and the carrier, and the top surface and the bottom surface of the insulation reinforcement body are fixedly connected with the HV chip and the carrier respectively. According to the utility model, the physical creepage distance between the high-voltage pins can be effectively increased, and the insulation thickness between the high-voltage chip and the bottom plate is increased, so that the safety performance of the product is improved, and the voltage endurance capability is improved.

In an embodiment, a method includes: depositing a protective layer on a source / drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source / drain region; etching an opening through the protective layer, the opening exposing the source / drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source / drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.

A method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a plurality of sacrificial layers that alternate with a plurality of channel layers, forming a dummy gate stack over a top surface and sidewalls of the multi-layer stack, forming first spacers on sidewalls of the dummy gate stack, growing an epitaxial source / drain region that extends through the plurality of sacrificial layers and the plurality of channel layers, forming a metal-semiconductor alloy region on first portions of the epitaxial source / drain region, forming a coating layer on the metal-semiconductor alloy region, wherein during the forming of the metal-semiconductor alloy region and the coating layer, a residual layer is formed on sidewalls of the first spacers, and performing a wet clean process to selectively etch the residual layer from the sidewalls of the first spacers.

In an embodiment, a method of forming a semiconductor device includes depositing a protective layer over a source / drain region and a gate mask, the gate mask disposed over a gate structure, the gate structure disposed over a channel region of a substrate, the channel region contiguous to the source / drain region; etching an opening through the protective layer, the opening exposing the source / drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source / drain region; and removing residue of the metal from the opening using a cleaning process, the protective layer covering the gate mask during the cleaning process. According to other embodiments of the application, a semiconductor device is also provided.