25 results about "Semiconductor alloys" patented technology

The present invention relates to a method for obtaining a doped semiconductor layer, comprising the following sequential steps: a) implanting ions of a first dopant element B and a second undoped element C of a semiconductor alloy, which is made of at least a first element A1 and a second element A2, into a first single crystal layer to amorphize the upper part of the first layer and maintain the crystal structure of the lower part of the first layer; and b) subjecting the upper part of the first layer to solid-state recrystallization annealing, thereby transforming the upper part of the first layer into a doped single crystal layer of the alloy.

The invention relates to the technical field of solar cells, and particularly discloses a crystalline silicon thermal electron solar cell and a photovoltaic module, which comprise a silicon substrate, and the silicon substrate comprises a P-type region and an n-type region positioned on one side of an illumination surface of the P-type region; the illumination surface of the silicon substrate is provided with a silver collection gate electrode, and the back side of the silicon substrate is provided with a silver extraction electrode; an Ag-Si semiconductor alloy junction is arranged at the position, corresponding to the silver collection gate electrode, in the silicon substrate, an n-type ultra-shallow diffusion layer is formed on the outer side of the Ag-Si semiconductor alloy junction, an n-P junction is formed between the n-type ultra-shallow diffusion layer and the P-type region, and the n-P junction and the n-P junction form a three-dimensional PN junction quantum well; the silver collection gate electrode and the Ag-Si semiconductor alloy structure form a contact electrode. Thermo-electron transmission is accelerated, thermo-electron extraction and utilization are realized, and the photoelectric conversion efficiency is further improved.

In an embodiment, a device includes: a source / drain region adjacent a channel region; an inter-layer dielectric on the source / drain region; a source / drain contact extending through the inter-layer dielectric and into the source / drain region; a metal-semiconductor alloy region between the source / drain contact and the source / drain region, the metal-semiconductor alloy region disposed beneath a top surface of the channel region, the metal-semiconductor alloy region including a first dopant; and a contact spacer around the source / drain contact, the contact spacer including the first dopant and an amorphizing impurity.

The example relates to a method for fabricating a semiconductor structure having multiple quantum wells. The method includes: providing a substrate comprising a binary semiconductor compound having a first lattice constant; depositing at least a first layer on the substrate and a second layer in contact with the first layer to form a first stack of substantially planar semiconductor layers on the substrate, the first layer being a first semiconductor alloy comprising InP, and the second layer being a second semiconductor alloy comprising InP; depositing a third layer of the binary semiconductor compound having the first lattice constant in contact with the first stack; depositing at least a fourth layer on the third layer and a fifth layer in contact with the fourth layer to form a second stack of substantially planar semiconductor layers on the third layer, the fourth layer comprising a third semiconductor alloy containing InP, and the fifth layer comprising a fourth semiconductor alloy containing InP.

A semiconductor device and the method of forming are provided. The semiconductor device may include a first dielectric layer, a first source / drain region in the first dielectric layer, a first nanostructure on a sidewall of the first source / drain region, a first gate structure around the first nanostructure, a first conductive contact electrically connected to the first source / drain region, and a first metal-semiconductor alloy region between the first portion of the first conductive contact and the first source / drain region. A first portion of the first conductive contact may extend through the first source / drain region, and the first portion of the first conductive contact comprises a first sidewall and a second sidewall opposite the first sidewall in a cross-sectional view. A first portion of the first metal-semiconductor alloy region may be on the first sidewall and a second portion of the first metal-semiconductor alloy region may be on the second sidewall.

The application discloses a preparation method of a group IV compound epitaxial alloy thin film. It relates to the technical field of semiconductor alloy thin film growth, and comprises the following steps: placing initial silicon single crystal particles and target doped group IV metal single crystal particles with a preset atomic mole ratio on the surface of a reaction substrate; after a target vacuum degree and a target heating temperature are reached in a preparation device, the target doped group IV metal single crystal particles become a molten state, a target metal solution is obtained, the initial silicon single crystal particles are dissolved in the target metal solution, and a reaction metal solution is formed; a carrier gas and a carbon-containing reaction gas are introduced into the preparation device, the carbon-containing reaction gas contacts the surface of the reaction metal solution and is cracked to form carbon reaction atoms, the carbon reaction atoms diffuse and react in the reaction metal solution, and a group IV compound epitaxial alloy thin film is formed. Through the application, the problem that an epitaxial multi-component alloy thin film with high metal concentration, controllable composition and good crystal quality cannot be obtained in the prior art is solved.

Aspects of the present disclosure relate to a 3D-millimeter wave integrated circuit (3D-mmWIC configured to improve the efficiency and functionality of radio-frequency (RF) circuits through a multi-material, multi-layered architecture. These aspects can integrate silicon-based complementary metal-oxide semiconductor (CMOS) technology with other semiconductor materials, including Gallium Nitride (GaN), graphene, and / or various semiconductor alloys from the periodic table's Groups II-VI and / or III-V. The 3D-mmWIC can employ a layered structure comprising a silicon substrate, interleaved dielectric layers with embedded metal regions of varying thicknesses and lengths, a semiconductor layer, and / or additional oxide and dielectric layers. This architecture can enable the integration of multiple source, drain, and gate modules, interconnected via a sophisticated metal / oxide network. The disclosed integrated circuit architecture can provide significant advancements in RF circuit integration, offering reductions in size and cost while increasing design flexibility and performance.

InxAlyGa1-x-yN semiconductor structures having optoelectronic elements characterized by epitaxial layers having different in-plane a-lattice parameters and different InN mole fractions are disclosed. The active regions are configured to emit radiation in different wavelength ranges and are characterized by strain states within about 1% to 2% of compressive strain. The epitaxial layers are grown on patterned InxAlyGa1-x-yN seed regions on a single substrate, where the relaxed InGaN growth layers provide (0001) InxAlyGa1-x-yN growth surfaces characterized by different in-plane a-lattice parameters and different InN mole fractions. InxAlyGa1-x-yN semiconductor structures can be used in optoelectronic devices such as in light sources for illumination and in display applications.

InxAlyGa1-x-yN semiconductor structures having optoelectronic elements characterized by epitaxial layers having different in-plane a-lattice parameters and different InN mole fractions are disclosed. The active regions are configured to emit radiation in different wavelength ranges and are characterized by strain states within about 1% to 2% of compressive strain. The epitaxial layers are grown on patterned InxAlyGa1-x-yN seed regions on a single substrate, where the relaxed InGaN growth layers provide (0001) InxAlyGa1-x-yN growth surfaces characterized by different in-plane a-lattice parameters and different InN mole fractions. InxAlyGa1-x-yN semiconductor structures can be used in optoelectronic devices such as in light sources for illumination and in display applications.

A method includes depositing an inter-layer dielectric (ILD) over a source / drain region; forming a contact opening through the ILD, wherein the contact opening exposes the source / drain region; forming a metal-semiconductor alloy region on the source / drain region; depositing a first layer of a conductive material on the metal-semiconductor alloy region; depositing an isolation material along sidewalls of the contact opening and over the first layer of the conductive material; etching the isolation material to expose the first layer of the conductive material, wherein the isolation material extends along sidewalls of the contact opening after etching the isolation material; and depositing a second layer of the conductive material on the first layer of the conductive material.

A light-emitting diode manufacturing method, including the successive steps of: a) forming an active layer including a stack of multiple quantum wells, each quantum well including a layer made of a semiconductor alloy; b) forming a trench for singularizing the diode, the trench crossing the active layer; and c) applying to the sides of the active layer, at the level of the lateral walls of the trench, a chemical treatment capable of etching a first component of the semiconductor alloy selectively over at least another component of the semiconductor alloy, wherein the bandgap width of the semiconductor alloy is a function of the concentration of the first component in the alloy.

In an embodiment, a method includes: depositing a protective layer on a source / drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source / drain region; etching an opening through the protective layer, the opening exposing the source / drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source / drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.

A method includes patterning a first opening through a first dielectric layer, a first source / drain region, and a second dielectric layer to expose a second source / drain region; forming a first dielectric liner along sidewalls of the first opening, wherein the second source / drain region is exposed; forming a first metal-semiconductor alloy region in the first opening along the second source / drain region; depositing a first conductive material to fill a remainder of the first opening; patterning a second opening through the first dielectric layer to expose the first source / drain region; forming a second dielectric liner along sidewalls of the second opening, wherein the first source / drain region is exposed; forming a second metal-semiconductor alloy region in the second opening along the first source / drain region; and depositing a second conductive material to fill a remainder of the second opening.

An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers can be formed as electrically conductive layers, or can be subsequently replaced with electrically conductive layers. Memory openings can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which can optionally be partially or fully converted to silicon nitride material portions. The semiconductor material portions and / or the silicon nitride material portions can be used as discrete charge storage elements.

In an embodiment, a method includes: depositing a protective layer on a source / drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source / drain region; etching an opening through the protective layer, the opening exposing the source / drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source / drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.

A method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a plurality of sacrificial layers that alternate with a plurality of channel layers, forming a dummy gate stack over a top surface and sidewalls of the multi-layer stack, forming first spacers on sidewalls of the dummy gate stack, growing an epitaxial source / drain region that extends through the plurality of sacrificial layers and the plurality of channel layers, forming a metal-semiconductor alloy region on first portions of the epitaxial source / drain region, forming a coating layer on the metal-semiconductor alloy region, wherein during the forming of the metal-semiconductor alloy region and the coating layer, a residual layer is formed on sidewalls of the first spacers, and performing a wet clean process to selectively etch the residual layer from the sidewalls of the first spacers.

In an embodiment, a method of forming a semiconductor device includes depositing a protective layer over a source / drain region and a gate mask, the gate mask disposed over a gate structure, the gate structure disposed over a channel region of a substrate, the channel region contiguous to the source / drain region; etching an opening through the protective layer, the opening exposing the source / drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source / drain region; and removing residue of the metal from the opening using a cleaning process, the protective layer covering the gate mask during the cleaning process. According to other embodiments of the application, a semiconductor device is also provided.

In an embodiment, a device includes: a source / drain region adjacent a channel region; an inter-layer dielectric on the source / drain region; a source / drain contact extending through the inter-layer dielectric and into the source / drain region; a metal-semiconductor alloy region between the source / drain contact and the source / drain region, the metal-semiconductor alloy region disposed beneath a top surface of the channel region, the metal-semiconductor alloy region including a first dopant; and a contact spacer around the source / drain contact, the contact spacer including the first dopant and an amorphizing impurity.

1. Name of the product in this design: High-Temperature Combustion Ion Chromatograph. 2. Application of this design: for quantitative analysis of halogens and sulfur in samples such as soil, biomass, waste, petroleum, natural gas, semiconductors, and alloy materials. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key features: the front view.

A method includes depositing an inter-layer dielectric (ILD) over a source / drain region; forming a contact opening through the ILD, wherein the contact opening exposes the source / drain region; forming a metal-semiconductor alloy region on the source / drain region; depositing a first layer of a conductive material on the metal-semiconductor alloy region; depositing an isolation material along sidewalls of the contact opening and over the first layer of the conductive material; etching the isolation material to expose the first layer of the conductive material, wherein the isolation material extends along sidewalls of the contact opening after etching the isolation material; and depositing a second layer of the conductive material on the first layer of the conductive material.

The method includes: patterning a first opening through a first dielectric layer, a first source / drain region, and a second dielectric layer to expose a second source / drain region; forming a first dielectric liner along sidewalls of the first opening with the second source / drain region exposed; forming a first metal-semiconductor alloy region in the first opening along the second source / drain region; depositing a first conductive material to fill a remaining portion of the first opening; patterning a second opening through the first dielectric layer to expose the first source / drain region; forming a second dielectric liner along sidewalls of the second opening with the first source / drain region exposed; forming a second metal-semiconductor alloy region in the second opening along the first source / drain region; and depositing a second conductive material to fill a remaining portion of the second opening. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Semiconductor devices and methods of forming the same are provided. The semiconductor device may include a first dielectric layer, a first source / drain region in the first dielectric layer, a first nanostructure on a sidewall of the first source / drain region, a first gate structure around the first nanostructure, and a second gate structure around the first gate structure. A first conductive contact electrically connected to the first source / drain region; and a first metal semiconductor alloy region between a first portion of the first conductive contact and the first source / drain region. A first portion of the first conductive contact may extend through the first source / drain region, and in a cross-sectional view, the first portion of the first conductive contact includes a first sidewall and a second sidewall opposite the first sidewall. A first portion of the first metal semiconductor alloy region may be located on the first sidewall, and a second portion of the first metal semiconductor alloy region may be located on the second sidewall.

The invention belongs to the technical field of alloys, and particularly relates to a copper-indium-tin-selenium quaternary semiconductor alloy and a preparation method and application thereof. The atomic ratio of the elements in the alloy is as follows: copper is 2.2-3, indium is 0.7-1, tin is 0.7-1, and selenium is 4-5; the preparation method of the alloy comprises the following steps: according to the atomic ratio, the weighed raw materials are subjected to one-step smelting in a vacuum and protective atmosphere to obtain the copper-indium-tin-selenium semiconductor alloy. The prepared novel copper-indium-tin-selenium quaternary semiconductor alloy is a P-type semiconductor and can be applied to the photo-thermal and photoelectric conversion related fields such as solar cells.

The invention discloses an In < x > Al < y > Ga < 1-x-y > N semiconductor structure with a photoelectric element. The photoelectric element is characterized by an epitaxial layer with different in-plane a-lattice parameters and different InN mole fractions. The active region is configured to emit radiation in different wavelength ranges, and is characterized by a strain state that differs from compressive strain by about 1% to 2%. The epitaxial layer is grown on a patterned In < x > Al < y > Ga < 1-x-y > N seed region on a single substrate, wherein the relaxed InGaN growth layer provides a (0001) In < x > Al < y > Ga < 1-x-y > N growth surface characterized by different in-plane a-lattice parameters and different InN molar fractions. The InxAlyGa1-x-yN semiconductor structure can be used in optoelectronic devices, such as in light sources for illumination and in display applications.

The invention discloses a preparation method of an epitaxial alloy film of IV-group compounds. The method relates to the technical field of semiconductor alloy film growth, and comprises the following steps: placing initial silicon single crystal particles and target doped group IV metal single crystal particles with a preset atom molar ratio on the surface of a reaction substrate; after the target vacuum degree and the target heating temperature are reached in the preparation device, the target doped group IV metal single crystal particles become a molten state to obtain a target metal solution, and the initial single silicon crystal particles are dissolved in the target metal solution to form a reaction metal solution; carrier gas and carbon-containing reaction gas are introduced into the preparation device, the carbon-containing reaction gas makes contact with the surface of the reaction metal solution and is cracked to form carbon reaction atoms, the carbon reaction atoms diffuse and react in the reaction metal solution, and the IV-group compound epitaxial alloy film is formed. According to the invention, the problem that an epitaxial multi-component alloy film with high metal concentration, controllable components and good crystal quality cannot be obtained in the prior art is solved.