16 results about "Metal semiconductor" patented technology

In an embodiment, a method is described that includes forming a source / drain region having a first base material composition and a first concentration of a first conductivity type dopant; removing a portion of the source / drain region having the first base material composition and the first concentration of the first conductivity type dopant to expose a contact surface; and forming a contact layer on the contact surface. The contact layer comprises a second composition and has a second concentration of the first conductivity type dopant, wherein the second concentration is greater than the first concentration for the first conductivity type dopant. A metal is deposited on the contact layer, wherein an interface between the metal and the contact layer includes a metal semiconductor alloy.

This invention discloses a method for preparing van der Waals metal thin films. The method includes the following steps: S1, coating a polyvinyl alcohol (PVA) film onto the surface of a supporting substrate; S2, depositing a metal film on the surface of the PVA film to obtain an intermediate; S3, placing the intermediate in water at 60-80°C to remove the PVA film, obtaining a floating metal film; transferring the metal film to the surface of a target substrate, and bonding the two together using van der Waals forces to obtain the final product. This invention utilizes the controllable dissolution properties of PVA, achieving the separation and transfer of the metal film from the supporting substrate using deionized water, avoiding the use of toxic chemical solvents and interface damage caused by high-energy bombardment. The method is simple, environmentally friendly, and can be widely applied to the preparation of van der Waals heterostructures such as metal-semiconductor and metal-insulator structures.

A metal-semiconductor contact structure and a preparation method thereof, a solar cell and a photovoltaic module are provided. The metal-semiconductor contact structure includes a metal electrode and a semiconductor layer in contact with each other. The metal electrode has a metal 5 element, and the semiconductor layer has a semiconductor element and a doping element for doping the semiconductor layer. A contact interface between the metal electrode and the semiconductor layer has a hole and a conductive structure. The conductive structure includes a conductive eutectic adjacent to the semiconductor layer, and a conductive crystal extending from the conductive eutectic into the hole. The conductive eutectic includes a eutectic formed by the 10 metal element and the semiconductor element, and the conductive crystal includes a crystal formed by crystallization of the metal element. [FIG. 1] 20 25 20 20 63 21 M ar 2 02 5 A B S T R A C T 2 0 2 5 2 0 2 0 6 3 2 1 M a r 2 0 2 5 A m e t a l - s e m i c o n d u c t o r c o n t a c t s t r u c t u r e a n d a p r e p a r a t i o n m e t h o d t h e r e o f , a s o l a r c e l l a n d a p h o t o v o l t a i c m o d u l e a r e p r o v i d e d . T h e m e t a l - s e m i c o n d u c t o r c o n t a c t s t r u c t u r e i n c l u d e s a m e t a l e l e c t r o d e a n d a s e m i c o n d u c t o r l a y e r i n c o n t a c t w i t h e a c h o t h e r . T h e m e t a l e l e c t r o d e h a s a m e t a l 5 e l e m e n t , a n d t h e s e m i c o n d u c t o r l a y e r h a s a s e m i c o n d u c t o r e l e m e n t a n d a d o p i n g e l e m e n t f o r d o p i n g t h e s e m i c o n d u c t o r l a y e r . A c o n t a c t i n t e r f a c e b e t w e e n t h e m e t a l e l e c t r o d e a n d t h e s e m i c o n d u c t o r l a y e r h a s a h o l e a n d a c o n d u c t i v e s t r u c t u r e . T h e c o n d u c t i v e s t r u c t u r e i n c l u d e s a c o n d u c t i v e e u t e c t i c a d j a c e n t t o t h e s e m i c o n d u c t o r l a y e r , a n d a c o n d u c t i v e c r y s t a l e x t e n d i n g f r o m t h e c o n d u c t i v e e u t e c t i c i n t o t h e h o l e . T h e c o n d u c t i v e e u t e c t i c i n c l u d e s a e u t e c t i c f o r m e d b y t h e 1 0 m e t a l e l e m e n t a n d t h e s e m i c o n d u c t o r e l e m e n t , a n d t h e c o n d u c t i v e c r y s t a l i n c l u d e s a c r y s t a l f o r m e d b y c r y s t a l l i z a t i o n o f t h e m e t a l e l e m e n t . [ F I G . 1 ] A B S T R A C T 2 0 2 5 2 0 2 0 6 3 2 1 M a r 2 0 2 5 5 2 / 4 FIG. 3 FIG. 4 2 / 4 1a 1222 122 1221 121 13 FIG. 3 301 701 1 201 601 100 602 202 702 302 FIG. 4 20 25 20 20 63 21 M ar 2 02 5 2 / 4 2 1 M a r 2 0 2 5 l a 1 2 2 2 1 2 2 2 0 2 5 2 0 2 0 6 3 1 2 2 1 1 2 1 1 3 F I G . 3 3 0 1 7 0 1 1 2 0 1 6 0 1 1 0 0 6 0 2 2 0 2 7 0 2 3 0 2 F I G . 4 2 1 M a r 2 0 2 5 l a 2 0 2 5 2 0 2 0 6 3 1 2 2 1 1 3 1 0 0 6 0 2

An electrically-dissipative coating comprises an electrically-dissipative material, wherein the electrically-dissipative coating is uniform and conformal, wherein the electrically-dissipative coating has a thickness ranging from about 10 nm to about 900 nm, and wherein the electrically-dissipative coating comprises one or more first material-containing layers and one or more second material-containing layers, the one or more first material-containing layers consisting of a metal or a metal alloy comprising at least one of Al, Y—Zr, Mg—Al, or Ca—Al, and the one or more second material-containing layers consisting of a transition metal, a rare earth, a main group metal, a semiconductor, or an alloy thereof.

This invention belongs to the field of semiconductor device technology, specifically relating to a method for fabricating a flexible ZnO ultraviolet photodetector using full screen printing. Through a full screen printing process, the integrated fabrication of the flexible ZnO ultraviolet detector is achieved. The process is simple, low-cost, and suitable for large-area manufacturing. This invention sequentially fabricates a ZnO photosensitive layer and silver interdigitated electrodes via screen printing, followed by optimized heat treatment and low-temperature curing to form a metal-semiconductor-metal structure device. Through synergistic optimization of ink formulation, printing process, and electrode structure, the photoresponse current is effectively improved while maintaining a high light-to-dark current ratio and responsivity.

The method for preparing ohmic contact on intrinsic diamond surface by using iron catalysis solves the problems of large energy loss of semiconductor device at metal-semiconductor contact and the like.The method for preparing ohmic contact comprises the following steps: uniformly gluing treatment on the cleaned diamond, then photoetching treatment, then magnetron sputtering deposition of Fe layer on the photoetched diamond surface, then cleaning and degumming, then placing the diamond with Fe plated on the surface into a quartz tube for sealing, then filling the quartz tube with protective gas, then transferring to a tube furnace, and then annealing treatment at 800-950 DEG C, so as to prepare ohmic contact on the intrinsic diamond surface.The minimum contact resistivity is obtained by controlling the annealing temperature and time, the conductivity is greatly improved, the contact binding performance is good and the device can work stably for a long time, the lead difficulty is reduced due to the existence of Fe, the mechanically stable contact is easily formed on the surface, the temperature of surface graphitization is reduced, and the preparation process is simplified.

a kind of nC 60+ Fullerene meteorite-based radar and communication antenna technology solution, nC 60+ This approach utilizes focused ion beam electromagnetic field technology, which leverages shared ionic bonds and large π-bonded covalent bonds; micro / nano electronic grid resonant cavities formed by laser direct writing and sintering of large π-bonded electron clouds; and selective terahertz wave propagation technology using metal, semiconductor, and CMOS chips directly written onto micro / nano electronic grid resonant arrays and phased arrays. This scheme enables antennas to become superconducting tools for transmitting and receiving optical and electromagnetic waves. Applications include long-distance terahertz weak signal communication, radar, "black holes" and "light boxes" for optical and electromagnetic waves (such as terahertz wave absorption or submersion – used for stealth), imaging detection, sensitive wave identification, and selective sensing. 60+ Fullerene meteorite-like materials, including laboratory-produced nC60. + and having nC 60+ Mineral or synthetic polymer substitutes with a particular strength or complementarity.

The application discloses a two-dimensional metal semiconductor vertical heterojunction NbS2 / MoS2 and a preparation method and application thereof, and the method comprises the following steps: taking a sapphire as a substrate by sequentially spin-coating NaCl aqueous solution and NbCl5 isopropyl alcohol solution, introducing H2S gas and an inert gas flow carrying a Mo gaseous precursor into a reaction cavity at 850 DEG C, introducing H2 at the same time, and epitaxially growing a single-layer MoS2 triangle domain on the substrate; the temperature of the reaction cavity is increased to above 980 DEG C, H2S and an inert gas flow carrying a Nb gaseous precursor are introduced, NbS2 is grown on the single-layer MoS2 triangle domain, and the NbS2 / MoS2 vertical heterojunction is formed. The application realizes selective vertical epitaxial growth of NbS2 on the MoS2 triangle domain, constructs the NbS2 / MoS2 vertical heterojunction with an atom-level sharp interface and a highly consistent crystal lattice orientation, and has a wide application prospect in the fields of photoelectric devices, electronic devices and sensors.

A method includes patterning a first opening through a first dielectric layer, a first source / drain region, and a second dielectric layer to expose a second source / drain region; forming a first dielectric liner along sidewalls of the first opening, wherein the second source / drain region is exposed; forming a first metal-semiconductor alloy region in the first opening along the second source / drain region; depositing a first conductive material to fill a remainder of the first opening; patterning a second opening through the first dielectric layer to expose the first source / drain region; forming a second dielectric liner along sidewalls of the second opening, wherein the first source / drain region is exposed; forming a second metal-semiconductor alloy region in the second opening along the first source / drain region; and depositing a second conductive material to fill a remainder of the second opening.

The present invention provides a method for manufacturing semiconductor devices that improves the integration density and reliability of semiconductor devices. [Solution] The method comprises the steps of: removing a portion of the interlayer insulating layer and the source / drain region to form a contact hole; forming a metal-semiconductor compound layer on the lower end of the contact hole; forming a liner conductive layer on the metal-semiconductor compound layer so as to cover the side surface of the contact hole; selectively oxidizing the liner conductive layer formed on the metal-semiconductor compound layer; selectively removing the oxidized liner conductive layer; forming a preliminary contact conductive layer on the liner conductive layer; forming a sacrificial metal layer on the preliminary contact conductive layer; removing a portion of the sacrificial metal layer and the preliminary contact conductive layer by a planarization process; and forming a contact conductive layer by heat treatment of the preliminary contact conductive layer using hydrogen plasma.

The application provides a kind of 0BB solar cell laser-induced sintering device, including bearing platform, electric input module and laser module, battery piece is placed on bearing platform, electric input module includes power supply and first electrode and second electrode for being connected with power supply, first electrode and second electrode can be contacted with the upper surface, lower surface of battery piece respectively;First electrode includes multiple probe rows, multiple probes are arranged on each probe row along the length direction of probe row, when first electrode is contacted with the upper surface of battery piece, the probes on multiple probe rows are staggered on the upper surface of battery piece, all fine grid lines on the upper surface of battery piece are pressed, reverse bias is applied to battery piece by first electrode and second electrode, laser-induced sintering is carried out on battery piece under the irradiation of laser, and excellent metal-semiconductor contact structure is obtained.

A method of manufacturing a semiconductor device includes: forming source / drain regions; forming an interlayer insulating layer on the source / drain regions; forming a contact hole to expose the source / drain regions by removing at least a portion of the interlayer insulating layer; forming a metal semiconductor compound layer in the contact hole to connect to the source / drain regions; forming a pad conductive layer on the metal semiconductor compound layer; oxidizing the pad conductive layer; removing the oxidized portion of the pad conductive layer; and forming a contact conductive layer on the pad conductive layer.

A method of manufacturing a semiconductor device, includes: forming a source / drain region; forming an interlayer insulating layer on the source / drain region; forming a contact hole by removing at least a portion of the interlayer insulating layer to expose the source / drain region; forming a metal-semiconductor compound layer in the contact hole to be connected to the source / drain region; forming a liner conductive layer on the metal-semiconductor compound layer; and oxidizing the liner conductive layer; removing an oxidized portion of the liner conductive layer; and forming a contact conductive layer on the liner conductive layer.

The method includes: patterning a first opening through a first dielectric layer, a first source / drain region, and a second dielectric layer to expose a second source / drain region; forming a first dielectric liner along sidewalls of the first opening with the second source / drain region exposed; forming a first metal-semiconductor alloy region in the first opening along the second source / drain region; depositing a first conductive material to fill a remaining portion of the first opening; patterning a second opening through the first dielectric layer to expose the first source / drain region; forming a second dielectric liner along sidewalls of the second opening with the first source / drain region exposed; forming a second metal-semiconductor alloy region in the second opening along the first source / drain region; and depositing a second conductive material to fill a remaining portion of the second opening. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

One-time programmable (OTP) bit-cell for an integrated circuit (IC) that includes an OTP element, such as a fuse or antifuse, coupled in electrical series with a selector that comprises a Schottky junction. The selector may comprise a metal-semiconductor-metal (MSM) material stack operable as transient voltage suppression (TVS) device that experiences electrical breakdown at a voltage below a programming voltage of the OTP element. In response to a programming voltage, the MSM stack may breakdown and pass a transient current sufficient for programming the OTP element. In response to a lower (e.g., read) voltage, the MSM stack may breakdown and pass a transient current insufficient for programming, but sufficient to sense a state of the OTP element. In response to an even lower (e.g., half-read) voltage, the MSM stack may present a very high OTP bit-cell input impedance, reducing leakage and / or sneak path currents within an array of such bit-cells.

This invention discloses a novel photovoltaic cell structure, comprising a lower electrode P-type silicon semiconductor layer and an upper electrode N-type silicon semiconductor layer. One side of the N-type silicon semiconductor layer is a periodically structured three-dimensional surface. A transparent carbon-based electrode material layer is disposed on the three-dimensional structured surface, and the transparent carbon-based electrode material layer is tightly bonded to the three-dimensional structured surface. This novel photovoltaic cell structure enhances the surface light scattering capability and improves its stability and controllability by designing the N-type semiconductor side of the photovoltaic cell as a periodically structured three-dimensional surface. A layer of carbon-based transparent electrode material (such as graphene, carbon nanotubes, etc.) tightly bonded to the structured surface serves as the upper electrode, improving light scattering performance and effectively avoiding the problem of poor metal-semiconductor contact due to the small work function difference between carbon and silicon, which belong to the same group.