151 results about "Metal semiconductor" patented technology

The invention discloses a vortex beam orbital angular momentum detector based on surface plasmon and a detection method, and belongs to the field of micro-nano photonics and photoelectric detection. The detector is based on a plane photoelectric detector of a metal-semiconductor-metal type, a vortex light field beam splitting structure is arranged on a metal electrode on one side of the detector or between two metal electrodes, the vortex light field beam splitting structure comprises an incident coupling grating, an incident light field carrying different orbital angular momentums can be split into plasmons in different directions, and the plasmons in different directions can be split into a vortex light field. The single detector resolution of the orbital angular momentum of the vortex beam is realized through the direction and propagation loss difference of plasmons. The detector is compatible with an existing semiconductor technology, the structure is simple, vortex light beams carrying high-order orbital angular momentum can be detected, and the rotation direction of a vortex light field can be detected.

The invention discloses a material with a silver coating for low-temperature brazing of brazing filler metal, and particularly relates to the field of brazing welding, which comprises the following steps: silver amalgam paste is prepared by oscillating and mixing silver powder and mercury according to the mass ratio of 1: 9-0.5: 9.5 in a manner and method for plating silver on the surface of base metal (metal, semiconductor, ceramic or glass); when brazing is carried out, the surface of the silver plating layer of the to-be-welded piece is coated with brazing filler metal, and then heating and pressurizing are carried out in a low-temperature interval of 120-350 DEG C in a vacuum, protective atmosphere or atmospheric environment to complete connection. According to the method, the amalgam reaction and isothermal solidification principles are utilized, a tough welding spot mainly comprising a silver-based solid solution is finally formed, generation of a large number of brittle intermetallic compounds is avoided, a connector has high strength, high reliability and excellent thermal fatigue resistance, and therefore the problems that gold-tin brazing filler metal is high in cost, the brittleness of the welding spot is large, and the welding temperature is high are successfully solved.

Described are light emitting diode (LED) arrays (100) comprising a plurality of mesas (101a, b) defining pixels having sidewalls, each of the mesas comprising semiconductor layers (108) having a total thickness (11), the semiconductor layers including an n-type layer (104n), an active region (106), and a p-type layer (104p). A plurality of junction spacers (118) comprise a dielectric material conformal to a portion of the sidewalls, and span a longitudinal distance of greater than or equal to 20% of the thickness (t1) of the semiconductor layers. A plurality of cathodes comprising an n-contact material (114) between each of the mesas provide optical isolation therebetween, and electrically contact an uninsulated portion (105) of the n-type layer of each of the mesas along the sidewalls, the uninsulated portion of the n-type layer comprising a doped N-type material (104n-d-1). A surface (120) of the doped N-type material of the uninsulated portion of the n-layer is effective to provide an active metal-semiconductor contact.

A metal-semiconductor contact structure and a preparation method thereof, a solar cell and a photovoltaic module are provided. The metal-semiconductor contact structure includes a metal electrode and a semiconductor layer in contact with each other. The metal electrode has a metal element, and the semiconductor layer has a semiconductor element and a doping element for doping the semiconductor layer. A contact interface between the metal electrode and the semiconductor layer has a hole and a conductive structure. The conductive structure includes a conductive eutectic adjacent to the semiconductor layer, and a conductive crystal extending from the conductive eutectic into the hole. The conductive eutectic includes a eutectic formed by the metal element and the semiconductor element, and the conductive crystal includes a crystal formed by crystallization of the metal element.

A metal-semiconductor contact structure, a solar cell and a photovoltaic module are provided. The metal-semiconductor contact structure includes: a doped semiconductor layer; a metal electrode in contact with the doped semiconductor layer; a first conductive region provided at a contact interface between the doped semiconductor layer and the metal electrode, and including: a first conductive structure including a plurality of first metal particles distributed in the first conductive region, at least part of the first conductive structure contacting the doped semiconductor layer; and a second conductive structure, wherein the second conductive structure is radial, at least part of the second conductive structure is located on a surface of the first metal particles, and the second conductive structure has a radial direction towards the metal electrode; wherein the metal electrode, the first metal particles, and the second conductive structure all have a same metal element.

A metal-semiconductor contact structure is provided. The metal-semiconductor contact structure includes a doped silicon-based semiconductor layer and a metal electrode in contact with each other. A contact region between the doped silicon-based semiconductor layer and the metal electrode includes a first conductive region and a second conductive region. In the first conductive region, the metal electrode is recessed towards an inner direction of the doped silicon-based semiconductor layer to form a pit island, a silicon-based eutectic in conductive connection with the doped silicon-based semiconductor layer is provided in the pit island, and a conductive crystal in conductive connection with the silicon-based eutectic is provided. A conductive aggregate including a glass phase material and metal conductive particles is provided in the second conductive region, and the metal conductive particles have a same kind of the metal element as the conductive crystal.

Embodiments of the present application relate to the field of semiconductor, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate comprising spaced-apart bit lines and semiconductor channels, the bit lines extending along a first direction, the semiconductor channels being located on part of top surfaces of the bit lines, and in a direction perpendicular to the top surfaces of the bit lines, the semiconductor channels comprising a first region, a second region and a third region arranged in sequence; a dielectric layer located between adjacent bit lines and on sidewalls of the semiconductor channels; a gate electrode surrounding the dielectric layer of the second region and extending along a second direction, the first direction being different from the second direction; a metal-semiconductor compound layer located on top surfaces of the semiconductor channels; a diffusion barrier layer at least surrounding sidewalls of the metal-semiconductor compound layer; and an insulating layer located between adjacent semiconductor channels on the same bit line and separating the gate electrode and the diffusion barrier layer located on adjacent dielectric layers. The embodiments of the present application can at least improve the electrical performance of the semiconductor structure.

This invention in one aspect relates to a method of synthesizing a self-assembled mixed-dimensional heterostructure including 2D metallic borophene and 1D semiconducting armchair-oriented graphene nanoribbons (aGNRs). The method includes depositing boron on a substrate to grow borophene thereon at a substrate temperature in an ultrahigh vacuum (UHV) chamber; sequentially depositing 4,4″-dibromo-p-terphenyl on the borophene grown substrate at room temperature in the UHV chamber to form a composite structure; and controlling multi-step on-surface coupling reactions of the composite structure to self-assemble a borophene / graphene nanoribbon mixed-dimensional heterostructure. The borophene / aGNR lateral heterointerfaces are structurally and electronically abrupt, thus demonstrating atomically well-defined metal-semiconductor heterojunctions.

The invention discloses a boron diffusion method, a preparation method of a solar cell and the solar cell. The boron diffusion method comprises the following steps: preparing an oxide layer on the surface of one side of a silicon substrate; boron source pre-deposition is carried out on the oxide layer; propelling the pre-deposited boron source, including performing a first propelling process in an oxygen-free atmosphere, and performing a second propelling process, a third propelling process and a fourth propelling process in an oxygen atmosphere; and cooling the pushed silicon substrate. According to the boron diffusion method, the preparation method of the solar cell and the solar cell, the inter-sheet and in-sheet uniformity of the square resistance on the surface of the cell can be improved, the contact loss of a metal semiconductor is reduced, the carrier recombination is reduced, and the cell efficiency is improved.

Disclosed is a simple and scalable method for preparing a netted heterostructure of a thermoelectric material at a nanoscale. The preparation method involves shaking the nanomaterial of component B and component A in molten form in an inert environment, followed by controlled consolidation. A cellular network of component B with voids filled with component A forms a heterostructure B / A at nanoscale, where component A and component B may be a metal, a semiconductor or an insulator. Also disclosed are methods of improving the thermoelectric figure of merit (ZT) through the quantum confinement effect and methods of inverting its polarity by injecting carriers from a barrier layer in a nano-sized heterostructure. It is shown that ZTgt; ZTgt, ZTgt, ZTgt, ZTgt, ZTgt, ZTgt ', ZTgt', ZTgt ', ZTgt', ZTgt ', ZTgt' 2. The method of ZT enhancement is also applicable to semiconductor-semiconductor heterostructures as well as superlattice structures. The high ZT materials may be used for power generation, Peltier cooling and refrigeration, thermal infrared sensing and imaging, and thermal infrared display.

The invention provides a preparation method of a boron-doped selective emitter, the emitter and a TOPCon battery, and relates to the technical field of TOPCon batteries. The preparation method comprises the following steps: depositing a borosilicate glass layer on the front surface of a textured silicon wafer through a PECVD (Plasma Enhanced Chemical Vapor Deposition) process; removing the borosilicate glass layer in a non-fine grid region on the front surface of the silicon wafer through a laser patterning process to obtain the silicon wafer of which the borosilicate glass layer in a fine grid region on the front surface of the silicon wafer is reserved; forming a shallow doped region in a non-fine grid region on the front surface of the silicon wafer through a boron diffusion process, and forming a primary heavily doped region on a borosilicate glass layer in a fine grid region on the front surface of the silicon wafer; and pushing the boron source in the primary heavily doped region into the silicon wafer through an SE process to form a secondary heavily doped region so as to obtain the boron-doped selective emitter. The preparation method can reduce the proportion of concentric circles generated by silicon wafer oxygen precipitation caused by a high-temperature process, further reduces the contact resistivity of the front metal semiconductor, and improves the efficiency of the cell.

The invention provides a method for improving metal-semiconductor contact based on a silane coupling agent and application. The method comprises the steps that a semiconductor device is provided, the semiconductor device comprises a metal-semiconductor contact structure, the metal-semiconductor contact structure is Schottky contact, and a semiconductor material, in contact with a metal material, contained in the metal-semiconductor contact structure comprises a two-dimensional semiconductor material with hydroxyl on the surface; the semiconductor device is in contact with a silane coupling agent solution, so that the silane coupling agent reacts with hydroxyl on the surface of the two-dimensional semiconductor material, a molecular passivation layer is formed on the surface of the two-dimensional semiconductor material, and Schottky contact is converted into ohmic contact. According to the method provided by the invention, the molecular passivation layer is constructed on the surface of the two-dimensional semiconductor material by adopting the silane coupling agent, so that a surface dangling bond and an interface state in the metal-semiconductor contact structure are effectively eliminated, the metal-semiconductor contact structure is converted from Schottky contact to ohmic contact, and the stability and the reliability of a semiconductor device are improved.

The invention discloses a metal-semiconductor direct current friction nanometer generator based on a depletion mode u-GaN / AlGaN / AlN / GaN high electron mobility transistor. The generator comprises a titanium (Ti) metal friction layer and a depletion mode GaN HEMT friction layer, and direct current is generated through the interface friction volt effect. The core of the invention lies in that high-concentration two-dimensional electron gas (2DEG) and surface state characteristics in the u-GaN / AlGaN / AlN / GaN heterojunction are utilized, and the friction volt effect is combined, so that efficient mechanical energy-electric energy conversion is realized. In the dynamic Schottky contact of the D-GaN HEMT and metal, unbalanced carriers in u-GaN Cap are excited by friction, electrons and holes are separated by a built-in electric field, surface state electrons of u-GaN Cap obtain friction energy to be transited to a conduction band, and a Schottky barrier is overcome to form current; in the sliding process, metal and a semiconductor interact to increase the surface state density, a large number of electrons are excited, chemical bonds are formed, two-dimensional electron gas is formed on an AlN / GaN interface and flows back under a reverse electric field, the electron concentration is maintained, current is continuously generated, and finally direct current is formed in an external circuit.

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a dielectric layer, an etching stop layer, a silicide layer, and a contact metal. The semiconductor substrate has a groove. The dielectric layer and the etching stop layer are disposed in the groove. The silicide layer is located within the semiconductor substrate. The dielectric layer has a via in the groove. The etching stop layer has a through hole under the via of the dielectric layer. The silicide layer is aligned with an inner sidewall of the through hole of the etching stop layer. The contact metal is disposed in the via.

In an embodiment, a method is described that includes forming a source / drain region having a first base material composition and a first concentration of a first conductivity type dopant; removing a portion of the source / drain region having the first base material composition and the first concentration of the first conductivity type dopant to expose a contact surface; and forming a contact layer on the contact surface. The contact layer comprises a second composition and has a second concentration of the first conductivity type dopant, wherein the second concentration is greater than the first concentration for the first conductivity type dopant. A metal is deposited on the contact layer, wherein an interface between the metal and the contact layer includes a metal semiconductor alloy.

The invention discloses a cold and hot dual-purpose cup which comprises a cup body, a cup cover and a semiconductor refrigeration system arranged in the cup body, the cup body comprises a shell, an inner container and a support, the bottom wall of the inner container or the whole inner container is made of metal, and the semiconductor refrigeration system comprises a semiconductor refrigeration piece, a refrigeration piece heat insulation plate, first cooling fins and a cooling fan; the support comprises an upper support body and a lower support body, the upper support body is fixed to the bottom of the inner container, and the upper support body and the lower support body are folded to form an installation cavity of the semiconductor refrigeration system. The shell is provided with a plurality of first heat dissipation holes corresponding to the first heat dissipation fan, and a bottom plate of the shell is provided with a second ventilation opening. The refrigerating system is installed and fixed through the upper support and the lower support, the supports are positioned, installed and fixed in the shell through the multiple installation columns, the structure is simple and reasonable, and the product cost is reduced.

The invention relates to a C-type contact structure of a two-dimensional device and a preparation method and application of the C-type contact structure. The C-type contact structure comprises a substrate (1), a gate electrode (2), a gate dielectric layer (3), a first-layer source-drain electrode (4), a two-dimensional semiconductor channel (5) and a second-layer source-drain electrode (6) which are sequentially arranged from bottom to top. And the second layer of source and drain electrode (6) and the first layer of source and drain electrode (4) are contacted and connected at the two sides of the two-dimensional semiconductor channel (5) to form C-type contact, and the two sides of the two-dimensional semiconductor channel (5) are wrapped between the second layer of source and drain electrode (6) and the first layer of source and drain electrode (4). Compared with the prior art, an upper layer of contact metal and a lower layer of contact metal (the first layer of source-drain electrode and the second layer of source-drain electrode) are designed on the contact between a channel (a two-dimensional semiconductor channel) and the source and the drain to form a C-type metal-semiconductor contact structure, so that the contact area of the two is effectively increased, and the contact resistance is reduced.

A method for preparing a MOF-based multiphase composite electromagnetic wave absorbing material is disclosed, which relates to the preparation method and application of electromagnetic wave absorbing materials. The purpose of this invention is to solve the problems of poor attenuation and narrow absorption bandwidth in ABO3-type perovskite electromagnetic wave absorbing materials prepared by existing methods. This invention is based on the metallic Fe in MIL-88A. 3+ Ions were successfully induced to form an oxide perovskite phase in MIL-88A via etching, resulting in a hierarchical hollow nanocomposite material. In this structure, the oxide perovskite, a typical spinel-type p-type semiconductor, is composited with the surrounding elemental Fe phase through an outer graphitized carbon shell. Utilizing the heterojunction effect with metal-semiconductor contacts, an excellent interfacial polarization process is generated, significantly enhancing the dielectric loss performance of the composite material. Simultaneously, by consuming excess Fe metal... 3+ Excellent electromagnetic wave absorption performance was obtained by adjusting the impedance matching of the composite material.

A semiconductor device may include a substrate insulating layer, a semiconductor pattern extending on the lower insulating pattern, a plurality of channel layers stacked on the semiconductor pattern, a gate structure surrounding the plurality of channel layers, a source / drain region on the semiconductor pattern and opposite sides of the gate structure, a backside contact structure including a contact region connected to the source / drain region, and an intermediate insulating pattern in contact with the semiconductor pattern. The backside contact structure may include a metal-semiconductor compound layer, a first insulating liner layer, a second insulating liner layer, and a conductive layer. The backside contact structure may pass through each of the substrate insulating layer, and the semiconductor pattern. The conductive layer may have a step portion between a first vertical region and a second vertical region of the backside contact structure.

The invention is applicable to the technical field of biosensors, and provides a preparation method of a nanoparticle array type SERS (Surface Enhanced Raman Scattering) substrate with an Au-CeO2 (at) 4MPBA Janus structure, which comprises the following steps: step 1, synthesizing nanoparticles with the Au-CeO2 (at) 4MPBA Janus structure; step 2, assembling a nanoparticle array SERS (Surface Enhanced Raman Scattering) substrate; and step 3, constructing a diagnosis and treatment integrated platform. According to the method, through a metal-semiconductor heterojunction structure, nanoparticles with relatively simple morphology have high-strength SERS hot spots. 4-MPBA multifunctional small molecules are modified on the surfaces of the nano particles, and the small molecules have the functions of regulating the particle spacing, providing Raman signals as signal molecules and capturing molecules of bacteria at the same time. The prepared SERS detection platform shows considerable enzymatic activity and photo-thermal performance, so that the SERS biosensor can be used for removing captured bacteria.

The invention belongs to the technical field of ferroelectric memristors, and particularly relates to a ferroelectric memristor capable of being regulated and controlled in multiple dimensions and a preparation method and application of the ferroelectric memristor. The ferroelectric memristor comprises a substrate, a gate electrode, a gate medium, a semiconductor layer, a source electrode, a drain electrode and a ferroelectric layer, dynamic adjustment of a metal-semiconductor interface potential barrier is realized by regulating and controlling polarization in a ferroelectric surface, so that the conductivity state of the device and the response of the device to an optical signal are controlled; the switching operation of the memristor and the conductivity of a semiconductor channel are realized by utilizing a gate voltage regulation and control mechanism, so that the high efficiency and accuracy of the device in executing a complex calculation task are ensured; by controlling the polarization degree and direction of the ferroelectric material, the multi-stage conductivity state and optical response are realized. The memristor can be used in the field of next-generation artificial intelligence, and is particularly excellent in performance when sensing, storage and calculation tasks are executed. In addition, the method shows excellent undercurrent control capability in large-scale integrated circuit design, which shows that the method has wide application potential in the fields of high-performance calculation and intelligent data processing.

The application discloses a preparation method and structure of a metal-semiconductor structure, and a top gate field effect tube, comprising the following steps: sequentially depositing a sacrificial layer and a second bearing layer on a first bearing layer, evaporating electrode metal on the second bearing layer by an electron beam to form a first metal layer, and etching the first metal layer and the second bearing layer by an ion beam to obtain a first structure; evaporating electrode metal on the first structure by an electron beam to form a second metal layer, etching the second metal layer by an ion beam to form an electrode on the sacrificial layer, spin-coating a support layer on the etched first structure to obtain a second structure; placing the second structure into a first dissolving solution to dissolve the sacrificial layer and obtain a third structure; and transferring the third structure to a substrate to dissolve the support layer and obtain a metal-semiconductor structure; and the application evaporates and etches the metal electrode on the sacrificial layer, avoids the direct contact between high-energy particles and the semiconductor, and solves the technical problem of poor contact performance between the metal electrode and the semiconductor.

The present disclosure provides for methods for designing and constructing metal / semiconductor heterostructures as catalysts for a wide range of applications such as oxygen activation. In a particular aspect, the present disclosure provides for the manipulation of atomic structures at M / TiO2 interface (e.g., Au / TiO2 interface) that significantly alters the interfacial electron distribution and prompts O2 activation. In an aspect, the present disclosure provides for a M / TiO2 composites (e.g., heterostructures) having a defect-free M / TiO2 interface and method of making the M / TiO2 composites having a defect-free M / TiO2 interface. The M can be Au, Ag, Cu, Al, Pt, Ni, or Pd, for example.

An embodiment of the present invention provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate; a bit line located on the substrate, the bit line material comprising a metal-semiconductor compound; a semiconductor channel comprising a first doped region, a channel region, and a second doped region arranged in sequence, the first doped region being in contact with the bit line; a first dielectric layer covering the sidewall surfaces of the first doped region, with a first spacer between first dielectric layers located on adjacent first doped region sidewalls on the same bit line; an insulating layer covering the sidewall surfaces of the channel region; a word line covering the sidewall surfaces of the insulating layer away from the channel region, with a second spacer between adjacent word lines; a second dielectric layer covering the sidewall surfaces of the second doped region, with a third spacer between second dielectric layers located on adjacent second doped region sidewalls; and a third dielectric layer located between the first spacer, the second spacer, and the third spacer. The embodiments of the present invention are advantageous for reducing the resistance of the bit line, thereby improving the electrical performance of the semiconductor structure.

Metal-semiconductor contact structure, comprising: a doped semiconductor layer (200); a metal electrode (300) in contact with the doped semiconductor layer; and a first conductive region (1a) provided at a contact interface between the doped semiconductor layer and the metal electrode, the first conductive region comprising: a first conductive structure (11), the first conductive structure comprising a plurality of first metal particles (111) distributed in the first conductive region, the first metal particles having a spherical shape and / or an ellipsoidal shape, at least a part of the first conductive structure being in contact with the doped semiconductor layer; a second conductive structure (12), wherein the second conductive structure is radial, at least a part of the second conductive structure is arranged on a surface of the first metal particles, and a radial direction of the second conductive structure is a direction towards the metal electrode, wherein the metal electrode, the first metal particles and the second conductive structure all comprise the same metal element.

The application discloses a power device and a preparation method thereof and electronic equipment, and relates to the technical field of electronic components. The power device comprises a semiconductor substrate and a two-dimensional metal material layer on the surface of the semiconductor substrate. In the application, the two-dimensional metal material layer is in contact with the semiconductor substrate to form an electrode contact. Since the two-dimensional layered metal material forming the two-dimensional metal material layer has an atomically flat surface without dangling bonds, the two-dimensional layered metal material can provide a uniform and low-wrinkle surface for the interface between the metal and the semiconductor substrate, which is beneficial to improving the contact quality, reducing the influence of the rough surface of the semiconductor substrate, improving the transport efficiency of the carriers, and further improving the performance of the semiconductor power device.

The invention discloses a SnS2-based multi-element core-shell heterojunction and a preparation method and application thereof, and belongs to the technical field of material science and gas sensors, the SnO2 / WO3 nanorod heterojunction with uniform morphology is obtained by adopting Sn atom doping and adjusting the stirring temperature and the reaction time. The SnS2 nanosheet is used as a template, the SnO2 / WO3 nanorod and CS (NH2) 2 are used as raw materials, and the SnS2-based multi-element core-shell heterojunction is obtained through a vulcanization reaction. The SnS2-based multi-element core-shell heterojunction prepared by the preparation method disclosed by the invention not only comprises a p-n junction formed by p-type WS2 and n-type SnS2, but also comprises a metal / semiconductor heterojunction formed by 1T-WS2 and n-type SnS2, and a crystalline phase heterojunction formed between the 1T-WS2 and 2H-WS2. The sensitivity of the NO2 gas sensor is effectively enhanced through the synergistic effect of the three heterojunctions.

In an embodiment, a device includes: a source / drain region adjacent a channel region; an inter-layer dielectric on the source / drain region; a source / drain contact extending through the inter-layer dielectric and into the source / drain region; a metal-semiconductor alloy region between the source / drain contact and the source / drain region, the metal-semiconductor alloy region disposed beneath a top surface of the channel region, the metal-semiconductor alloy region including a first dopant; and a contact spacer around the source / drain contact, the contact spacer including the first dopant and an amorphizing impurity.

The invention discloses a method for high-sensitivity detection of polystyrene plastic based on a metal semiconductor composite material, and belongs to the technical field of nano plastic detection. The detection method comprises the following steps: synthesizing bismuth selenide nanosheets, adding water to disperse, centrifuging, re-dispersing to obtain dispersion liquid, and adding chloroauric acid to react to obtain a metal semiconductor composite material; and mixing the solution to be detected, the dispersion liquid of the composite material and the aggregation agent to form a mixed solution to be detected, and collecting an enhanced Raman spectrum signal of the mixed solution to be detected through a Raman spectrometer to realize the detection of the nano plastic. The metal semiconductor composite material is prepared by reducing chloroauric acid through the bismuth selenide nanosheets, the preparation method is simple, and the composite material can better realize aggregation of nano-plastics and combination with Raman spectrum, and realizes enrichment and high-sensitivity detection of nano-plastic particles in a nano-plastic solution.

An electrical generator system including a radionuclide material; and a sandwich structure, the sandwich structure including: a layer of an n-type semiconductor material; a layer of intrinsic n-type semiconductor material; a layer of p-type semiconductor material; and metal electrodes, one of the electrodes being in direct contact with said n-type semiconductor material and another electrode being in contact with the p-type semiconductor material, forming metal-semiconductor junctions therebetween; wherein radiation emissions received from said radionuclide material are converted into electrical energy at said metal-semiconductor junctions; and electrical contacts connected to said electrodes which facilitate the flow of said electrical energy when connected to a load.