376 results about "In situ doping" patented technology

A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses via a selective epitaxial growth process. The epitaxial silicon is in-situ alloyed with substitutional carbon and in-situ doped with phosphorus. The silicon-carbon alloy generates a uniaxial tensile strain in the channel region between the source and drain, thereby increasing electron channel mobility and the transistor's drive current. The silicon-carbon alloy decreases external resistances by reducing contact resistance between source/drain and silicide regions and by reducing phosphorous diffusivity, thereby permitting closer placement of the transistor's source/drain and channel regions.

The invention relates to a novel preparing method for an in-situ nitrogen-doped porous carbon material, the application of the in-situ nitrogen-doped porous carbon material serving as a carrier of a load type catalyst, the load type catalyst comprising the in-situ nitrogen-doped porous carbon material, and the application of the load type catalyst in the water phase alcohol condensation reaction. Cheap micromolecule nitrogen substances serve as a nitrogen source of the in-situ nitrogen-doped porous carbon material, nitrogen atom in-situ doping is achieved in the carbon material preparing process, the doping content of the in-situ nitrogen-doped porous carbon material is controllable, the in-situ nitrogen-doped porous carbon material is distributed evenly, the dispersity of metal in the carrier and the combining strength with the carrier can be improved through doping of nitrogen atoms, and therefore the catalytic activity of the nitrogen-doped porous carbon material can be improved, and the service life of the nitrogen-doped porous carbon material can be prolonged.

Methods of forming field effect transistors include forming an insulated gate electrode on a non-SiGe semiconductor substrate and then selectively etching the semiconductor substrate to define source and drain region trenches on opposite sides of the insulated gate electrode. A step is performed to remove native oxide layers from sidewalls of the source and drain region trenches. The removal of the native oxide is followed by recessing the sidewalls of the source and drain region trenches by selectively wet etching the sidewalls of the source and drain region trenches. This step of wet etching the sidewalls of the source and drain region trenches may include exposing the sidewalls to a cleaning solution including ammonium hydroxide (NH₄OH). A step is then performed to epitaxially grow SiGe source and drain regions in the source and drain region trenches. This step of epitaxially growing SiGe source and drain regions may include epitaxially growing in-situ doped SiGe source and drain regions of first conductivity type in the source and drain region trenches.

Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.

A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

A composite-coated lithium iron phosphate in a three-dimensional nanonetwork layered structure and a preparation method therefor, and a lithium ion battery, wherein a composite is prepared by compounding a conducting polymer, graphene and a carbon nano tube. The preparation method for the coated lithium iron phosphate comprises the following steps: doping the composite and anhydrous ferric phosphate in situ in the process of preparing the anhydrous ferric phosphate, serving as a lithium iron phosphate precursor, then mixing the composite in-situ doped anhydrous ferric phosphate, a lithium source, a traditional carbon material and a solvent to obtain slurry, spray drying the slurry, and calcining to obtain the composite-coated lithium iron phosphate in a three-dimensional nanonetwork layered structure. The preparation method is simple and has a wide raw material source, low cost and very broad practical application prospect. Serving as an anode material of the lithium ion battery, the coated lithium iron phosphate has higher electrical conductivity and cycling stability, and more excellent comprehensive electrochemical performance.

A method for depositing an in situ doped epitaxial semiconductor layer comprises maintaining a pressure of greater than about 80 torr in a process chamber housing a patterned substrate. The method further comprises providing a flow of dichlorosilane to the process chamber. The method further comprises providing a flow of a dopant hydride to the process chamber. The method further comprises selectively depositing the epitaxial semiconductor layer on single crystal material on the patterned substrate at a rate of greater than about 3 nm min⁻¹.

The invention provides a preparation method and an application of a nitrogen and phosphorus co-doped porous carbon catalyst and belongs to the field of oxygen reduction catalysts for a fuel cell cathode. Nitrogen and phosphorus are introduced with an in-situ doping method, and the nitrogen and phosphorus doping amount is changed by adjusting the content of a nitrogen and phosphorus precursor. Besides, nitrogen and phosphorus co-doped porous carbon is prepared with a hard template method, and controllability of pore diameters of the porous carbon is realized by adjusting a hard template. The method comprises steps as follows: an earlier polymer of aniline monomers, a phosphorus precursor, a silica-based hard template and non-precious metal salt is prepared; the earlier polymer is calcined, and solids are obtained; the solids are etched, cleaned and dried, and the carbon material is obtained. More importantly, the prepared nitrogen and phosphorus co-doped porous carbon material has an excellent oxygen reduction electro-catalytic property under the acid condition and has huge application potential.

A first dielectric layer is formed over a PFET gate and an NFET gate, and lithographically patterned to expose a PFET area, while covering an NFET area. Exposed PFET active area is etched and refilled with a SiGe alloy, which applies a uniaxial compressive stress to a PFET channel. A second dielectric layer is formed over the PFET gate and the NFET gate, and lithographically patterned to expose the NFET area, while covering the PFET area. Exposed NFET active area is etched and refilled with a silicon-carbon alloy, which applies a uniaxial tensile stress to an NFET channel. Dopants may be introduced into the SiGe and silicon-carbon regions by in-situ doping or by ion implantation.

A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a gate structure, a source region and a drain region. The gate structure is disposed on a substrate. The source and drain regions disposed at respective sides of the gate structure include a boron-doped silicon germanium (SiGeB) layer substantially without stress relaxation. The boron-doped silicon germanium (SiGeB) layer has a germanium concentration greater than 30 at % and an in-situ doping concentration of boron ranging between 2.65×10²⁰/cm³ and 1×10²¹/cm³.

A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.

A method is disclosed to form a large-grain, lightly p-doped polysilicon film suitable for use as a channel region in thin film transistors. The film is preferably deposited lightly in situ doped with boron atoms by an LPCVD method at temperatures sufficiently low that the film is amorphous as deposited. After deposition, such a film contains an advantageous balance of boron, which promotes crystallization, and hydrogen, which retards crystallization. The film is then preferably crystallized by a low-temperature anneal at, for example, about 560 degrees for about twelve hours. Alternatively, crystallization may occur during an oxidation step performed, for example at about 825 degrees for about sixty seconds. The oxidation step forms a gate oxide for a thin film transistor device, for example a tunneling oxide for a SONOS memory thin film transistor device.

The invention relates to a vanadium doping type titanium base fume denitration catalytic material and a preparation method thereof. The material is characterized in that a surface active agent is used as a pore structure guiding agent, a water solution system sol-gel method is used for preparing the vanadium doping type titanium base catalytic material, and the doping content of active component vanadium is 0.5 to 20wt percent measured by V2O5. Because an in-situ doping loading mode is adopted in the sol-gel process, the preparation method is simple, and the production cost is low; in addition, the prepared denitration catalytic material has larger specific surface area, higher heat stability, higher denitration efficiency and wider active temperature window, and is suitable for the field of removal of coal-fired fume nitrogen oxide. The laboratory simulation fume evaluation shows that when the air speed is 10,000/h, and under the condition that the content of NO is 1000ppm, the removal rate of NO achieves more than 95 percent at the temperature of 180 to 420 DEG C.

A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process.

The process of the present invention provides for the manufacture of a novel proton conductive polymer gel useful as backfill for sacrificial and impressed current anode systems The process of the present invention is carried out in aqueous phase thus providing a cheaper option besides the use of ingredients readily available in the international markets. The polymer used as backfill is transformed into a proton conducting form in the gelated network through an in-situ doping process during gelation. The gel product produced can be sliced to sheet of any desired size suitable and compatible to concrete or soil medium. The novelty of the product of the present invention is that it can be used as backfill between any anode such as sacrificial or impressed current mode and is adaptable to the concrete surface both in the presence of moisture or absence of moisture, which is not hitherto been achieved in prior art. Further, the specialty of the utility of this product, is its compatibility with all the sacrificial anodes such Mg, Al, Zn which is not hitherto been realized with any of the earlier chemical backfill known for this application.

The invention discloses a non-carbon heteroatom-modified porous graphene framework and a preparation method thereof, and belongs to the technical field of novel material preparation. The framework is of a three-dimensional structure formed by assembling graphene slices, a supporting cavity with the size of 50-5000 nm is presented, and 80%-99% of non-carbon heteroatoms are modified on the edges of the graphene slices and holes. The non-carbon heteroatom-modified porous graphene framework is prepared by calcining a ternary solid mixture of a carbon source, a non-carbon heteroatom source and a catalytic graphitization template at high temperature, and in-situ doping is achieved. The framework enriches the varieties of carbon nanomaterials, supplies a hole structure and non-carbon heteroatom-modified graphene material which is controllable in adjustment and has the wide application prospect in the fields of electrochemical energy storage, heterogeneous catalysis, adsorptive separation and the like. Meanwhile, the efficient low-cost graphene preparation method is achieved, the technology is simple and safe, the raw materials are rich and cheap, research and industrialization of the graphene material are effectively promoted, and the high additional value of the cheap raw materials, production of graphene-related energy materials and development of energy industry are promoted.

The invention relates to an ultra-thin-body-silicon-on-insulator (UTB-SOI) tunneling field-effect transistor with an abrupt junction and a preparation method thereof. The preparation method comprises: selecting a UTB-SOI substrate; forming a shallow trench isolation unit; carrying out etching to form a P type/N type trench; carrying out silicon material deposition in the P type/N type trench and carrying out in-situ doping to form a P type/N type highly-doped source region; carrying out etching to form an N type/P type trench; carrying out silicon material deposition in the N type/P type trench and carrying out in-situ doping to form a low doped N type/P type drain region; forming a gate dielectric layer and a front gate layer on the top layer silicon surface of the substrate and carrying out etching to form a front gate; and carrying out lead window photoetching, metal deposition, and lead photoetching to form source region, drain region, and front gate metal leads. According to the invention, with the technique and preparation of trench etching and selective epitaxy deposition and filling at the source and drain regions, the tunnel junction area can be limited precisely; and on the basis of in-situ doping, the tunnel junction with the steep doping concentration gradient and the source and drain regions with uniform doping can be formed well and the driving current of the device can be effectively improved and the sub-threshold slope can be reduced.