35 results about "Channel pattern" patented technology

The invention provides an azimuth multichannel synthetic aperture radar two-dimensional time-varying error compensation method and device, which can be applied to the technical field of radars. The method comprises the following steps: estimating and compensating the attitude error of each channel according to the attitude information and velocity vector of the flight process of an aircraft carrying a synthetic aperture radar; doppler centers of sampling point echoes in different distance directions of each channel are calculated by adopting a vector method, channel pattern errors are estimated, and the pattern errors are compensated by utilizing an amplitude equalization method; performing two-dimensional Fourier transform on the echo of the channel after the attitude error and directional diagram error compensation is completed to obtain a two-dimensional frequency domain echo; performing two-dimensional frequency domain echo interference on the two-dimensional frequency domain echo, and estimating and compensating the distance time delay error of each channel; and performing two-dimensional frequency domain echo interference on the two-dimensional frequency domain echoes of the channels after distance time delay error compensation, and estimating and compensating the fixed phase error of each channel. Therefore, various actual errors of the channel are compensated, the image quality is improved, and the method is suitable for small-squint-angle signal reconstruction and imaging.

Disclosed is a three-dimensional semiconductor device comprising a substrate including first and second regions, a first active section on the first region and including a first lower channel pattern and a first lower source / drain pattern, a second active section on the first active section and including a first upper channel pattern and a first upper source / drain pattern, a third active section on the second region and including a second lower channel pattern and a second lower source / drain pattern, a fourth active section on the third active section and including a second upper channel pattern and a second upper source / drain pattern, and a gate electrode on the first and second lower channel patterns and the first and second upper channel patterns. A first width in a first direction of the first lower channel pattern is greater than a second width in the first direction of the second lower channel pattern.

A semiconductor memory device is provided that includes a bit line on a substrate, a protruded insulating pattern on the bit line, and in a channel trench, first and second channel patterns that extend along sidewalls of the channel trench, and spaced apart from the first channel pattern in the first direction, a channel interfacial layer that extends along the sidewalls of the channel trench, and is in contact with the first channel pattern and the second channel pattern, a first word line between the first channel pattern and the second channel pattern, a second word line between the first channel pattern and the second channel pattern, and is spaced apart from the first word line in the first direction and a first capacitor and a second capacitor, which are electrically connected to the first channel pattern and the second channel pattern.

Embodiments of the present disclosure relate to a memory device which has a dual channel thickness, and a method of forming the same. The memory device includes a source plate; a stack structure including a plurality of interlayer insulating layers and a plurality of electrode layers which are alternately stacked on the source plate in a vertical direction; a through hole passing through the stack structure; a charge storage structure disposed on a sidewall of the through hole; and a channel pattern disposed on the charge storage structure, and including a first channel pattern which is adjacent to the source plate and a second channel pattern which is disposed on the first channel pattern in the vertical direction and has a width different from a width of the first channel pattern. It is possible to prevent deterioration of device characteristics due to a defect in processing.

The present invention is applied to the technical field of river channel water depth inversion. Disclosed is a river channel water depth inversion method based on a water depth-water surface area mathematical model and remote sensing, comprising constructing a first water depth-water surface area mathematical model of a river channel; on the basis of the type of the river channel, calculating a relationship function among the discharge section area, the water depth and the flow path of the river channel, and a relationship function among the area of triangles on two sides, the water depth and the flow path of the river channel, and substituting the relationship functions into the first water depth-water surface area mathematical model to obtain a second water depth-water surface area mathematical model; on the basis of the relationship between a water level and the water depth, converting the second water depth-water surface area mathematical model into a water level-water surface area mathematical model, in view of a water level-water surface area relationship obtained by remote sensing, solving an unknown number in the mathematical model, and substituting the solved number into the second water depth-water surface area mathematical model to obtain a third water depth-water surface area mathematical model; and substituting a water surface area extracted by remote sensing into the third water depth-water surface area mathematical model to obtain the water depth of the river channel. The present invention improves the representativeness of a water depth value, and also overcomes the difficulty of using bands to invert the water depth of water having high sediment content.

A micro-channel membrane for use with high-temperature molten salts used with high-temperature reference electrodes (HTREs). The micro-channel membrane includes a ring having an opening with an opening surface and a plug positioned within the opening with a plug surface. The opening surface and the plug surface contact and interface with each other to form a plurality of micro-channels. The opening surface and the plug surface may be tapered. The opening surface and / or the plug surface may have a surface configuration to facilitate formation of the micro-channels, such as a plurality of facets, a helical channel, a roughened surface, a channel pattern, or a knurled surface pattern. One or more tack welds may secure the plug within the ring. A method for making the micro-channel membrane may include measuring a leak rate through the micro-channels and securing the plug when a target leak rate is measured.

A semiconductor memory device is provided that includes a bit line on a substrate, a protruded insulating pattern on the bit line, and in a channel trench, first and second channel patterns that extend along sidewalls of the channel trench, and spaced apart from the first channel pattern in the first direction, a channel interfacial layer that extends along the sidewalls of the channel trench, and is in contact with the first channel pattern and the second channel pattern, a first word line between the first channel pattern and the second channel pattern, a second word line between the first channel pattern and the second channel pattern, and is spaced apart from the first word line in the first direction and a first capacitor and a second capacitor, which are electrically connected to the first channel pattern and the second channel pattern.

The invention relates to the technical field of antenna channel calibration, in particular to a global calibration method and system for the multi-channel directional diagram distinction degree of a plate-shaped array antenna, and provides the following scheme: firstly, carrying out local calibration, extracting the directional diagram characteristics of each channel to construct a local objective function, and obtaining an initial compensation parameter through an optimization method; and if the global optimization stage condition is met, introducing a particle swarm algorithm, establishing an identification subspace based on distinction degree guide particles in the double-role particle structure, and applying graph avoidance drive to the controlled cooperative particles to realize global optimization calibration of the directional diagram. According to the invention, the discrimination degree of the directional diagram and the space structure regulation and control capability are improved.

The invention relates to the technical field of seismic signal processing, and relates to an offshore seismic data double-detection merging method based on multi-channel pattern matching, which comprises the following steps: inputting water detection data and land detection data; introducing an instrument correction factor to perform frequency matching on the land detection data to obtain corrected land detection data; obtaining a phase matching factor from the corrected land detection data in a Hilbert transform domain by using a phase matching factor characteristic equation, and applying the phase matching factor to the land detection data to obtain land detection data after phase correction; enveloping and smoothing the land detection data after phase correction to realize amplitude energy balance, and obtaining the land detection data after amplitude consistency correction; calculating multi-channel joint coefficients for the land detection data, and acting each joint coefficient on respective adjacent multi-channel data to obtain multi-channel joint land detection data; and carrying out pattern matching on the obtained multi-channel combined land detection data, and then combining the land detection data with the water detection data to obtain a double-detection combination result. According to the invention, an accurate water and land detection data merging result can be obtained.

A semiconductor memory device may include first and second bit lines spaced apart from each other, an interlayer insulating layer covering the first and second bit lines and including a groove extending to cross both of the first and second bit lines, a first channel pattern connected to the first bit line and in contact with an inner side surface of the groove and covering a top surface of the interlayer insulating layer, a second channel pattern connected to the second bit line and in contact with an opposite inner side surface of the groove and covering the top surface of the interlayer insulating layer, a word line in the groove, first and second electrodes on the interlayer insulating layer and in contact with the first and second channel patterns, respectively, and a dielectric layer between the first and second electrodes.

The invention discloses a droplet microfluidic in-situ test chip and method for microbial mineralization crystallization kinetic research, and relates to the technical field of rock and soil tests. In order to solve the problems that in the prior art, a single crystal crystallization process is difficult to visualize and nucleation sites of crystals are difficult to observe in situ and in real time, the following technical scheme is provided: the device comprises an upper layer channel pattern layer, solid polydimethylsiloxane and cover glass, an oil phase liquid injection port is formed in the top of the upper layer channel pattern layer, and is connected with an annular oil phase pipeline; a first water-phase liquid injection port and a second water-phase liquid injection port are formed in the middle of the area where the annular oil-phase liquid injection pipeline is located, a pipeline connecting the first water-phase liquid injection port and the second water-phase liquid injection port forms a reaction liquid mixing area at the communication position of the water-phase liquid injection pipeline, a liquid drop generation area is formed at the communication position of the oil-phase liquid injection pipeline and the water-phase liquid injection pipeline, and liquid drops form an in-liquid-drop solution mixing area in the snakelike circulation pipeline. And the liquid drops flow out through the liquid outlet. The method has the advantages of high flux, accurate reaction conditions, accurate observation and the like.

A semiconductor memory device may include first and second bit lines spaced apart from each other, an interlayer insulating layer covering the first and second bit lines and including a groove extending to cross both of the first and second bit lines, a first channel pattern connected to the first bit line and in contact with an inner side surface of the groove and covering a top surface of the interlayer insulating layer, a second channel pattern connected to the second bit line and in contact with an opposite inner side surface of the groove and covering the top surface of the interlayer insulating layer, a word line in the groove, first and second electrodes on the interlayer insulating layer and in contact with the first and second channel patterns, respectively, and a dielectric layer between the first and second electrodes.

A semiconductor device, comprising: a substrate; a plurality of bit lines located on the substrate, and disposed parallel to each other in a first horizontal direction; a plurality of word lines located on the bit line, and disposed parallel to each other in a second horizontal direction substantially perpendicular to the first horizontal direction; a plurality of channel patterns arranged in an array on the bit line, the plurality of channel patterns; a gate insulating pattern located between the plurality of channel patterns and the plurality of word lines; a plurality of switching insulating layers each formed on an upper surface of each of the plurality of channel patterns, at least a portion of which has a thickness that an electron can penetrate upon application of a voltage; and a plurality of control electrodes disposed parallel to each other to connect the plurality of switching insulating layers, is disclosed.

The application relates to the technical field of antenna channel calibration, in particular to a plate array antenna multi-channel directional diagram resolution global calibration method and system, and the application proposes the following scheme: firstly, local calibration is carried out, a local target function is constructed by extracting directional diagram characteristics of each channel, and initial compensation parameters are obtained through an optimization method; if a global optimization stage condition is met, a particle swarm algorithm is introduced, a recognition subspace is established based on resolution in a dual-role particle structure, and a pattern avoidance drive is applied to a controlled collaborative particle, so that global optimization calibration of the directional diagram is realized. The application improves the resolution and spatial structure regulation and control capability of the directional diagram.

A transistor includes: a substrate; a constant current formation layer provided on the substrate; a pair of source / drain patterns provided on the constant current formation layer; a gate electrode provided between the pair of source / drain patterns; a channel pattern extending in a direction between the pair of source / drain patterns; and a gate insulating layer surrounding the channel pattern, wherein the channel pattern penetrates the gate insulating layer and the gate electrode and is electrically connected to the source pattern and the drain pattern, the gate insulating layer separates the channel pattern and the gate electrode from each other, the constant current formation layer generates a constant current between the drain pattern and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

A semiconductor device with improved device performance and reliability includes a substrate, an active pattern including a plurality of channel patterns disposed on substrate and vertically spaced apart from each other, a gate electrode surrounding the plurality of channel patterns, a lower source / drain pattern disposed on the substrate, and disposed on one side of the plurality channel patterns, an upper source / drain pattern spaced upward from the lower source / drain pattern, and sidewall spacers including a first sidewall spacer in contact with a first side surface of the lower source / drain pattern and defining the first side surface, and a second sidewall spacer in contact with a second side surface of the lower source / drain pattern and defining the second side surface, in which the first side surface and the second side surface are opposing side surfaces of the lower source / drain pattern.

A semiconductor memory device includes a data storage pattern on a substrate, a buried contact on the data storage pattern, a bit-line spaced apart from the buried contact in a first direction perpendicular to an upper surface of the substrate and extending in a second direction parallel to the upper surface of the substrate, a channel pattern between the buried contact and the bit-line and connected to the buried contact and the bit-line, and a word-line on the channel pattern and extending in a third direction parallel to the upper surface of the substrate and intersecting the second direction. The channel pattern includes a first surface contacting the buried contact and a second surface contacting the bit-line. A width in the second direction of the first surface of the channel pattern is greater than a width in the second direction of the second surface of the channel pattern.

A semiconductor device and a method of manufacturing the semiconductor device includes a bit line extending in a first direction parallel to an upper surface of a substrate. And a first channel pattern connected to the bit line. The first channel pattern extends perpendicular to an upper surface of the substrate. A gate insulating pattern is disposed on the first channel pattern. The word line is disposed on the gate insulating pattern and extends in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction. The data storage patterns are spaced apart from each other in the first direction and the second direction. A contact pad is disposed on each of the data storage patterns. The second channel pattern is disposed on the bonding pad. The second channel pattern extends in the first direction from a first end of the first channel pattern.

Provided is a semiconductor device and method of manufacturing same, the method including: preparing a substrate including first and second regions; forming a first and second channel patterns in the first and second regions, wherein the first and second channel patterns each include a plurality of semiconductor patterns vertically stacked on the substrate, an inner region, and an outer region; forming a high-k dielectric layer covering the first channel pattern and the second channel pattern; forming a first protective mask on the high-k dielectric layer in the first region and the second region; removing the first protective mask from the first outer region and the second outer region; and forming an additional mask layer surrounding the first channel pattern and the second channel pattern, wherein the additional mask layer does not have etch selectivity with the first protective mask.

Three-dimensional (3D) semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and a pair of lower source / drain patterns that are on opposing side surfaces of the lower channel pattern respectively, a second active region stacked on the first active region, the second active region including an upper channel pattern and a pair of upper source / drain patterns that are on opposing side surfaces of the upper channel pattern, respectively, a dummy channel pattern between the lower and upper channel patterns, a pair of liner layers that are on opposing side surfaces of the dummy channel pattern, respectively, and a gate electrode on the lower, dummy, and upper channel patterns. The gate electrode may include a lower gate electrode on the lower channel pattern and an upper gate electrode on the upper channel pattern.

A semiconductor memory device includes: a channel pattern; a gate electrode layer configured to surround at least a portion of each of an upper surface and a lower surface of the channel pattern and extend in a first horizontal direction; a bit line structure connected to a first end of the channel pattern in a second horizontal direction orthogonal to the first horizontal direction and configured to extend in a vertical direction; a capacitor structure connected to a second end of the channel pattern in the second horizontal direction; a gate dielectric layer located between the channel pattern and the gate electrode layer and configured to cover the upper surface, the lower surface, and two side surfaces in the first horizontal direction of the channel pattern; and a bit line shield structure located on both sides of the bit line structure in the first horizontal direction and configured to extend in the vertical direction.

This disclosure provides a two-dimensional time-varying error compensation method and apparatus for azimuth multi-channel synthetic aperture radar, applicable to the field of radar technology. The method includes: estimating and compensating for the attitude error of each channel based on the attitude information and velocity vector of the aircraft carrying the synthetic aperture radar during flight; calculating the Doppler center of the echoes from different range sampling points of each channel using a vector method, estimating the channel pattern error, and compensating for the pattern error using an amplitude equalization method; performing a two-dimensional Fourier transform on the echoes of the channels after attitude and pattern error compensation to obtain two-dimensional frequency domain echoes; performing two-dimensional frequency domain echo interferometry on the two-dimensional frequency domain echoes to estimate and compensate for the range delay error of each channel; and performing two-dimensional frequency domain echo interferometry on the two-dimensional frequency domain echoes of the channels after range delay error compensation to estimate and compensate for the fixed phase error of each channel. This compensates for various actual errors in the channels, improves image quality, and is suitable for small oblique angle signal reconstruction and imaging.

There is provided a semiconductor memory device including: a molded insulating film extending in a first direction; a channel pattern protruding from the molded insulating film in a second direction; a gate insulating film covering at least a portion of the channel pattern and the molded insulating film; a word line on the gate insulating film; and a gate capping film covering at least a portion of the word line and the gate insulating film, in which the gate capping film includes: a first portion overlapping the word line in the second direction in a cross-sectional view cut in the first direction; and a second portion below the first portion and having a width greater than a width of the first portion based on the second direction, the gate insulating film having substantially the same first width and second width.

The invention discloses a DRAM (Dynamic Random Access Memory) element with a layout of a 3.5 F2 structure. The DRAM element comprises a substrate; a plurality of bit lines located on the substrate and arranged parallel to each other in a first horizontal direction at predetermined intervals; a plurality of word lines located on the bit lines and arranged parallel to each other at predetermined intervals in a second horizontal direction substantially perpendicular to the first horizontal direction; a plurality of channel patterns disposed on the bit lines in a honeycomb structure, each of the channel patterns extending in a vertical direction, each of the channel patterns including an upper electrode and a lower electrode, a region between the upper electrode and the lower electrode being a body region; and a gate insulating pattern between the plurality of channel patterns and the plurality of word lines, the plurality of word lines including first and second word lines arranged at different heights from each other, the first and second word lines being alternately arranged in a first horizontal direction, the plurality of channel patterns in contact with a single word line being arranged on the same straight line, and the first and second word lines being alternately arranged in a second horizontal direction. A plurality of channel patterns on a single bit line are arranged in a zigzag shape along both side edges of the single bit line.

The invention relates to a method for producing a base body (2) for a flat temperature control unit (1), comprising the steps: - Specifying an arrangement area (F) in a room (R), - Specifying a desired performance profile (L) via the arrangement area (F), - Creating a channel pattern (K) for laying a tubular body for conducting a thermal fluid over the measured arrangement area (F) based on the specified performance profile (L), - dividing the channel pattern (K) on the arrangement surface (F) into surface segments (S1, S2, S3, S4), - Creating and outputting control data for producing base body segments (G, G1, G2, G3) based on the surface segments (S1, S2, S3, S4), wherein a part of the channel pattern (K) assigned to a surface segment (S1, S2, S3, S4) is introduced as a number of guide channels (4) designed to guide the tubular body into the corresponding base body segment (G, G1, G2, G3). Furthermore, the invention comprises a temperature control unit, a control data and a system of base body segments.

Provided are a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a substrate, a plurality of word lines extending in a first direction on the substrate, a plurality of ferroelectric patterns respectively provided on the word lines, a blocking insulating film covering the ferroelectric patterns, a plurality of bit line pairs including a first bit line and a second bit line extending in a second direction crossing the word lines and the ferroelectric patterns on the blocking insulating film and intersecting the first direction, and a channel pattern provided between the first bit line and the second bit line of each of the bit line pairs on the blocking insulating film, wherein the channel pattern has an ambipolar conduction characteristic.

A semiconductor device according to an example embodiment of the present disclosure can include a lower channel pattern extending in a vertical direction, a lower gate electrode overlapping the lower channel pattern in a first horizontal direction, an upper channel pattern overlapping the lower channel pattern in the vertical direction, an upper gate electrode overlapping the upper channel pattern in the first horizontal direction, and a charge storage region extending in the vertical direction and contacting the upper channel pattern. The lower channel pattern can include a first source / drain region, a second source / drain region spaced apart from the first source / drain region in the vertical direction, and a channel region between the first source / drain region and the second source / drain region, and at least a portion of the charge storage region can overlap the lower channel pattern in a second horizontal direction intersecting the first horizontal direction.

A semiconductor device includes an active pattern including a plurality of channel patterns in a first region, a gate electrode surrounding the channel patterns, a doped bottom pattern including a first well having a first conductivity type and a second well region at the same level as the first well region and having a second conductivity type in a second region, a device isolation layer between the active pattern and the doped bottom pattern, a first doped region in the first well region having a dopant concentration of the first conductivity type larger than that within the first well region, and a second doped region in the second well region having a dopant concentration of the second conductivity type larger than that within the second well region, wherein the first doped region and the second doped region are positioned higher than a bottom surface of the device isolation layer.

A semiconductor device according to an example embodiment of the present disclosure may include: a lower channel pattern extending in a vertical direction; a lower gate electrode overlapping the lower channel pattern in a first horizontal direction; an upper channel pattern overlapping the lower channel pattern in the vertical direction; an upper gate electrode overlapping the upper channel pattern in the first horizontal direction; and a charge storage region extending in the vertical direction and contacting the upper channel pattern. The lower channel pattern may include a first source / drain region, a second source / drain region spaced apart from the first source / drain region in the vertical direction, and a channel region between the first source / drain region and the second source / drain region, and at least a portion of the charge storage region may overlap the lower channel pattern in a second horizontal direction, intersecting the first horizontal direction.