14 results about "Channel pattern" patented technology

A micro-channel membrane for use with high-temperature molten salts used with high-temperature reference electrodes (HTREs). The micro-channel membrane includes a ring having an opening with an opening surface and a plug positioned within the opening with a plug surface. The opening surface and the plug surface contact and interface with each other to form a plurality of micro-channels. The opening surface and the plug surface may be tapered. The opening surface and / or the plug surface may have a surface configuration to facilitate formation of the micro-channels, such as a plurality of facets, a helical channel, a roughened surface, a channel pattern, or a knurled surface pattern. One or more tack welds may secure the plug within the ring. A method for making the micro-channel membrane may include measuring a leak rate through the micro-channels and securing the plug when a target leak rate is measured.

The invention relates to the technical field of antenna channel calibration, in particular to a global calibration method and system for the multi-channel directional diagram distinction degree of a plate-shaped array antenna, and provides the following scheme: firstly, carrying out local calibration, extracting the directional diagram characteristics of each channel to construct a local objective function, and obtaining an initial compensation parameter through an optimization method; and if the global optimization stage condition is met, introducing a particle swarm algorithm, establishing an identification subspace based on distinction degree guide particles in the double-role particle structure, and applying graph avoidance drive to the controlled cooperative particles to realize global optimization calibration of the directional diagram. According to the invention, the discrimination degree of the directional diagram and the space structure regulation and control capability are improved.

The invention relates to the technical field of seismic signal processing, and relates to an offshore seismic data double-detection merging method based on multi-channel pattern matching, which comprises the following steps: inputting water detection data and land detection data; introducing an instrument correction factor to perform frequency matching on the land detection data to obtain corrected land detection data; obtaining a phase matching factor from the corrected land detection data in a Hilbert transform domain by using a phase matching factor characteristic equation, and applying the phase matching factor to the land detection data to obtain land detection data after phase correction; enveloping and smoothing the land detection data after phase correction to realize amplitude energy balance, and obtaining the land detection data after amplitude consistency correction; calculating multi-channel joint coefficients for the land detection data, and acting each joint coefficient on respective adjacent multi-channel data to obtain multi-channel joint land detection data; and carrying out pattern matching on the obtained multi-channel combined land detection data, and then combining the land detection data with the water detection data to obtain a double-detection combination result. According to the invention, an accurate water and land detection data merging result can be obtained.

A semiconductor memory device may include first and second bit lines spaced apart from each other, an interlayer insulating layer covering the first and second bit lines and including a groove extending to cross both of the first and second bit lines, a first channel pattern connected to the first bit line and in contact with an inner side surface of the groove and covering a top surface of the interlayer insulating layer, a second channel pattern connected to the second bit line and in contact with an opposite inner side surface of the groove and covering the top surface of the interlayer insulating layer, a word line in the groove, first and second electrodes on the interlayer insulating layer and in contact with the first and second channel patterns, respectively, and a dielectric layer between the first and second electrodes.

The application relates to the technical field of antenna channel calibration, in particular to a plate array antenna multi-channel directional diagram resolution global calibration method and system, and the application proposes the following scheme: firstly, local calibration is carried out, a local target function is constructed by extracting directional diagram characteristics of each channel, and initial compensation parameters are obtained through an optimization method; if a global optimization stage condition is met, a particle swarm algorithm is introduced, a recognition subspace is established based on resolution in a dual-role particle structure, and a pattern avoidance drive is applied to a controlled collaborative particle, so that global optimization calibration of the directional diagram is realized. The application improves the resolution and spatial structure regulation and control capability of the directional diagram.

A transistor includes: a substrate; a constant current formation layer provided on the substrate; a pair of source / drain patterns provided on the constant current formation layer; a gate electrode provided between the pair of source / drain patterns; a channel pattern extending in a direction between the pair of source / drain patterns; and a gate insulating layer surrounding the channel pattern, wherein the channel pattern penetrates the gate insulating layer and the gate electrode and is electrically connected to the source pattern and the drain pattern, the gate insulating layer separates the channel pattern and the gate electrode from each other, the constant current formation layer generates a constant current between the drain pattern and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Three-dimensional (3D) semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and a pair of lower source / drain patterns that are on opposing side surfaces of the lower channel pattern respectively, a second active region stacked on the first active region, the second active region including an upper channel pattern and a pair of upper source / drain patterns that are on opposing side surfaces of the upper channel pattern, respectively, a dummy channel pattern between the lower and upper channel patterns, a pair of liner layers that are on opposing side surfaces of the dummy channel pattern, respectively, and a gate electrode on the lower, dummy, and upper channel patterns. The gate electrode may include a lower gate electrode on the lower channel pattern and an upper gate electrode on the upper channel pattern.

A semiconductor memory device includes: a channel pattern; a gate electrode layer configured to surround at least a portion of each of an upper surface and a lower surface of the channel pattern and extend in a first horizontal direction; a bit line structure connected to a first end of the channel pattern in a second horizontal direction orthogonal to the first horizontal direction and configured to extend in a vertical direction; a capacitor structure connected to a second end of the channel pattern in the second horizontal direction; a gate dielectric layer located between the channel pattern and the gate electrode layer and configured to cover the upper surface, the lower surface, and two side surfaces in the first horizontal direction of the channel pattern; and a bit line shield structure located on both sides of the bit line structure in the first horizontal direction and configured to extend in the vertical direction.

Provided are a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a substrate, a plurality of word lines extending in a first direction on the substrate, a plurality of ferroelectric patterns respectively provided on the word lines, a blocking insulating film covering the ferroelectric patterns, a plurality of bit line pairs including a first bit line and a second bit line extending in a second direction crossing the word lines and the ferroelectric patterns on the blocking insulating film and intersecting the first direction, and a channel pattern provided between the first bit line and the second bit line of each of the bit line pairs on the blocking insulating film, wherein the channel pattern has an ambipolar conduction characteristic.

A semiconductor device according to an example embodiment of the present disclosure can include a lower channel pattern extending in a vertical direction, a lower gate electrode overlapping the lower channel pattern in a first horizontal direction, an upper channel pattern overlapping the lower channel pattern in the vertical direction, an upper gate electrode overlapping the upper channel pattern in the first horizontal direction, and a charge storage region extending in the vertical direction and contacting the upper channel pattern. The lower channel pattern can include a first source / drain region, a second source / drain region spaced apart from the first source / drain region in the vertical direction, and a channel region between the first source / drain region and the second source / drain region, and at least a portion of the charge storage region can overlap the lower channel pattern in a second horizontal direction intersecting the first horizontal direction.

A semiconductor device includes an active pattern including a plurality of channel patterns in a first region, a gate electrode surrounding the channel patterns, a doped bottom pattern including a first well having a first conductivity type and a second well region at the same level as the first well region and having a second conductivity type in a second region, a device isolation layer between the active pattern and the doped bottom pattern, a first doped region in the first well region having a dopant concentration of the first conductivity type larger than that within the first well region, and a second doped region in the second well region having a dopant concentration of the second conductivity type larger than that within the second well region, wherein the first doped region and the second doped region are positioned higher than a bottom surface of the device isolation layer.

A semiconductor device according to an example embodiment of the present disclosure may include: a lower channel pattern extending in a vertical direction; a lower gate electrode overlapping the lower channel pattern in a first horizontal direction; an upper channel pattern overlapping the lower channel pattern in the vertical direction; an upper gate electrode overlapping the upper channel pattern in the first horizontal direction; and a charge storage region extending in the vertical direction and contacting the upper channel pattern. The lower channel pattern may include a first source / drain region, a second source / drain region spaced apart from the first source / drain region in the vertical direction, and a channel region between the first source / drain region and the second source / drain region, and at least a portion of the charge storage region may overlap the lower channel pattern in a second horizontal direction, intersecting the first horizontal direction.

A semiconductor memory device may include a contact pattern including a first surface and a second surface opposite to each other in a first direction, a data storage pattern electrically connected to the first surface of the contact pattern, a channel pattern including a first surface and a second surface opposite to each other in the first direction, and a first sidewall and a second sidewall opposite to each other in a second direction, wherein the first surface of the channel pattern is electrically connected to the contact pattern, and at least a portion of the first sidewall of the channel pattern is in contact with the contact pattern, a bitline on the channel pattern, electrically connected to the second surface of the channel pattern, and extending in the second direction, and a wordline on the second sidewall of the channel pattern and extending in a third direction.