1624 results about "Lattice constant" patented technology

A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.

Low-bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of InAsP positioned somewhere between the InP substrate (26) and the LMM subcell(s) (22, 24). These devices are monofacial (10) or bifacial (80) and include monolithic, integrated, modules (MIMs) (190) with a plurality of voltage-matched subcell circuits (262, 264, 266, 270, 272) as well as other variations and embodiments.

A method of manufacturing a semiconductor device includes: the first step of forming a gate electrode over a silicon substrate, with a gate insulating film; and the second step of digging down a surface layer of the silicon substrate by etching conducted with the gate electrode as a mask. The method of manufacturing the semiconductor device further includes the third step of epitaxially growing, on the surface of the dug-down portion of the silicon substrate, a mixed crystal layer including silicon and atoms different in lattice constant from silicon so that the mixed crystal layer contains an impurity with such a concentration gradient that the impurity concentration increases along the direction from the silicon substrate side toward the surface of the mixed crystal layer.

The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed. The method may further comprises growing a fourth semiconductor layer having the second lattice constant on the second semiconductor layer, wherein the fourth semiconductor layer is relaxed, and growing a strained fifth semiconductor layer having the first semiconductor lattice constant on the fourth semiconductor layer. The method controls the surface roughness of the semiconductor layers. The method also has the unexpected benefit of reducing dislocations in the semiconductor layers.

A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.

The nitride-based semiconductor device includes a carrier traveling layer 1 composed of non-doped Al_xGa_1-xN (0≦X<1); a barrier layer 2 formed on the carrier traveling layer 1 and composed of non-doped or n-type Al_YGa_1-YN (0<Y≦1, X<Y) having a lattice constant smaller than that of the carrier traveling layer 1; a threshold voltage control layer 3 formed on the barrier layer 2 and composed of a non-doped semiconductor having a lattice constant equal to that of the carrier traveling layer 1; and a carrier inducing layer 4 formed on the threshold voltage control layer 3 and composed of a non-doped or n-type semiconductor having a lattice constant smaller than that of the carrier traveling layer 1. The nitride-based semiconductor device further includes a gate electrode 5 formed in a recess structure, a source electrode 6 and a drain electrode 7.

A method and system for providing a hard bias structure include providing a seed layer for a hard bias structure. The seed layer has a lattice constant and a natural growth texture. The method and system further include depositing the hard bias layer for the hard bias structure on the seed layer. The natural growth texture of the seed layer corresponds to a texture for the hard bias layer. The hard bias layer has a bulk lattice constant. Providing the seed layer includes forming a first plasma of a first deposition gas configured to expand the seed layer lattice constant if the bulk lattice constant is greater than the seed layer constant. Depositing the hard bias layer further includes forming a second plasma of a second deposition gas configured to expand the bulk lattice constant if the seed layer lattice constant is greater than the bulk lattice constant.

A method of manufacturing a solar cell by providing a first semiconductor substrate for the epitaxial growth of semiconductor material; forming a first subcell on the substrate with a first semiconductor material with a first band gap and a first lattice constant; forming a second subcell with a second semiconductor material with a second band gap and a second lattice constant, wherein the second band gap is less than the first band gap and the second lattice constant is greater than the first lattice constant; the second subcell including a strain balanced quantum well structure; and forming a lattice constant transition material positioned between the first subcell and the second subcell, the lattice constant transition material having a lattice constant that changes gradually from the first lattice constant to the second lattice constant.

A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

A multijunction, monolithic, photovoltaic (PV) cell and device (600) is provided for converting radiant energy to photocurrent and photovoltage with improved efficiency. The PV cell includes an array of subcells (602), i.e., active p/n junctions, grown on a compliant substrate, where the compliant substrate accommodates greater flexibility in matching lattice constants to adjacent semiconductor material. The lattice matched semiconductor materials are selected with appropriate band-gaps to efficiently create photovoltage from a larger portion of the solar spectrum. Subcell strings (601, 603) from multiple PV cells are voltage matched to provide high output PV devices. A light emitting cell and device is also provided having monolithically grown red-yellow and green emission subcells and a mechanically stacked blue emission subcell.

A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induce tensile strain within the layer.

A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.

A ferromagnetic tunnel junction structure comprising a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer that is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the tunnel barrier layer includes a crystalline non-magnetic material having constituent elements that are similar to those of an crystalline oxide that has spinel structure as a stable phase structure; the non-magnetic material has a cubic structure having a symmetry of space group Fm-3m or F-43m in which atomic arrangement in the spinel structure is disordered; and an effective lattice constant of the cubic structure is substantially half of the lattice constant of the oxide of the spinel structure.

The present invention provides a high quality thin film comparable to a bulk single crystal and providres a semiconductor device with superior characteristics. A channel layer 11, for example, is formed of a semiconductor such as zinc oxide ZnO or the like. A source 12, a drain 13, a gate 14 and a gate insulating layer 15 are formed on the channel layer 111 to form an FET. For a substrate 16, a proper material is selected depending on a thin film material of the channel layer 11 in consideration of compatibility of both lattice constants. For example, if ZnO is used for the semiconductor of the channel layer as a base material, ScAlMgO₄ or the like can be used for the substrate 16.

The invention relates to a method for modifying a USY (Ultra-Stable Y) molecular sieve. The method is characterized in that organic acid and an inorganic salt dealuminizing reagent are simultaneously added in a modifying process for organic acid-inorganic salt combined modification, and optimum process conditions, namely optimum concentration, volume ratio, reaction time, reaction temperature and the like, of an organic acid and an inorganic salt solution are determined by virtue of an orthogonal test. Compared with an industrial USY molecular sieve, the USY molecular sieve obtained by adopting the method disclosed by the invention is obviously increased in secondary pore content, can be kept at higher crystallinity and is enhanced in silica-alumina ratio, reduced in lattice constant and suitable for high-medium oil type hydrocracking catalyst carriers.

A dislocation-free high quality template with relaxed lattice constant, fabricated by spatially restricting misfit dislocation(s) around heterointerfaces. This can be used as a template layer for high In composition devices. Specifically, the present invention prepares high quality InGaN templates (In composition is around 5-10%), and can grow much higher In-composition InGaN quantum wells (QWs) (or multi quantum wells (MQWs)) on these templates than would otherwise be possible.

A plurality of III-nitride semiconductor structures, each comprising a light emitting layer disposed between an n-type region and a p-type region, are grown on a composite substrate. The composite substrate includes a plurality of islands of III-nitride material connected to a host by a bonding layer. The plurality of III-nitride semiconductor structures are grown on the III-nitride islands. The composite substrate may be formed such that each island of III-nitride material is at least partially relaxed. As a result, the light emitting layer of each semiconductor structure has an a-lattice constant greater than 3.19 angstroms.

A nitride-based semiconductor device includes a diode provided on a semiconductor substrate. The diode contains a first nitride-based semiconductor layer made of non-doped Al_XGa_1-XN (0≦X<1); a second nitride-based semiconductor layer made of non-doped or n-type Al_YGa_1-YN (0≦Y≦1, X<Y) having a lattice constant smaller than that of the first nitride-based semiconductor layer; a first electrode formed on the second nitride-based semiconductor layer; a second electrode formed on the second nitride-based semiconductor layer; and an insulating film that covers the second nitride-based semiconductor layer below a peripheral portion of the first electrode. In the diode, a recess structure portion is formed at a position near the peripheral portion of the first electrode on the second nitride-based semiconductor layer, and the first electrode covers the second nitride-based semiconductor layer and at least a part of the insulating film.