The embodiment of the invention provides a
transistor and a preparation method thereof, a
memory array, a memory and
electronic equipment, relates to the technical field of semiconductors, and aims to ensure the
gate control capability of the
transistor while reducing the parasitic resistance of the
transistor. The transistor comprises a substrate, a first
electrode, a first insulating layer, a grid
electrode, a second insulating layer, a grid
dielectric layer, an
auxiliary electrode, a channel structure and a second
electrode. The
auxiliary electrode is located on one side of the first electrode away from the substrate. The
auxiliary electrode includes a first sub-portion and a second sub-portion. The second sub-part is located on the side, away from the substrate, of the first sub-part. The first sub-part is located between the
gate dielectric layer and the first electrode, and the distance from the surface, away from the substrate, of the second sub-part to the substrate is larger than the distance from the surface, close to the substrate, of the first insulating layer to the substrate. The material of the auxiliary electrode includes a
crystalline oxide semiconductor or a
crystalline oxide conductor. The transistor is applied to the
electronic equipment to improve the performance of the
electronic equipment.