1058results about How to "Reduce defect density" patented technology

The invention concerns a method for producing a gallium nitride (GaN) epitaxial layer characterised in that it consists in depositing on a substrate a dielectric layer acting as a mask and depositing on the masked gallium nitride, by epitaxial deposit, so as to induce the deposit of gallium nitride patterns and the anisotropic lateral growth of said patterns, the lateral growth being pursued until the different patterns coalesce. The deposit of the gallium nitride patterns can be carried out ex-situ by dielectric etching or in-situ by treating the substrate for coating it with a dielectric film whereof the thickness is of the order of one angstrom. The invention also concerns the gallium nitride layers obtained by said method.

A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.

A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.

A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a Si substrate is formed on the Si substrate on the upper portion of which are formed a plurality of pairs of facets being mirror-symmetrical to the surface orientation of a semiconductor substrate, further on the top of the layer a SiC layer is sequentially formed.

To provide a semiconductor substrate of a group III nitride with low defect density and little warp, this invention provides a process comprising such steps of: forming a GaN layer 2 on a sapphire substrate 1 of the C face ((0001) face); forming a titanium film 3 thereon; heat-treating the substrate in an atmosphere containing hydrogen gas or a gas of a compound containing hydrogen to form voids in the GaN layer 2; and thereafter forming a GaN layer 4 on the GaN layer 2'.

A lateral growth method for defect reduction of semipolar nitride films. The process steps include selecting a semipolar nitride plane and composition, selecting a suitable substrate for growth of the semipolar nitride plane and composition, and applying a selective growth process in which the semipolar nitride nucleates on some areas of the substrate at the exclusion of other areas of the substrate, wherein the selective growth process includes lateral growth of nitride material by a lateral epitaxial overgrowth (LEO), sidewall lateral epitaxial overgrowth (SLEO), cantilever epitaxy or nanomasking.

Methods, and structures formed thereby, are disclosed for forming laterally grown structures with nanoscale dimensions from nanoscale arrays which can be patterned from nanoscale lithography. The structures and methods disclosed herein have applications with electronic, photonic, molecular electronic, spintronic, microfluidic or nano-mechanical (NEMS) technologies. The spacing between laterally grown structures can be a nanoscale measurement, for example with a spacing distance which can be approximately 1-50 nm, and more particularly can be from approximately 3-5 nm. This spacing is appropriate for integration of molecular electronic devices. The pitch between posts can be less than the average distance characteristic between dislocation defects for example in GaN (ρ=10¹⁰/cm²→d=0.1 μm) resulting an overall reduction in defect density. Large-scale integration of nanoscale devices can be achieved using lithographic equipment that is orders of magnitude less expensive that that used for advanced lithographic techniques, such as electron beam lithography.

A method of forming a high-quality relaxed SiGe alloy layer on a bulk Si-containing substrate is provided. The method of the present invention includes growing a strained SiGe alloy layer on a Si-containing substrate that has a porous Si-containing layer at or near the surface of the Si-containing substrate. The porous layer is formed by an electrolytic anodization process. The pores create free volume below the strained SiGe layer which can serve to accommodate strain relaxation during SiGe deposition or a subsequent heating step. The subsequent heating step is optional and is performed to further increase the relaxation of the SiGe alloy layer. The buried porous structure allows for a unique relaxation mechanism compared to prior art methods.

This invention pertains to e lectronic/optoelectronic devices with reduced extended defects and to a method for making it. The method includes the steps of depositing a dielectric thin film mask material on a semiconductor substrate surface; patterning the mask material to form openings therein extending to the substrate surface; growing active material in the openings; removing the mask material to form the device with reduced extended defect density; and depositing electrical contacts on the device.

There is provided a group III nitride crystal growth method capable of obtaining a material which is a GaN substrate of low defect density capable of being used as a power semiconductor substrate and in which characteristics of n-type and p-type requested for formation of transistor or the like. A growth method of group III nitride crystals includes: forming a mixed melt containing at least group III element and a flux formed of at least one selected from the group consisting of-alkaline metal and alkaline earth metal, in a reaction vessel; and growing group III nitride crystals from the mixed melt and a substance containing at least nitrogen, wherein after immersing a plurality of seed crystal substrates placed in an upper part of the reaction vessel in which the mixed melt is formed, into the mixed melt to cause crystal growth, the plurality of seed crystal substrates are pulled up above the mixed melt.

A dry cleaning method for use in semiconductor fabrication, including the following steps. An etched metallization structure is provided and placed in a processing chamber. The etched metallization structure is cleaned by introducing a fluorine containing gas/oxygen containing gas mixture into the processing chamber proximate the etched metallization structure without the use of a downstream microwave while applying a magnetic field proximate the etched metallization structure and maintaining a pressure of less than about 50 millitorr within the processing chamber for a predetermined time.

A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nanocolumns compliant layer with an HVPE growth process is provided. The method uses a combination of dry and wet etching to create nanocolumns consisting of layers of non-polar III nitride material and other insulating materials or materials used to grow the non-polar III-V nitride materials.

Described is a method for making silicon on sapphire structures, and devices therefrom. The inventive method of forming integrated circuits on a sapphire substrate comprises the steps of providing a device layer on an oxide layer of a temporary substrate; bonding the device layer to a handling substrate; removing the temporary substrate to provide a structure containing the device layer between the oxide layer and the handling substrate; bonding a sapphire substrate to the oxide layer; removing the handling substrate from the structure; and annealing the final structure to provide a substrate comprising the oxide layer between the device layer and the sapphire substrate. The sapphire substrate may comprise bulk sapphire or may be a conventional substrate material with an uppermost sapphire layer.

A method of producing a layered semiconductor device comprises the steps of: (a) providing a base comprising a plurality of semiconductor nano-structures, (b) growing a semiconductor material onto the nano-structures using an epitaxial 5 growth process, and (c) growing a layer of the semiconductor material using an epitaxial growth process.

This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials.

The invention discloses a high-conductivity graphene/copper-based layered composite material and a preparation method thereof. The composite material is characterized in that the composite material is of a layered structure formed by alternate combination of chemical vapor deposition (CVD) graphene and a copper substrate, the copper substrate is in a single-crystal state in the thickness direction in layers, and the (111) crystal face high-orientation effect is achieved. The method includes the following steps that (1) graphene is grown on the upper surface and the lower surface of the platy copper substrate through a CVD technology and the copper substrate is induced to achieve preferred orientation along a (111) crystal face, and the sandwich-shaped graphene-cladding copper substrate is obtained through preparation; and (2) multiple pieces of graphene-cladding copper substrates are subjected to hot pressed sintering densification to form the high-conductivity graphene/copper-based layered composite material. The layered composite material prepared by the method is high in conductivity, higher than pure silver in conduction level and easy to produce and can be used as various conduction materials.

Semiconductor light emitting device and methods for its manufacture comprises a plurality of textured district defined on the surface of the substrate. The initial inclined layer deposition serves to guide the extended defects to designated gettering centers in the trench region where the defects combine with each other. As a result, the defect density in the upper section of the structure is much reduced. By incorporating a blocking mask in the structure, the free propagation of extended defects into the active layer is further restricted. The present invention is useful in the fabrication of semiconductor light emitting devices in misfit systems.

The invention relates to a method for manufacturing of a mask blank for extreme ultraviolet (EUV) photolithography, comprising the steps of: providing a substrate having a front surface and a back surface; depositing a film comprising tantalum nitride (TaN) on said front surface of said substrate for absorbing EUV light used during a photolithographic process; and depositing a conductive coating on said back surface of said substrate. Preferably, ion beam sputtering is used for depositing the film comprising tantalum nitride (TaN) and/or the conductive coating on the back surface of the substrate. Preferably, Xenon is used as a sputter gas for ion beam sputtering. Another aspect of the present invention relates to a mask blank for extreme ultraviolet (EUV) photolithography.

A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nano-pores and nano-network compliant layer with an HVPE, MOCVD, and integrated HVPE/MOCVD growth process in a manner that minimum growth will occur in the nano-pores is provided. The method produces nano-networks made of the non-polar III-V nitride material and the substrate used to grow it where the network is continuous along the surface of the template, and where the nano-pores can be of any shape.

A strained Si-SOI substrate is produced by a method comprising: growing a SiGe mixed crystal layer on an SOI substrate having a Si layer of not less than 5 nm in thickness and a buried oxide layer; forming a protective film on the SiGe mixed crystal layer; implanting light element ions into a vicinity of an interface between the silicon layer and the buried oxide layer; a first heat treatment for heat treating the substrate at a temperature of 400 to 1000° C. in an inert gas atmosphere; a second heat treatment for heat treating the substrate at a temperature not lower than 1050° C. in an oxidizing atmosphere containing chlorine; removing an oxide film from the surface of the substrate, and forming a strained silicon layer on the surface of the substrate.