24 results about "Threading dislocations" patented technology

The invention relates to the technical field of oil pipe connection, in particular to an air-tight seal oil pipe connecting structure which comprises a coupling and an oil pipe body suitable for being connected to the axial end of the coupling, the axial end of the coupling is provided with a conical thread groove, and the peripheral wall of the axial end of the oil pipe body is provided with a conical external thread. A conical external thread of the oil pipe body is in threaded connection with a conical thread groove in the corresponding axial end of the coupling, the oil pipe further comprises a connecting device, the connecting device comprises two clamping jaws which are driven to move in the opposite direction to clamp the coupling or move in the opposite direction to loosen the coupling, and supporting blocks are fixedly arranged on the outer walls of the two clamping jaws. The two supporting blocks are the first supporting block and the second supporting block respectively. According to the air-tight seal oil pipe, thread centering is carried out on the butt joint hoop and the oil pipe body, the connecting precision is improved, the connecting stability and reliability are enhanced, the looseness caused by thread dislocation and even the leakage risk caused by thread damage are reduced, and the connecting effect of the air-tight seal oil pipe is improved.

The invention discloses an epitaxial layer of a gallium nitride HEMT (High Electron Mobility Transistor) device on a substrate and a manufacturing method, and the epitaxial layer comprises the substrate, and a SiO2 discontinuous layer, an AlN nucleating layer, an AlGaN layer, a buffer layer, a high-carbon GaN layer, a low-carbon GaN channel layer, an AlGaN barrier layer and a cap layer which are sequentially stacked on the surface of the substrate along the longitudinal direction, random irregular similar triangles are distributed on the surface of the SiO2 discontinuous layer, so that part of the substrate can be exposed out of the surface of the SiO2 discontinuous layer. According to the epitaxial structure, the substrate is discontinuously covered by the random irregular SiO2 thin layer which is similar to a triangle, the HEMT structure is grown on the substrate, so that the density of GaN penetrating dislocation in the high-carbon GaN layer and the low-carbon GaN channel layer is reduced, and the performance and the reliability of an HEMT power device prepared by using the epitaxial structure with the low dislocation density are improved.

The invention provides a method for identifying penetration dislocation in silicon carbide, which comprises the following steps of: preliminarily corroding a silicon carbide sample to be identified, selecting a proper diffraction vector, and calculating relevant parameters containing an incidence angle # imgabs0 # corresponding to X-ray morphology detection under the selected diffraction vector by utilizing a Bragg diffraction principle; carrying out TSD and TED corrosion pit observation on the silicon carbide sample subjected to preliminary corrosion, recording an included angle # imgabs1 # between a connecting line between the highest point and the lowest point of the selected corrosion pit and the horizontal plane, obtaining an average value # imgabs2 # of the included angles of the selected corrosion pit, multiplying the average value # imgabs3 # of the included angles by a selected fixed coefficient # imgabs4 # to obtain a coefficient included angle # imgabs5 #, and carrying out TSD and TED corrosion pit observation on the coefficient included angle # imgabs5 #; the coefficient included angle # imgabs6 # is compared with the incidence angle # imgabs7 # of the diffraction vector, if # imgabs8 # is larger than # imgabs9 #, X-ray morphology detection is directly carried out, and otherwise, corrosion is carried out again; and carrying out identification by using an image detected by the X-ray morphology. According to the method, positioning and statistics of different kinds of dislocations in silicon carbide can be effectively realized.

The present invention relates to a method of producing an epitaxial wafer, the method comprising the steps of: forming a first layer on a growth substrate wafer; depositing a material layer on the first layer; and patterning the material layer to form a plurality of protrusions spaced apart from each other at predetermined intervals. According to the present invention, crystalline defects are hardly generated in regions having protrusions, and crystalline defects such as threading dislocations and the like are only generated on surfaces between the protrusions in conjunction with the growth of materials such as GaN, AlGaN, AlN, etc. Therefore, the crystallinity of epitaxial growth on a GaN-on-Si epitaxial wafer can be greatly improved. Accordingly, the performance and reliability of a HEMT power device and an LED optical device can be improved.

The present application discloses an LED epitaxial structure for improving luminous efficiency and a manufacturing method thereof. The LED epitaxial structure includes: a substrate, and a buffer layer, an N-GaN layer, a multi-quantum well structure, and a P-GaN layer sequentially grown on one surface of the substrate; wherein, the multi-quantum well structure is formed by alternating multiple quantum barriers and quantum wells. The quantum well includes an InN layer, an InGaN layer, a GaN layer, and an AlInGaN layer sequentially grown on the quantum barrier. The GaN layer and the AlInGaN layer constitute a Cap layer. Between the N-GaN layer and the P-GaN layer, the Cap layer adopts a growth mode with a gradual change of Al / In, which can play a role in polarization matching, form a high conduction band barrier, and reduce electron leakage. And in the initial stage of the growth of the quantum well, a growth mode of pre-passing In is adopted to form InN clusters, increase the incorporation of In, thereby reducing threading dislocations and increasing radiative recombination luminescence.

This silicon carbide substrate has a main surface. The polytype of the silicon carbide substrate is 4H. The main surface is the {0001} face or a surface inclined with respect to the {0001} face at an off angle of 1° or less. The main surface is composed of an outer edge, an outer peripheral region extending up to 5 mm from the outer edge, and a central region surrounded by the outer peripheral region. The average value of the electrical resistivity in the central region is 1×1010 Ωcm or higher. When the surface density of threading dislocations in square regions with a side length of 1 mm located at intervals of 5 mm in the central region is measured, the value obtained by dividing the number of square regions in which the surface density of threading dislocations is 5000 cm-2 or higher by the total number of square regions is 30% or less.

To provide a technique for further reducing a dislocation density in a crystal substrate composed of a group III nitride.SOLUTION: A crystal substrate is a substrate composed of a group III nitride single crystal, a low-index crystal plane most proximate to a principal surface of the substrate is a c-plane, a threading dislocation included in the single crystal and penetrating the c-plane extends in a thickness direction without bending in a direction orthogonal to the thickness direction of the substrate, and a ratio of edge dislocations in the threading dislocations is less than 60%.SELECTED DRAWING: Figure 12

A method and an apparatus for manufacturing a silicon carbide single crystal, and a silicon carbide single crystal ingot, obtaining a silicon carbide single crystal reduced in defects such as threading dislocations, are provided. The method manufactures a silicon carbide single crystal by supplying a raw material gas into a reaction vessel with a seed substrate, and heats the interior to grow a silicon carbide single crystal on the surface of the seed substrate. The method includes growing the silicon carbide single crystal on the seed substrate surface, while controlling the temperature, to perform pair annihilation of threading dislocations or synthesis of the threading dislocations; and a second step of maintaining the temperature inside the reaction vessel in the state of the first predetermined temperature after execution of the first step, to bring the leading ends of the threading dislocations close to the surface of the seed substrate.

This application provides an apparatus and method for reducing the density of through-type dislocation defects in silicon carbide crystals. The apparatus includes an insulation component formed by an upper insulation layer, a first outer insulation layer, and a lower insulation layer. The insulation component is provided with gas exchange channels. By placing a crucible containing a silicon carbide seed crystal and silicon carbide raw material into the insulation component and placing them together into a single crystal growth furnace, silicon carbide crystal is grown according to the parameters set for each growth stage to obtain an N-type silicon carbide crystal. When in the isothermal section, N2 is introduced into the single crystal growth furnace in a cycle of n periods according to a first flow rate state and a second flow rate state. Nitrogen is intentionally doped into the silicon carbide crystal during the growth process through the gas exchange channels to increase the conversion probability and ejection probability of through-type dislocations to basal plane dislocations and stacking faults in the N-type silicon carbide crystal. This solves the problem of high dislocation density in SiC single crystals grown by the current PVT method.

The invention relates to the field of semiconductor micro-nano light-emitting devices, in particular to a high-density AlN penetrating dislocation ultraviolet light-emitting device and a preparation method thereof, which are suitable for high-integration, small-size and high-luminous-intensity micro-nano light-emitting devices. The method comprises the following steps: firstly, epitaxially growing a high-quality AlN thin film on an Al2O3 substrate by a pulse laser deposition method, and then measuring the luminescence behavior of penetrating dislocation in the AlN thin film by utilizing a cathode fluorescence spectrum. Due to the fact that large lattice mismatch exists between the AlN thin film and the Al2O3 substrate, a high-density penetrating dislocation array is formed in the grown AlN thin film. And due to the change of coordination number and bond length penetrating through the dislocation core, the dislocation shows a high-brightness ultraviolet light-emitting phenomenon, and a micro-nano light-emitting device taking dislocation as a light-emitting unit is formed. The invention provides a new thought for the application of nano-scale dislocation in the field of functional devices, and lays a foundation for the development of novel micro-nano light-emitting devices in the fields related to high-resolution displays, quantum communication and micro photoelectric sensors.

The present invention provides a method for preparing a silicon-based patterned substrate, comprising the following steps: S1. growing a first extension layer on a Si substrate; S2. etching the first extension layer until the Si substrate is exposed; S3. growing a dielectric layer on the exposed Si substrate; S4. etching the dielectric layer within the width range of the first strip-shaped trench until the Si substrate is exposed; S5. growing a second extension layer on the Si substrate exposed by the second strip-shaped trench; S6. etching a strip-shaped window in the second extension layer above the dielectric layer; S7. removing the dielectric layer under the strip-shaped window, thereby forming a Si-based patterned substrate in a shape of a Chinese character 'hui'. By epitaxially growing group III-V semiconductor materials such as GaAs, InP, GaN, etc. on the prepared Si-based patterned substrate in the shape of a Chinese character 'hui', most of the threading dislocations can be confined within the patterned substrate, realizing the epitaxy of low-defect-density Si-based GaAs, InP, GaN, etc. materials.

An embodiment of the present invention provides a semiconductor epitaxial structure and a method for preparing a semiconductor epitaxial structure, relating to the field of semiconductor epitaxial technology. The semiconductor epitaxial structure includes a substrate, a nucleation layer and a buffer layer. The present invention forms a nucleation layer on the substrate and then forms a buffer layer on the nucleation layer, wherein the nucleation layer includes multiple layers of periodically doped and repeatedly arranged semiconductor periodic stacks, so that the nucleation layer forms a doped superlattice structure with different doping types. The embodiment of the present invention uses doped superlattice structures with different doping types to improve the crystal quality of the nucleation layer. The embodiment of the present invention utilizes the formed doped superlattice to reduce epitaxial layer threading dislocations and obtain an epitaxial film with high crystal quality, and can simply and efficiently obtain a high-quality nucleation layer, reduce epitaxial layer threading dislocations, and thus obtain an epitaxial film with high crystal quality.

The present invention provides a semiconductor light-emitting element and a method for manufacturing the same. The epitaxial stack comprises an N-type semiconductor layer, an active region, a P-type semiconductor layer, and a V-shaped pit extending through the active region. Furthermore, a static charge collection layer is provided between the N-type semiconductor layer and the active region, with the tip of the V-shaped pit extending into the static charge collection layer. The N-type semiconductor layer has threading dislocations. Thus, the static charge collection layer collects static charge on the lower surface of the epitaxial stack (i.e., the N-type semiconductor layer side). The threading dislocations and the V-shaped pits then form a leakage path, transporting the static charge to the surface of the epitaxial stack (i.e., the P-type semiconductor layer side) to neutralize the accumulated positive charge. This prevents static charge from accumulating on the lower surface of the epitaxial stack, reduces the risk of electrostatic breakdown of the semiconductor light-emitting element, and improves the anti-static capability of the semiconductor light-emitting element.

Embodiments relate to a semiconductor device, which includes: a substrate made of a first material; an insulating layer formed on an upper surface of the substrate; a trench formed at the insulating layer to penetrate the insulating layer toward the substrate; and a seed layer disposed in the trench. The seed layer is made of a second material, the second material lattice-mismatches with respect to the first material, the seed layer includes a threading dislocation extending at least partially in a first direction non-parallel to the upper surface of the substrate and parallel to a <110> direction of a (111) plane and a threading dislocation extending at least partially in a second direction, and the extension of the threading dislocation is terminated at a sidewall of the trench.

A numerical control machining method for a thread buckle head comprises the following steps that after thread turning is completed, parameters of a residual thread buckle are input into a lathe main machine; the starting point of the screwer is positioned according to the parameters of the residual thread buckle, the difference between the starting point of the screwer and the starting point of the thread turning process is 0.5 thread pitch, and it is ensured that the screwer turns the residual thread buckle in a feeding mode; rapid feeding and drawing of the screwer are controlled by increasing the acceleration and deceleration constants of the moving shaft of the numerically controlled lathe and the rotating speed of the main shaft, and the ratio of the acceleration and deceleration constants of the moving shaft of the numerically controlled lathe to the rotating speed of the main shaft is the same as that in the thread turning process; and controlling the screwer to feed repeatedly for multiple times, and turning the residual thread in a layered manner. The length of the thread buckle head can be controlled within 1 / 4 circle arc length, and the angle is steeper and far smaller than 1 / 3 circle arc length, so that it is guaranteed that the thread buckle head can be rapidly and accurately aligned during field assembly, and thread dislocation grinding damage is avoided.

A light emitting element includes an n-type semiconductor, a p-type semiconductor, and an active layer between the n-type semiconductor and the p-type semiconductor, threading dislocations are formed in the n-type semiconductor, and openings are formed on a surface of the n-type semiconductor based on the threading dislocations.

A method and an apparatus for manufacturing a silicon carbide single crystal, and a silicon carbide single crystal ingot, obtaining a silicon carbide single crystal reduced in defects such as threading dislocations, are provided. The method manufactures a silicon carbide single crystal by supplying a raw material gas into a reaction vessel with a seed substrate, and heats the interior to grow a silicon carbide single crystal on the surface of the seed substrate. The method includes growing the silicon carbide single crystal on the seed substrate surface, while controlling the temperature, to perform pair annihilation of threading dislocations or synthesis of the threading dislocations; and a second step of maintaining the temperature inside the reaction vessel in the state of the first predetermined temperature after execution of the first step, to bring the leading ends of the threading dislocations close to the surface of the seed substrate.

SiC wafers the difference between the density of filament dislocations exposed on a first surface and the density of filament dislocations exposed on a second surface is 10% or less of the filament dislocation density on the surface with the higher filament dislocation density on the first surface and the second surface, 90% or more of the filament dislocations exposed on the surface with the higher filament dislocation density extend to the surface with the lower filament dislocation density, and The density of exposed dislocations on the surface with the higher dislocation density between the first and second surfaces is at most 1.5 dislocations / mm². 2 amounts, wherein the filament dislocations exposed on a first surface and a second surface of a SiC wafer can be matched by identifying the exposed filament dislocations on one of the surfaces through non-destructive measurement.

A method for hindering the growth of dislocations in GaN by covering it with SiO2. Step S1: In the MOCVD reaction chamber, a GaN nucleation layer is prepared on a sapphire substrate. Step S2: Etching. The substrate and GaN are transferred out of the reaction chamber and selectively etched using KOH. Step S3: Deposition of silicon dioxide. The substrate is transferred to the PECVD reaction chamber, and a SiO2 thin film is deposited on the surface of the nucleation layer. Step S4: Etching of silicon dioxide. The SiO2 thin film on the surface is removed by photolithography etching. Step S5: Continuing the growth of gallium nitride. The substrate is transferred into the MOCVD reaction chamber, and the GaN epitaxial growth is continued. The present invention utilizes the principle that the corrosion rates are different at the defective and non-defective parts of the gallium nitride material, and corrosion pits can be formed at the parts with threading dislocations through selective corrosion. Depositing SiO2 on the surface of gallium nitride can hinder the further growth of threading dislocations, and removing the deposited SiO2 by photolithography means can accurately control whether there is SiO2 on the surface of the GaN nucleation layer after photolithography, reducing the threading dislocation density of the subsequently grown GaN.

A semiconductor wafer for forming GaN semiconductor components having a diameter of at least 100 mm, comprising a substrate having an upper face and a lower face, wherein: the substrate is formed on the upper face of silicon. A transition layer is integrally bonded to the upper face of the substrate. A first GaN layer is integrally formed on the transition layer. The first GaN layer comprises a first GaN partial layer and a second GaN partial layer. The second GaN partial layer is formed on the first GaN partial layer. The second GaN partial layer comprises, on average, a lower number of threading dislocations than the first GaN partial layer. The first GaN partial layer has a first layer thickness and the second GaN partial layer has a second layer thickness, the second layer thickness being greater than or equal to the first layer thickness.

The application provides a method for identifying penetrating dislocations in silicon carbide, and the method comprises the following steps: performing preliminary etching on a silicon carbide sample to be identified; selecting a suitable diffraction vector; calculating relevant parameters corresponding to X-ray topography detection under the selected diffraction vector by using Bragg diffraction principle, the relevant parameters containing an incident angle; observing TSD and TED etch pits of the preliminary etched silicon carbide sample; recording an included angle between a line connecting the highest point and the lowest point of the selected etch pit and a horizontal line; obtaining an average value of the included angle of the selected etch pit; multiplying the average value of the included angle by a fixed coefficient to obtain a coefficient included angle; comparing the coefficient included angle with the incident angle of the selected diffraction vector; if the coefficient included angle is greater than the incident angle, directly performing X-ray topography detection; otherwise, etching again; and identifying by using an image of the X-ray topography detection. The application can effectively realize positioning and counting of different types of dislocations in silicon carbide.

To provide a method for manufacturing a SiC single crystal and a method for manufacturing a SiC substrate, capable of achieving the simplification of a process and cost reduction.SOLUTION: A method for manufacturing a SiC single crystal comprises: a step S100 of preparing a seed crystal formed of a SiC single crystal having a predetermined off angle in a predetermined direction using a (0001) plane or a (000-1) plane as a principal surface; and a step (S130) of forming a growth layer formed of a SiC single crystal on the principal surface of the seed crystal heated in an atmosphere including nitrogen gas using SiC gas obtained by heating and sublimating a raw material including carbon and silicon as a raw material, in which a penetration dislocation appearing on the principal surface of the seed crystal is converted into a dislocation extending in a c in-plane direction in an initial formation layer formed in the initial stage of the growth layer. The predetermined off angle is 14° or more.SELECTED DRAWING: Figure 3

The invention discloses a nitride semiconductor epitaxial structure for improving blue-green dual-wavelength luminous intensity and a growth method of the nitride semiconductor epitaxial structure. The epitaxial structure sequentially comprises a buffer layer, an undoped GaN layer, an undoped GaN layer, an N-type GaN layer, a stress release layer, a stress release layer, a green light multi-quantum well structure, a V-type defect filling layer, a low-temperature opening Pits layer, a defect blocking layer, a blue light multi-quantum well structure, an electron buffer layer, an electron blocking layer, a P-type GaN layer, an InGaN contact transition layer and a P-type contact layer. Wherein the green light multi-quantum well adopts a wide-well narrow-barrier design to relieve lattice strain and piezoelectric polarization effect; a three-layer defect regulation and control structure is arranged between the green light area and the blue light area, and through stress induction and dislocation conversion, dislocation is prevented from penetrating to extend to the blue light area, and the crystal quality is improved. According to the growth method, the epitaxy of each functional layer is controlled in stages under the conditions of different temperature zones and V / III ratios, and the construction of the high-quality multi-quantum well integrated structure is realized.

The invention discloses a preparation method of a nitride semiconductor laser. The method comprises the following steps: providing a gallium nitride substrate; sequentially growing a P-type waveguide layer, a quantum well layer and an N-type waveguide layer on the gallium surface of the gallium nitride substrate; wherein the doping concentration of the P-type waveguide layer is gradually changed along the growth direction; firstly removing the gallium nitride substrate, and then bonding a heat dissipation heat sink on one side, far away from the quantum well layer, of the P-type waveguide layer; or, a heat dissipation heat sink is bonded on the side, away from the quantum well layer, of the N-type waveguide layer, and then the gallium nitride substrate is removed. The gallium surface serves as a growth surface, heat scattering is facilitated, the high-power output performance is improved, the P-type waveguide layer is formed firstly, the crystal quality and the doping effect of the P-type waveguide layer can be improved, the hole transmission path is shortened, the non-radiative recombination loss is reduced, meanwhile, the doping concentration of the P-type waveguide layer is gradually changed, and the efficiency is improved. Lattice mismatch of the substrate and the epitaxial layer can be absorbed step by step through staged lattice matching, and penetration dislocation is reduced.