131 results about "Lateral overgrowth" patented technology

An epitaxy procedure for growing extremely low defect density non-polar and semi-polar III-nitride layers over a base layer, and the resulting structures, is generally described. In particular, a pulsed selective area lateral overgrowth of a group III nitride layer can be achieved on a non-polar and semi-polar base layer. By utilizing the novel P-MOCVD or PALE and lateral over growth over selected area, very high lateral growth conditions can be achieved at relatively lower growth temperature which does not affect the III-N surfaces.

A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.

There are provided a GaN field effect transistor (FET) exhibiting an excellent breakdown voltage owing to the high quality of GaN crystal in a region where the electric lines of force concentrate during operation of the same, and a method of manufacturing the same. The FET has a layer structure formed of a plurality of GaN epitaxial layers. A gate electrode and a source electrode are disposed on the surface of the layer structure, and a drain electrode is disposed on the reverse surface of the same. A region of the layer structure in which the electric lines of force concentrate during operation of the FET has a reduced dislocation density compared with the other regions in the layer structure. The GaN FET is manufactured by forming, on a crystal-growing substrate having a surface formed with a plane pattern of a material other than a GaN-based material in an identical design to a plane pattern of an electrode determining the region in which the electric lines of force concentrate, a plurality of GaN epitaxial layers, one upon another, by using the epitaxial lateral overgrowth technique, thereby forming a layer structure, and then forming operational electrodes on the surface of the layer structure.

A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.

Semiconductor devices are fabricated using semiconductor nano-rod arrays, which are merged through coalescence into a continuous planar layer after the nano-rods in the nano-rod array are fabricated by growth or etching. Merging of the nano-rods through coalescence into a continuous layer is achieved by tuning the growth conditions into a regime allowing epitaxial lateral overgrowth.

An AlN layer having a surface of a texture structure is formed on a sapphire substrate. Then, a growth suppressing material layer is formed on the AlN layer so that the AlN layer is partially exposed to the outside. Then, group III nitride compound semiconductor layers are grown on the AlN layer and on the growth suppressing material layer by execution of an epitaxial lateral overgrowth method. Thus, a group III nitride compound semiconductor device is produced. An undercoat layer having convex portions each shaped like a truncated hexagonal pyramid is formed on a substrate. Group III nitride compound semiconductor layers having a device function are laminated successively on the undercoat layer.

Transistors and / or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and / or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and / or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and / or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

Gallium nitride substrates are grown by epitaxial lateral overgrowth using multiple steps. On a masked substrate having openings areas, selective growth produces first triangular stripes in which most of the threading dislocations are bent at 90°. In a second step, growth conditions are changed to increase the lateral growth rate and produce a flat (0001) surface. At this stage the density of dislocations on the surface is <5×107 cm 2. Dislocations are primarily located at the coalescence region between two laterally grown facets pinching off together. To further decrease the dislocation density a second masking step is achieved, with the openings exactly located above the first ones. Threading dislocations (TDs) of the coalescence region do not propagate in the top layer. Therefore the density of dislocations is lowered below <1×107 cm lover the entire surface.

Optoelectronic devices are provided that incorporate quantum dots as the electroluminescent layer in an inorganic wide-bandgap heterostructure. The quantum dots serve as the optically active component of the device and, in multilayer quantum dot embodiments, facilitate nanoscale epitaxial lateral overgrowth (NELOG) in heterostructures having non-lattice matched substrates. The quantum dots in such devices will be electrically pumped and exhibit electroluminescence, as opposed to being optically pumped and exhibiting photoluminescence. There is no inherent “Stokes loss” in electroluminescence thus the devices of the present invention have potentially higher efficiency than optically pumped quantum dot devices. Devices resulting from the present invention are capable of providing deep green visible light, as well as, any other color in the visible spectrum, including white light by blending different sizes and compositions of the dots and controlling manufacturing processes.

Provided is a nitride semiconductor device with high reliability and high flexibility in design and manufacture of the device. The nitride semiconductor device comprises a seed crystal portion (11) formed on a sapphire substrate (10) and having a mask (12) on one side surface thereof, and a GaN layer (15) grown on the sapphire substrate (10) and the seed crystal portion (11) through epitaxial lateral overgrowth. The GaN layer (15) is grown only from an exposed side surface of the seed crystal portion (11) which is not covered with the mask (12), so the lateral growth of the GaN layer (15) is asymmetrically carried out. Thereby, a meeting portion (32) is formed in the vicinity of a boundary between the seed crystal portion (11) and the mask (12) in a thickness direction of the GaN layer (15). Therefore, as the meeting portion (32) is formed in a position away from the center between the adjacent seed crystal portions (11) in a direction parallel to a surface of the substrate, a width WL of a lateral growth region is larger with respect to a pitch WP of the seed crystal potion (11), compared with conventional configurations.

Provided is a nitride semiconductor device with high reliability and high flexibility in design and manufacture of the device. The nitride semiconductor device comprises a seed crystal portion (11) formed on a sapphire substrate (10) and having a mask (12) on one side surface thereof, and a GaN layer (15) grown on the sapphire substrate (10) and the seed crystal portion (11) through epitaxial lateral overgrowth. The GaN layer (15) is grown only from an exposed side surface of the seed crystal portion (11) which is not covered with the mask (12), so the lateral growth of the GaN layer (15) is asymmetrically carried out. Thereby, a meeting portion (32) is formed in the vicinity of a boundary between the seed crystal portion (11) and the mask (12) in a thickness direction of the GaN layer (15). Therefore, as the meeting portion (32) is formed in a position away from the center between the adjacent seed crystal portions (11) in a direction parallel to a surface of the substrate, a width WL of a lateral growth region is larger with respect to a pitch WP of the seed crystal potion (11), compared with conventional configurations.

A method of forming a high germanium concentration, low defect density silicon germanium film and its associated structures is described, comprising forming a dielectric layer on a substrate, patterning the dielectric layer to form a silicon region and at least one dielectric region, and forming a low defect silicon germanium layer on at least one dielectric region.

The present invention provides a method for manufacturing a free-standing substrate, comprising: growing a first layer having a sacrificial layer on a growth substrate; patterning the first layer into a patterned first layer having a structure of a plurality of protrusions; growing a second layer on the patterned first layer having a structure of a plurality of protrusions by epitaxial lateral overgrowth; and separating the second layer from the growth substrate by etching away the sacrificial layer, wherein the separated second layer functions as a free-standing substrate for epitaxy. Also, the present invention provides a method for manufacturing a free-standing light-emitting device, comprising: growing a first layer having a sacrificial layer on a growth substrate; patterning the first layer into a patterned first layer having a structure of a plurality of protrusions; growing a second layer on the patterned first layer having a structure of a plurality of protrusions by epitaxy growth; forming a reflecting layer on the second layer; forming a conductive substrate on the reflecting layer; and separating the second layer, the reflecting layer, and the conductive substrate from the growth substrate by etching away the sacrificial layer, so as to form a free-standing light-emitting device.

A single crystal silicon micromachined capacitive microphone is disclosed. The microphone comprises a flexible plate made from a bottom layer of a first epitaxial single crystal silicon layer, a stiff and perforated plate made from a portion of a second epitaxial single crystal silicon layer, a supporting frame is made from a combination of lateral overgrowth of the first epitaxial single crystal silicon layer and a polysilicon layer grown or deposited on the surface of an insulating layer, and an air gap is formed by etching a portion of the first epitaxial single crystal silicon layer. Both the first epitaxial single crystal silicon layer and the second epitaxial single crystal silicon layer are developed from a single crystal silicon substrate. A micromaching technology based on selective formation and etching of porous single crystal silicon layers is used to make the microphone structure.

A photonic crystal light emitting diode (“PXLED”) is provided. The PXLED includes a periodic structure, such as a lattice of holes, formed in the semiconductor layers of an LED. The parameters of the periodic structure are such that the energy of the photons, emitted by the PXLED, lies close to a band edge of the band structure of the periodic structure. Metal electrode layers have a strong influence on the efficiency of the PXLEDs. Also, PXLEDs formed from GaN have a low surface recombination velocity and hence a high efficiency. The PXLEDs are formed with novel fabrication techniques, such as the epitaxial lateral overgrowth technique over a patterned masking layer, yielding semiconductor layers with low defect density. Inverting the PXLED to expose the pattern of the masking layer or using the Talbot effect to create an aligned second patterned masking layer allows the formation of PXLEDs with low defect density.

Exemplary embodiments provide semiconductor nanowires and nanowire devices / applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.

A technique for growing a high quality gallium nitride layer on a uniform nano-patterned substrate is described. The invented technique is based on the transfer of ordered nano-patterns from a nano-template to the substrate, followed by the growth of gallium nitride on the nano-patterned substrate. The nano-patterned substrate serves as a buffer layer to reduce the stress and dislocations.

An epitaxial deposition process produces epitaxial lateral overgrowth (ELO) of nitride based materials directly a patterned substrate (10). The substrate (10) is preferably formed from SiC or sapphire, and is patterned with a mask (12), preferably formed of silicon nitride, having a plurality of openings (13) formed therein. A nucleation layer (14), preferably formed of AlGaN, is grown at a high reactor temperature of 700-1100 degrees C., which wets the exposed substrate surface, without significant nucleation on the mask (12). This eliminates the need for regrowth while producing smooth growth surfaces in the window openings (13) as well as over the mask (12). Subsequent deposition of a nitride based material layer (16), preferably GaN, results in a relatively defect free planar surfaced material grown laterally over the mask (12).

A circuit structure includes a substrate; a patterned mask layer over the substrate, wherein the patterned mask layer includes a plurality of gaps; and a group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layer includes a first portion over the mask layer and second portions in the gaps, wherein the III-V compound semiconductor layer overlies a buffer / nucleation layer.

Lateral epitaxial overgrowth of non-polar III-nitride seed layers reduces threading dislocations in the non-polar III-nitride thin films. First, a thin patterned dielectric mask is applied to the seed layer. Second, a selective epitaxial regrowth is performed to achieve a lateral overgrowth based on the patterned mask. Upon regrowth, the non-polar III-nitride films initially grow vertically through openings in the dielectric mask before laterally overgrowing the mask in directions perpendicular to the vertical growth direction. Threading dislocations are reduced in the overgrown regions by (1) the mask blocking the propagation of dislocations vertically into the growing film and (2) the bending of dislocations through the transition from vertical to lateral growth.

At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

High quality free standing GaN is obtained using a new modification of the Epitaxial Lateral Overgrowth technology in which 3D islands or features are created only by tuning the growth parameters. Smoothing these islands (2D growth) is achieved thereafter by setting growth conditions producing enhanced lateral growth. The repetition of 3D-2D growth results in multiple bending of the threading dislocations thus producing thick layers or free standing GaN with threading dislocation density below 106 cm−2.

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and / or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and / or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and / or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.