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439 results about "Sapphire substrate" patented technology

Intelligent control system and method for sapphire substrate polishing

The invention relates to the technical field of machining, in particular to an intelligent control system and method for sapphire substrate polishing, and the method comprises the following steps: S1, surface topography data acquisition: collecting surface roughness data and a three-dimensional topography distribution diagram of a sapphire substrate in real time; s2, generating characteristic parameters: extracting the surface waviness, the local recess depth, the bulge density, the lattice distortion index and the residual stress distribution gradient as the characteristic parameters; s3, dynamic parameter adjustment: generating a dynamic adjustment instruction of the polishing pressure, the rotating speed of the polishing disk and the supply rate of the polishing solution; s4, distribution optimization of the polishing solution: realizing uniform coverage of the polishing solution on the surface of the substrate; s5, stress real-time monitoring: generating a stress abnormity early warning signal; s6, outputting a closed-loop control instruction: feeding back a stress abnormity early warning signal to the adaptive control model, and iteratively correcting the dynamic adjustment instruction; according to the method, the risks of stress concentration and fatigue damage can be reflected in real time, and the safety and high efficiency of the polishing process are ensured.
Owner:嘉兴南湖学院

Sapphire substrate automatic defect detection and classification method based on visual detection

The invention discloses a sapphire substrate automatic defect detection and classification method based on visual inspection, and relates to the technical field of visual inspection and image processing, and the method comprises the steps: carrying out the adaptive threshold segmentation and phase consistency detection of a multi-modal image data set, and carrying out the fusion, and obtaining a joint defect probability graph; extracting defect candidate areas from the joint defect probability graph, and generating unified feature representation; inputting the unified feature representation into a double-branch neural network, performing fusion and classification through a cross attention mechanism, outputting a defect classification result, performing reconstruction by using a NeRF algorithm, outputting a defect three-dimensional shape, and generating a three-dimensional shape map; and generating a defect thermodynamic diagram based on the three-dimensional morphology map, performing space-time correlation analysis in combination with equipment process parameters, and outputting a sapphire substrate defect process analysis report. According to the method, the image contrast and the defect characterization capability are improved, so that the comprehensiveness and the sensitivity of detection are remarkably enhanced.
Owner:QINGDAO JIAXING HIGH-TECH DEVELOPMENT CO LTD

Gallium oxide heteroepitaxial substrate and preparation method thereof

The invention relates to the technical field of semiconductors, in particular to a gallium oxide heteroepitaxial substrate and a preparation method thereof. The gallium oxide heteroepitaxial substrate comprises: a sapphire substrate; the sapphire substrate is provided with a beveled surface; a periodic pattern structure is arranged on the beveled surface of the sapphire substrate; the depth of a repetitive unit of the periodic pattern structure is 200 nm to 20 [mu] m, the maximum envelope size is 100 nm to 50 [mu] m, and the period interval is 200 nm to 100 [mu] m. The sapphire substrate is subjected to beveling processing and patterning processing, lattice mismatch is remarkably relieved, stress is released, accordingly, dislocation density is reduced, defects in the gallium oxide thin film are reduced, the gallium oxide single crystal thin film with better crystal quality is obtained, and the method has important application value in the field of gallium oxide thin film semiconductor material preparation.
Owner:GALLIUM TECHNOLOGY (CHANGZHOU) CO LTD

Micro LED transfer method and naked eye 3D display panel

The invention relates to a micro LED transfer method and a naked eye 3D display panel, and relates to the technical field of semiconductor display. According to the transfer method of the micro LED, a first magnetic region is formed in a sapphire substrate of each micro LED unit, and a second magnetic region is formed at the bottom of each groove, so that the micro LED units can be adsorbed in a transfer substrate; the first electrode comprises a first metal layer, a second magnetic metal layer and a third metal layer, and a third magnetic metal layer is arranged below each pixel electrode, so that when the micro LED units on the transfer substrate are transferred to the driving substrate, the first electrode and the third magnetic metal layers have a magnetic attraction effect, and the micro LED units on the transfer substrate can be transferred to the driving substrate; therefore, the transfer accuracy of the micro LED unit is greatly improved, and the transfer yield of the micro LED unit is greatly improved.
Owner:LOHUA CHIP-DISPLAY TECHNOLOGY DEVELOPMENT (JIANGSU) CO LTD

Method for depositing gold electrode on surface of BSCCO single crystal

The invention discloses a method for depositing a gold electrode on the surface of a BSCCO single crystal, and belongs to the technical field of superconducting device preparation, and the method comprises the following steps: S1, cleaning a sapphire substrate; s2, placing the sapphire substrate in a vacuum pipeline, fixing the PDMS film adhered with the BSCCO single crystal on the sapphire substrate, and cleaving the BSCCO single crystal in the vacuum pipeline; s3, depositing a layer of gold film on the surface of the BSCCO single crystal fixed on the sapphire substrate by magnetron sputtering; s4, photoetching and transferring a gold electrode pattern on the surface of the BSCCO single crystal; s5, carrying out ion beam etching to remove the gold film outside the photoetching pattern; s6, evaporating a silicon oxide film as a protective layer; and S7, removing the photoresist by using an organic solvent. According to the method disclosed by the invention, the necessary steps of depositing the gold electrode on the BSCCO single crystal are completed in a vacuum environment, so that the influence of an organic reagent, water and air on the structure of the BSCCO single crystal is effectively reduced.
Owner:NANJING UNIV

Deep ultraviolet LED epitaxial structure, deep ultraviolet LED device comprising same and preparation method of deep ultraviolet LED epitaxial structure

The invention discloses a deep ultraviolet LED epitaxial structure, a deep ultraviolet LED device comprising the same and a preparation method, and the epitaxial structure sequentially comprises a sapphire substrate, an AlN nanowire array layer, an AlN intrinsic layer and an AlGaN light-emitting structure layer from bottom to top. The AlGaN light-emitting structure layer further comprises an n-type AlGaN electron injection layer, a quantum well active layer, a p-type AlGaN electron blocking layer and other device structures. According to the invention, the vertically arranged AlN nanowire array is introduced to replace a traditional AlN buffer layer, so that lattice mismatching stress caused by a substrate is significantly released, and the dislocation density of an epitaxial layer is effectively reduced; meanwhile, the introduction of the AlN intrinsic layer further flattens the epitaxial interface and optimizes the lattice quality, thereby providing a high-quality template for the growth of a high-performance AlGaN material. The epitaxial structure is suitable for an LED device in a deep ultraviolet band, and the crystal quality, the electrical property and the luminous efficiency of the device can be improved.
Owner:WUHAN TEXTILE UNIV

Negative-electrode-free lithium ion battery current collector, preparation method thereof and negative-electrode-free lithium ion battery

The invention provides a preparation method and application of a single crystal copper foil current collector for a negative-electrode-free lithium ion battery, and aims to improve the cycling stability and electrochemical performance of the battery. The preparation method comprises the following steps: (1) carrying out ultrasonic cleaning on the commercial copper foil by using hydrochloric acid, absolute ethyl alcohol and deionized water in sequence to remove surface pollutants; (2) a phosphoric acid and absolute ethyl alcohol mixed electrolyte is used for electrochemical polishing, and the surface smoothness and uniformity are improved; (3) performing high-temperature heat treatment on the sapphire substrate in high-purity argon to induce abnormal growth of crystal grains; (4) annealing in a reducing atmosphere of 1000-1100 DEG C to enhance the crystal orientation and crystallinity of Cu (111); and (5) rapidly cooling to room temperature, stabilizing the structure and preventing oxidation. When the obtained single crystal copper foil is used for the negative-electrode-free lithium battery, the single crystal copper foil is used as a negative electrode current collector to electrochemically deposit lithium metal and then is reassembled into the negative-electrode-free battery. The current collector is high in conductivity and stable in structure, lithium deposition uniformity can be remarkably improved, dendritic crystal growth is inhibited, the cycle life is prolonged, and safety is improved.
Owner:CENT SOUTH UNIV

Adjustable machining grinding equipment

The invention discloses adjustable machining grinding equipment, and relates to the technical field of machining. According to the equipment, a multi-dimensional adjusting mechanism is innovatively integrated, a sliding block is driven through a rotatable double-thread lead screw, stepless adjustment of the grinding radius is achieved, and the equipment is suitable for machining of the inner diameters of workpieces of different sizes; and in combination with a dynamic balance weight system, vibration in high-speed grinding is effectively inhibited, and the stability is improved. Meanwhile, a pneumatic-servo cooperative control system is adopted, stepless switching of the grinding pressure in the four stages of light pressure, medium pressure, heavy pressure and fine grinding is supported, the revolution-rotation speed ratio of the grinding disc to the workpiece is synchronously regulated and controlled, and the uniformity of the grinding track is optimized. In addition, the equipment is provided with a PLC program control module and a touch screen interface, 30 sets of technological parameters can be preset and stored, one-key calling is achieved, and the machining efficiency and consistency of complex parts are remarkably improved. According to the design, the adaptability of the equipment to sapphire substrates, gears and hard alloy special-shaped high-hardness workpieces is greatly expanded.
Owner:NINGBO UNIV

Preparation method of SERS (Surface Enhanced Raman Scattering) substrate for multi-component residue detection

The invention belongs to the technical field of preparation of SERS (Surface Enhanced Raman Scattering) substrates, and particularly relates to a preparation method of an SERS substrate for multi-component residue detection, which comprises the following steps: selecting a patterned sapphire substrate with a micro-nano structure surface; designing a plurality of arrangement modes, and establishing a laminated body physical model in which longitudinal layers of the multi-element SERS effect material are deposited and distributed layer by layer; according to a physical vapor deposition method and a chemical vapor deposition method, obtaining a laminated body substrate with a multi-layer deposition structure; using a mechanical cutting method to obtain a flat surface with transverse distribution of the multi-element material; a mechanical scribing method is used for scribing the ordered array structure, and the processing step of the SERS substrate with the multi-element materials distributed in the transverse direction and the longitudinal direction is completed; and soaking the processed SERS substrate in the solution, drying, and evaluating the SERS activity through a Raman spectrum to complete the preparation. By constructing transverse and longitudinal distribution of multi-component materials on the surface of the SERS substrate, the detection sensitivity of multi-component residues can be improved.
Owner:SHANDONG UNIV OF TECH

Acoustic wave filter based on AlN / AlGaN superlattice structure and preparation method thereof

The invention discloses an acoustic wave filter based on an AlN / AlGaN superlattice structure and a preparation method of the acoustic wave filter, and relates to the technical field of filters, the acoustic wave filter comprises a superlattice main body, and is characterized in that the superlattice main body comprises a substrate and a piezoelectric superlattice layer located on one side of the substrate; wherein the substrate is a Si substrate, a sapphire substrate or a SiC substrate; the piezoelectric superlattice layer is a composite alternating layer of an AIN layer and an Al < x > Ga < 1-x > N layer, and x is a constant greater than 0. The invention has the effects of reducing strain, improving compatibility and reliability, being suitable for high-frequency operation and remarkably improving electromechanical coupling performance.
Owner:FUJIAN SUNWISE SEMICON TECH CO LTD

Batch preparation method and application of single crystal boron nitride wafer based on copper-nickel single crystal film

The invention discloses a single crystal boron nitride wafer batch preparation method based on a copper-nickel single crystal film and application, and belongs to the technical field of two-dimensional material preparation and nano electronic device manufacturing. The method comprises the following steps: forming a Cu80Ni20 (111) single crystal film on a c-plane sapphire substrate through magnetron sputtering and high-temperature annealing to serve as a growth substrate; carrying out thermal conversion treatment on the ammonia borane precursor to form a supply source system capable of stably releasing a borazine gas phase precursor; a porous structure quartz sleeve is adopted to regulate and control the release behavior of a precursor, and multi-wafer airflow homogenization control is realized in a CVD system through a quartz staggered wafer carrier; and carrying out epitaxial growth, and synchronously preparing more than 10 single crystal boron nitride wafers which are consistent in crystal orientation, smooth in surface and free of crystal boundaries in a single batch. According to the method, efficient, uniform and repeatable batch preparation of the high-quality monocrystal h-BN is realized, and the obtained wafer has atomic-scale flatness and excellent insulating property and is suitable for high-performance two-dimensional electronic devices, deep ultraviolet photoelectric devices and quantum device platforms.
Owner:PEKING UNIV

Method for growing (310) oriented beta-Ga2O3 single crystal thick film on sapphire substrate

The invention provides a method for growing a (310) oriented beta-Ga2O3 single crystal thick film on a sapphire substrate. The method comprises the following steps: cleaning the sapphire substrate and then carrying out annealing treatment; and with hydrogen chloride gas, gallium metal and oxygen as reaction sources, epitaxially growing a (310) oriented beta-Ga2O3 single crystal thick film on the treated sapphire substrate by using a hydride vapor phase epitaxy method. According to the method for growing the (310) oriented beta-Ga2O3 single crystal thick film on the sapphire substrate, the process is simple, operation is easy, controllability is high, the obtained (310) oriented beta-Ga2O3 single crystal thick film is smooth in surface, compact and uniform in thickness, the crystallinity of the single crystal film layer is high, and the growth requirement of a single crystal epitaxial film layer of tens of micrometers can be met; in addition, the method provided by the invention can realize large-batch and large-scale production of the (310) oriented beta-Ga2O3 single crystal thick film, and meets the device preparation requirements.
Owner:BEIJING MING GALLIUM SEMICON CO LTD

Preparation method of high-quality gallium nitride film based on porous silicon nitride insertion layer

The invention provides a preparation method of a high-quality gallium nitride film based on a porous silicon nitride insertion layer. The preparation method comprises the following steps: firstly, sequentially depositing a GaN low-temperature buffer layer and a u-GaN layer subjected to compression strain on a patterned sapphire substrate; a porous SiNx insertion layer is deposited on the u-GaN layer in situ, a nanoscale hole structure penetrating in the thickness direction is formed in the porous SiNx insertion layer, and the u-GaN layer is exposed at holes; then GaN nanorods vertically grow at the holes, finally, growth conditions are regulated and controlled to enable the GaN nanorods to transversely grow and combine to form a flat high-quality GaN thin film, and a gap is formed between the porous SiNx insertion layer and the GaN thin film. According to the method, the internal stress of the GaN film can be effectively reduced, the dislocation density is reduced, the film quality is improved, the process is simple, and the method is suitable for large-scale and low-cost industrial production of the GaN film.
Owner:HEFEI UNIV OF TECH

Sapphire gallium nitride-based red light epitaxial wafer structure and preparation method thereof

The invention discloses a sapphire gallium nitride-based red light epitaxial wafer structure and a preparation method thereof, and belongs to the technical field of semiconductors, and the sapphire gallium nitride-based red light epitaxial wafer structure comprises a patterned sapphire substrate, a GaN substrate, n-type AlGaN, an InGaN quantum well, an AlGaN electron barrier layer, p-type GaN, ITO and a first electrode which are sequentially laminated; a second electrode is arranged on the n-type AlGaN; the InGaN quantum well, the AlGaN electron barrier layer, the p-type GaN and the ITO form a red light enhancement structure; a plurality of circular through holes determined based on a light scattering theory and a quantum confinement stark effect are formed in the vertical direction of the red light enhancement structure between the first electrode and the second electrode in a penetrating manner; under the condition that voltage is applied to the first electrode and the second electrode, generated electrons and holes are compounded in the InGaN quantum well to generate red light, and the quality of the red light epitaxial wafer is effectively improved.
Owner:ZHONGKE (SHENZHEN) WIRELESS SEMICON CO LTD

Method for preparing high-crystal-quality beta-Ga2O3 heteroepitaxial film on sapphire substrate

The invention provides a method for preparing a beta-Ga2O3 heteroepitaxial thin film with high crystal quality on a sapphire substrate, which comprises the following steps of: selecting a sapphire single crystal wafer as a substrate, cleaning the sapphire single crystal wafer, and putting the cleaned sapphire single crystal wafer into metal organic chemical vapor deposition equipment; with trimethyl gallium or triethyl gallium as a gallium source and oxygen as an oxygen source, growing a beta-Ga2O3 thin layer with the thickness of less than 10 nm; hydrogen is introduced, and the defect bond of the beta-Ga2O3 thin film is etched; the temperature of the substrate is increased to 1000 DEG C or above, oxygen is introduced, annealing is carried out, the defects are further bridged, and oxygen vacancies are reduced; and reducing the temperature of the substrate to the growth temperature, repeating the steps 2-4, and gradually accumulating the thickness to reach an expected value. According to the method, layer-by-layer growth and in-situ defect repair are combined, and the ultra-wide forbidden band beta-Ga2O3 heteroepitaxial crystal film with extremely low defect density and ultra-high quality is successfully prepared.
Owner:DALIAN UNIV OF TECH

A Micro-LED chip carrier substrate and a manufacturing method thereof

ActiveCN113506843BChip carrierPhysics
The present invention discloses a Micro-LED chip carrier substrate and a manufacturing method thereof. The Micro-LED chip carrier substrate includes a substrate, a connection layer connected to the front surface of the substrate on the back surface, and a plurality of microstructures disposed on the front surface of the connection layer. The microstructures have elasticity, and each microstructure is arranged in an array on the front surface of the connection layer. The Micro-LED chip carrier substrate of the present invention is used for temporarily bonding with a Micro-LED chip. When the Micro-LED chip is peeled off from a sapphire substrate by using a laser lift-off technology (LLO), the Micro-LED chip carrier substrate can effectively prevent the Micro-LED chip from cracking and / or shifting in position.
Owner:FUJIAN QIANGLI PHOTOELECTRICITY

Gallium oxide composite copper diamond ceramic material substrate and preparation method and application thereof

The invention provides a gallium oxide composite copper diamond ceramic material substrate and a preparation method and application thereof. The method comprises the steps that (1) a GaN superlattice buffer layer is formed on a sapphire substrate through low-temperature sputtering; (2) epitaxially growing a gallium oxide single crystal on the superlattice buffer layer to obtain a gallium oxide wafer; (3) bonding the gallium oxide wafer to a copper diamond ceramic material substrate; (4) decomposing the superlattice buffer layer by adopting a laser lift-off technology to obtain a gallium oxide wafer composite substrate; and (5) performing chemical mechanical polishing on the gallium oxide wafer surface of the gallium oxide wafer composite substrate to obtain the gallium oxide composite copper diamond ceramic material substrate. The gallium oxide composite copper diamond ceramic material substrate provided by the invention can be used as a substrate of a gallium oxide-based power device, the matching range is wide, the quality of a gallium oxide wafer is high, not only is the performance of the device improved, but also the heat dissipation problem of the device is effectively solved, and the method is simple in process and low in cost.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI

Preparation method of high-conductivity AlN / GaN heterojunction

PendingCN120529622AHeterojunctionSputtering
The invention discloses a high-conductivity AlN / GaN heterojunction which sequentially comprises a sapphire substrate, an AlN buffer layer, a GaN channel layer and an AlN barrier layer from bottom to top. The total polarization intensity in an AlN material of the GaN channel layer is far greater than the total polarization intensity in a GaN material of the AlN barrier layer, net positive charges appear at an interface, the positive charges attract free electrons, a triangular potential well is formed on one side of GaN near the interface, the electrons are limited in the potential well by quantum, and high-density two-dimensional electron gas is formed. Polycrystal AlN is converted into single crystal AlN through magnetron sputtering in combination with a thermal annealing technology, so that the characteristic of small stress of the single crystal AlN is reserved, and two-dimensional electron gas can be formed at the interface of the AlN / GaN heterojunction.
Owner:XIDIAN UNIV

Multistage junction termination structure of vertical GaN diode

The utility model belongs to the field of semiconductors, and discloses a multistage junction termination structure of a vertical GaN diode. The multistage junction termination structure comprises a sapphire substrate on which a GaN nodule layer grows; a silicon-doped n +-GaN layer is grown on the GaN nodule layer, a silicon-doped n-GaN layer is grown on the n +-GaN layer, a magnesium-doped p-GaN layer is grown on the n-GaN layer, and a magnesium-doped p +-GaN layer is grown on the p-GaN layer; etching from the p < + >-GaN layer to the n < + >-GaN layer, and preparing a negative electrode on the surface of the n < + >-GaN layer; etching from the p +-GaN layer to the p-GaN layer to form a continuous multi-stage step, and preparing a positive electrode on the surface of the p +-GaN layer; according to the utility model, after the multi-stage step junction termination structure is introduced, the electric field aggregation phenomenon is obviously relieved, which indicates that the junction termination structure effectively reduces the internal electric field peak value.
Owner:SOUTHERN UNIVERSITY OF SCIENCE AND TECHNOLOGY

Efficient micro-ring acousto-optic modulator

The invention provides a high-efficiency micro-ring acousto-optic modulator, which combines high sensitivity and sound wave regulation and control capability of a micro-ring resonator, adopts two pairs of optical waveguides and acoustic waveguides with grating couplers, realizes flexible control of sound wave and light wave propagation directions, can be configured to perform common or reverse propagation, and can be used for acoustic wave and light wave propagation. The method is suitable for exploring the time reversal symmetry and the optical nonreciprocity of the system. The device adopts the sapphire substrate, by virtue of high mechanical strength, high sound velocity and low acoustic loss, the sound wave mode quality and transmission stability are improved, and meanwhile, high-quality integration with silicon dioxide and lithium niobate films is ensured; the silicon substrate has remarkable advantages in the aspects of micro-nano processing, heat conductivity and electro-optical system compatibility, and large-scale manufacturing and system integration are facilitated. In addition, a chalcogenide waveguide with low optical loss is introduced into the device, so that the light field constraint and locality are enhanced, the overlapping and coupling strength of an acousto-optic mode is improved, and meanwhile, the interface scattering loss is reduced.
Owner:NINGXIA UNIVERSITY

Method for preferentially growing epsilon-phase gallium oxide epitaxial film through oxygen flow regulation and control

The invention belongs to the field of semiconductor materials, and discloses a method for preferentially growing an epsilon-phase gallium oxide epitaxial film through oxygen flow regulation and control. The preparation method comprises the following steps: cleaning a sapphire substrate, and putting the sapphire substrate into a cavity of a metal organic chemical vapor deposition system; setting air pressure in the reaction cavity, introducing carrier gas, raising the temperature to a first preset temperature, introducing first preset high-flow oxygen, and entering a substrate high-oxygen preheating stage; raising the temperature to a second preset temperature, opening the gallium source, introducing second preset low-flow oxygen, and entering an epitaxial low-oxygen growth stage; closing the gallium source, introducing third preset high-flow oxygen, and entering an in-situ high-oxygen annealing stage; and after annealing is finished, recovering normal pressure, cooling to room temperature, and taking out to obtain the epsilon-phase gallium oxide epitaxial film. The pure phase property and the crystal quality of the epsilon-phase gallium oxide epitaxial film are improved in an oxygen flow regulation and control mode, and a way is laid for subsequent preparation of electronic and power devices.
Owner:NANJING UNIV OF POSTS & TELECOMM

Gallium nitride-based red light emitting diode and preparation method thereof

PendingCN120152456AElectron holeContact layer
The invention belongs to the technical field of semiconductor photoelectrons, and provides a gallium nitride-based red light emitting diode and a preparation method thereof. The epitaxial structure of the gallium nitride-based red light emitting diode sequentially comprises a sapphire substrate, a low-temperature GaN nucleating layer, a high-temperature non-doped GaN buffer layer, an n-type GaN layer, a composite stress release layer, an In < x > Ga < 1-x > N / In < y > Ga < 1-y > N multi-quantum well light emitting layer, a low-temperature p-type protective layer, a p-Aly < 1 > Ga < 1-y > N electron barrier layer, a high-temperature p-type GaN layer and a p-type InGaN contact layer from bottom to top. The V-shaped layer and the Inx1Ga1-x1N / GaN superlattice structure layer are introduced between the n-type GaN layer and the In < x > Ga < 1-x > N / In < y > Ga < 1-y > N multi-quantum well light-emitting layer to perform stress release, so that the influence of a piezoelectric polarization field on the spatial distribution of an electron hole wave function is reduced, and the radiation recombination light-emitting efficiency of an active region is improved.
Owner:DONGGUAN YUTENG SEMICONDUCTOR TECHNOLOGY CO LTD

Full-color Nano-LED array

The invention provides a full-color Nano-LED (Light Emitting Diode) array. The full-color Nano-LED array comprises a sapphire substrate; sequentially superposing an N-type gallium nitride layer and a dielectric layer on the sapphire substrate; nanowires, wherein each nanowire is grown on a nanometer circular hole reserved in the dielectric layer; the transparent electric insulation layer is filled among the plurality of nanowires; p electrodes, wherein each P electrode is correspondingly arranged on each nanowire; the first scanning lines are arranged on the multiple P electrodes in the first direction, the number of the first scanning lines is multiple, and the multiple first scanning lines are arranged in parallel in the second direction; the N electrodes are arranged on the lower surface of the sapphire substrate, and the position of each N electrode corresponds to the position of each nanowire; the second scanning lines are arranged on the lower surfaces of the N electrodes in the second direction, the number of the second scanning lines is multiple, and the second scanning lines are arranged in parallel in the first direction. According to the array, an alternating current driving mode is adopted, and accurate regulation and control of submicron pixels are achieved.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI

Method for epitaxially growing Ga2O3 single crystal film on sapphire substrate and epitaxial structure

The invention provides a method for epitaxial growth of a Ga2O3 single crystal film on a sapphire substrate and an epitaxial structure. The method for epitaxial growth of the Ga2O3 single crystal film on the sapphire substrate comprises the following steps: S1, carrying out Al ion implantation treatment on the surface of the sapphire substrate; s2, performing temperature gradient in-situ oxidation treatment on the surface of the sapphire substrate to form an Al2O3 composite buffer layer; s3, carrying out etching treatment on the surface of the Al2O3 composite buffer layer by adopting etching gas; and S4, epitaxially growing a Ga2O3 single crystal film on the etched surface of the Al2O3 composite buffer layer to obtain an epitaxial structure. According to the invention, the quality of the epitaxial Ga2O3 single crystal film can be effectively improved, and the growth of a large-area continuous film can be realized.
Owner:HUBEI JIUFENGSHAN LAB

Silicon carbide semiconductor structure and manufacturing method therefor, and manufacturing method for semiconductor working device using silicon carbide semiconductor structure

PCT designated stageWO2025248349A1Semiconductor structureSingle crystal
A silicon carbide semiconductor structure. A III-V base layer and a support substrate can be used as a basic growth interface for a silicon carbide epitaxial layer or a doped silicon carbide epitaxial layer growing into a perfect single crystal. The support substrate may be, for example, a sapphire substrate, an aluminum nitride substrate, or a silicon carbide substrate. If the support substrate is an aluminum nitride substrate, the silicon carbide epitaxial layer or the doped silicon carbide epitaxial layer may directly grow. The III-V base layer is made of one of an aluminum nitride (AlN) material, a gallium nitride (GaN) material, and an AlN / GaN mixed material. The silicon carbide epitaxial layer or the doped silicon carbide epitaxial layer is formed on the III-V base layer by means of an epitaxial process. The III-V base layer is formed on the support substrate. After a semi-finished semiconductor working device is formed using the silicon carbide semiconductor structure, the support substrate and the III-V base layer can be stripped by means of various scientific processes.
Owner:RAYNEXT SEMICON CO LTD

Patterned composite substrate and LED chip

ActiveCN223943112UComposite substratePhysics
The utility model discloses a patterned composite substrate and an LED chip. The patterned composite substrate comprises a patterned base layer and a composite layer arranged on the patterned base layer. The graphical base layer comprises a sapphire substrate and a plurality of sunken structures arranged on the surface of the sapphire substrate, and the sunken structures are in a non-penetrating state on the sapphire substrate; the composite layer comprises a first SiO2 layer and a second SiO2 layer, the first SiO2 layer and the second SiO2 layer are periodically and alternately arranged, the first SiO2 layer is arranged on the surface of the sapphire substrate, the concave structure is filled with the second SiO2 layer, and the first SiO2 layer is connected with the second SiO2 layer. By implementing the LED epitaxial wafer, the reflection of light can be increased, the luminous efficiency of the LED epitaxial wafer can be improved, the working temperature of the chip can be reduced, and the reliability and the stability of the device can be improved.
Owner:JIANGXI ZHAOCHI INTEGRATED TECHNOLOGY CO LTD +1

A feedback control method for material removal rate in polishing of sapphire substrate

PendingCN122323038AMaterial removalPolishing
This application discloses a feedback control method for the material removal rate during sapphire substrate polishing, relating to the field of precision machining control technology. The method pre-establishes a tool head wear compensation model and a mapping model between the material removal rate and process parameters, generating a priority list of adjustment variables based on the sensitivity coefficients of each process parameter. During polishing, the measured material removal rate is obtained after detecting spacing changes using a non-contact displacement sensor array and compensating for tool head wear. The deviation between this rate and the target value is calculated cyclically according to the sampling period. Parameter adjustments are implemented using an incremental control law based on the priority list of adjustment variables. When the adjustment variable reaches its range boundary, the process automatically switches to the next level of process parameters. Simultaneously, the thickness of the removed material is accumulated, and polishing stops when the target value is reached. This application overcomes rate drift caused by polishing slurry degradation, tool head wear, and environmental disturbances, significantly improving the batch-to-batch thickness consistency and removal accuracy of sapphire substrates.
Owner:嘉兴南湖学院

Large-area hexagonal boron nitride heteroepitaxial film on sapphire substrate and preparation method thereof

The application belongs to the technical field of semiconductor material science and technology, and particularly relates to a large-area hexagonal boron nitride heteroepitaxial film on a sapphire substrate and a preparation method thereof. The technical scheme provides a large-area hexagonal boron nitride epitaxial film directly grown on a sapphire substrate. The preparation method adopts an ion beam assisted sputtering method. In the growth process, the main and auxiliary ion sources give high-energy ion sputtering respectively, so that high-energy B / N atoms cross the energy barrier of the preferred orientation between the B / N atoms and the substrate surface, form covalent bonding with the substrate surface, induce the hexagonal grid plane of the hexagonal boron nitride to extend vertically to the substrate surface, and thus obtain a large-area vertically-oriented hexagonal boron nitride epitaxial film. Compared with the common Van der Waals epitaxial growth method, the epitaxial method can effectively release stress, so that the bonding force between the hexagonal boron nitride film and the substrate surface is stronger, and the stability is better, and the hexagonal boron nitride film is suitable for being used as a template, a transition layer, a heat dissipation layer and the like of optoelectronic devices and electronic devices.
Owner:JILIN UNIVERSITY

Sapphire substrate grinding device

The utility model discloses a sapphire substrate grinding device in the technical field of grinding devices, which comprises a grinding device main body, a fixed column is fixed on the side surface of the grinding device main body, a movable rod is connected in the fixed column in a sliding manner, and one end of the movable rod far away from the fixed column is connected with a connecting sleeve rod in a sliding manner; a fixed column is fixed to one side of a grinding device body, one end of a movable rod is slidably connected into the fixed column, then the fixed column and the movable rod are fixed through a fixing bolt, meanwhile, a connecting sleeve rod is arranged at the other end of the movable rod, and the angle of a clamping frame is controlled through the connecting sleeve rod; and meanwhile, a first fixing rod and a second fixing rod which are arranged in a connecting sleeve rod are used for clamping a plurality of sapphires, and the problems that in the background technology, existing sapphire substrates are manually ground one by one, and when the number of the sapphires is large, time is wasted due to the fact that the sapphires are independently ground one by one are solved.
Owner:LI LI IND INTELLIGENT TECH (SUZHOU) CO LTD

Display device manufacturing method, insert substrate, and computer program stored in readable medium

A method for manufacturing a display device includes: performing a first repair process of detecting a first defective light emitting diode (LED) from a plurality of LEDs disposed on a sapphire substrate and removing the first defective LED; attaching the plurality of LEDs to an electrode pattern inserted into a substrate and separating the sapphire substrate from the plurality of LEDs; and performing a second repair process of detecting a second defective LED from the plurality of LEDs attached to the electrode pattern and replacing the second defective LED.
Owner:SAMSUNG ELECTRONICS CO LTD