Product
Patsnap Eureka
For R&D, Patsnap Eureka makes reading and utilizing patents & technical documents easy.
Patsnap Eureka AIR
Designed for self-driven R&D workflows. Generate viable solutions, solve complex R&D challenges, empower your innovation with AI.
Patsnap Eureka Materials
Designed for material experts only. Revolutionize your material R&D, from search, analyze, to developing new materials.
Feature
TechResearch
Generate reliable direction feasibility study reports for your R&D in just a few steps.
TechSeek
Discover and master advanced knowledge NOW. Basics, ideas, possibilities, all at once.
TechMind
As an expert in R&D Theories, TechMind can generates customized viable solutions instantly.
TechRisk
Analyze your overall solution with one click, know your potential R&D risks in advance.
TechMonitor
Get weekly tech updates, stay abreast of the latest tech innovations and key insights.
Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
693results about How to "Warpage suppression" patented technology
Efficacy Topic
Property
Owner
Technical Advancement
Application Domain
Technology Topic
Technology Field Word
Patent Country/Region
Patent Type
Patent Status
Application Year
Inventor
Method for manufacturing semiconductor device
InactiveUS20060240574A1Warpage suppressionPolycrystalline material growthSemiconductor/solid-state device manufacturingDevice materialManufactured apparatus
A semiconductor manufacturing apparatus A semiconductor manufacturing apparatus comprises a hot plate which heats a sapphire substrate; a support table having a support plate disposed with being spaced away from the hot plate by a predetermined interval, and support portions which respectively support the sapphire substrate with being spaced by a predetermined interval between the hot plate and the support plate and support the sapphire substrate in such a manner that back surfaces of the hot plate and the sapphire substrate are opposite to each other; an elevating device which moves the support table up and down; and a shielding cover which externally blocks off spacing defined between the hot plate and the sapphire substrate and spacing defined between the sapphire substrate and the support plate.
Owner:LAPIS SEMICON CO LTD
Substrate processing apparatus
ActiveUS20060048710A1Avoid pollutionUniform temperature distributionSemiconductor/solid-state device manufacturingChemical vapor deposition coatingEngineeringDeposition process
The substrate processing apparatus according to the present invention is aimed to stably and efficiently perform a deposition process on a substrate W. The substrate processing apparatus supports the substrate W in a position facing a heater portion and thus rotates a holding member holding the substrate W. Furthermore, the heating portion houses a SiC heater and a heat reflecting member in an internal portion of a quartz bell jar made of transparent quartz, and depressurizes an internal space of a processing vessel and an internal space of the quartz bell jar at the same time; thereby allowing the thickness of the quartz bell jar to be thinner, and thus improving thermal conductivity of heat from the SiC heater and preventing contamination by the SiC heater.
Owner:TOKYO ELECTRON LTD
Semiconductor device and method for manufacturing the same
ActiveUS20060063312A1Excellent manufacturing stabilityWarpage suppressionSemiconductor/solid-state device detailsSolid-state devicesDevice materialSilicon
The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.
Owner:RENESAS ELECTRONICS CORP
Multilevel semiconductor module and method for fabricating the same
InactiveUS20060231939A1InhibitionReduce thicknessSemiconductor/solid-state device detailsSolid-state devicesElectrical conductorSemiconductor chip
A semiconductor module is formed by alternately stacking resin boards and sheet members. Each of the resin boards includes first buried conductors. A semiconductor chip is mounted on the upper face of each of the resin boards. Each of the sheet members having an opening for accommodating the semiconductor chip and including second buried conductors electrically connected to the first buried conductors. A first resin board located at the bottom is thicker than second resin boards. Each of the sheet members includes an adhesive member covering the upper and side faces of the semiconductor chip.
Owner:PANASONIC CORP
Piezoelectric actuator and micro-electromechanical device
InactiveUS20060055287A1Warpage suppressionImprove accuracyNanotechPiezoelectric/electrostrictive device manufacture/assemblyPiezoelectric actuatorsEngineering
A piezoelectric actuator includes a first beam including a first bottom electrode, a first piezoelectric film on the first bottom electrode, and a first top electrode on the first piezoelectric film, a fixed end assigned at an end of the first beam and fixed on a substrate, a connecting end assigned at another end of the first beam and suspended over a free space; and a second beam including a second piezoelectric film connected to the first piezoelectric film at the connecting end, a second bottom electrode under the second piezoelectric film, and a second top electrode on the second piezoelectric film, a working end assigned at an end of the second beam opposite to another end to which the connecting end is assigned and suspended over the free space; wherein a distance between centers of the fixed end and the working end is shorter than a distance from the working end to the connecting end.
Owner:KK TOSHIBA
Electrode, susceptor, plasma processing apparatus and method of making the electrode and the susceptor
InactiveUS7337745B1High strengthWarpage suppressionSemiconductor/solid-state device manufacturingChemical vapor deposition coatingSusceptorThermal expansion
A susceptor 24 includes a heater 38 disposed in a planar state, upper and lower ceramic-metal composites 40A and 40B disposed so as to sandwich the heater 38 from above and from below, and a ceramic electrostatic chuck 28 for attracting and holding an object to be treated, W. The electrostatic chuck is joined to an upper surface of the upper ceramic-metal composite 40A. The electrostatic chuck 28 has nearly the same coefficient of linear thermal expansion as that of the upper ceramic-metal composite 40A. Thus, peeling or cracking of the electrostatic chuck 28 due to the difference in thermal expansion and contraction between the electrostatic chuck 28 and the upper ceramic-metal composite 40A can be prevented.
Owner:TOKYO ELECTRON LTD
Method of manufacturing wiring board
ActiveUS20070044303A1Warpage suppressionThinner chip-built-in wiring boardSemiconductor/solid-state device detailsSolid-state devicesSemiconductor chipEngineering
A method of manufacturing a wiring board including an insulating layer where a semiconductor chip is embedded includes: forming, on a supporting board, the insulating layer where the semiconductor chip is embedded and a wiring connected to the semiconductor chip; removing the supporting board by etching; and simultaneously forming first and second reinforcing layers so as to sandwich the insulating layer after removing the supporting board.
Owner:SHINKO ELECTRIC IND CO LTD
Semiconductor device including wiring substrate having element mounting surface coated by resin layer
InactiveUS20080251913A1Thin structureSuppression of decline in manufacturing yieldSemiconductor/solid-state device detailsSolid-state devicesEngineeringSemiconductor device
In one embodiment of the present invention, there is provided a semiconductor device including a first semiconductor element mounted, through flip-chip bonding, on the element mounting surface of a first wiring substrate, and a resin layer that coats substantially the entire element mounting surface of the first wiring substrate. The first semiconductor element has two opposite surfaces. One surface faces the element mounting surface of the first wiring substrate, and the other surface is not coated by the resin layer.
Owner:NEC ELECTRONICS CORP
Nitride semiconductor substrate and method for manufacturing the same, and nitride semiconductor device using nitride semiconductor substrate
InactiveUS6861729B2Easy to controlReduce crystallinityPolycrystalline material growthLaser detailsNitride semiconductorsSemiconductor device
A nitride semiconductor substrate including (a) a supporting substrate, (b) a first nitride semiconductor layer having a periodical T-shaped cross-section, having grown from periodically arranged stripe-like, grid-like or island-like portions on the supporting substrate, and (c) a second nitride semiconductor substrate covering said supporting substrate, having grown from the top and side surfaces of said first nitride semiconductor layer, wherein a cavity is formed under the second nitride semiconductor layer.A protective layer having a periodically arranged stripe-like, grid-like or island-like apertures is formed on the supporting substrate. The first nitride semiconductor layer is laterally grown from the exposed portion of the substrate. The growth is stopped before the first nitride semiconductor layer covers the supporting substrate. Thus, the first nitride semiconductor layer has a periodical T-shaped cross-section. Then, the protective layer is removed and the second nitride semiconductor layer is grown from the top and side surface of the first nitride semiconductor layer to cover the substrate.
Owner:NICHIA CORP
Collective printed circuit board
ActiveUS20120081864A1High yieldNumberSemiconductor/solid-state device detailsSolid-state devicesPrinted circuit boardSemiconductor components
There is provided a collective printed circuit board including a plurality of printed circuit boards each having a mounting unit on which a semiconductor element is mounted at an upper-surface central portion, and a frame having a plurality of through holes having sizes to surround the mounting portion. Upper-surface peripheral edge portions of the printed circuit boards and a through-hole peripheral portion of the frame are bonded to each other such that the mounting units are exposed from the through holes.
Owner:KYOCERA CORP
Electronic component mounting base board having heat slug with slits and projections
InactiveUS6232558B1Avoid it happening againAvoid warpingPrinted circuit assemblingSemiconductor/solid-state device detailsHeat sinkElectrical conductor
An electronic component mounting base board has an insulating substrate provided with a conductor circuit and a mount portion for an electronic component, and a heat slug adhered to the insulating substrate, wherein the heat slug is comprised of a flat main body and a projection portion extending vertically from a side face of the main body, and provided with a slit deforming portion absorbing deformation of the insulating substrate.
Owner:IBIDEN CO LTD +1
Multilayered wiring substrate and method of manufacturing the same
InactiveUS20070057363A1Suppress generationReduce thicknessSemiconductor/solid-state device detailsPrinted circuit aspectsEngineering
Owner:SHINKO ELECTRIC IND CO LTD
Warp-suppressed semiconductor device
InactiveUS20100230797A1Warpage suppressionLow viscositySemiconductor/solid-state device detailsSolid-state devicesAdhesiveSemiconductor chip
A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region.
Owner:RENESAS ELECTRONICS CORP
Interconnecting substrate and semiconductor device
ActiveUS20060192287A1Improve transferabilityHigh reliabilitySemiconductor/solid-state device detailsPrinted circuit aspectsEngineeringElectrical conductor
An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor within the via hole and is formed on a top surface of the base insulating film, wherein the interconnecting substrate comprises a first interconnection pattern formed of the first interconnection which comprises at least a linear pattern which extends along a second direction orthogonal to a first direction, and a warpage-controlling pattern which is provided in the sunken section in the bottom surface of the base insulating film and is formed in such a manner as to suppress a warpage of the interconnecting substrate toward a bottom side on both sides of the first direction.
Owner:RENESAS ELECTRONICS CORP
Self-rolling laminated sheet and self-rolling pressure-sensitive adhesive sheet
InactiveUS20080131634A1Reduce pollutionEasy to peelWrappers shrinkageShrinkage connectionsEngineeringUltimate tensile strength
The present invention relates to a self-rolling pressure-sensitive adhesive sheet, comprising a shrinkable film layer which is contractible in at least one axial direction; a restriction layer restricting a contraction of the shrinkable film layer, the restriction layer being disposed on a side of the shrinkable film layer; and a pressure-sensitive adhesive layer disposed on the side of the restriction layer which is opposite to the side on which the shrinkable film layer is disposed, the self-rolling pressure-sensitive adhesive sheet being a releasable pressure-sensitive adhesive sheet, in which the pressure-sensitive adhesive layer or the pressure-sensitive adhesive layer after an adhesiveness decreasing treatment has a pressure-sensitive adhesive power (180° peeling, against a silicon mirror wafer, tensile speed: 300 mm / min) of 6.5 N / 10 mm or less, and in which the self-rolling pressure-sensitive adhesive sheet rolls up in one direction from an end to form one tubular roll or rolls up from two opposing ends toward a center of the two opposing ends to form two tubular rolls, when the self-rolling pressure-sensitive sheet is stimulated to induce the contraction of the shrinkable film layer. The self-rolling pressure-sensitive adhesive sheet can be very easily peeled off from an adherend without causing a damage or a contamination on the adherend, even when it is adhered to an adherend of a relatively low strength.
Owner:NITTO DENKO CORP
Warp-suppressed semiconductor device
InactiveUS7728440B2Suppression of deformationWarpage suppressionSemiconductor/solid-state device detailsSolid-state devicesAdhesiveSemiconductor chip
A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region.
Owner:RENESAS ELECTRONICS CORP
Sheet for Forming a Protective Film for Chips
InactiveUS20090053518A1Suppress warpageHigh accuracySemiconductor/solid-state device detailsDuplicating/marking methodsEngineeringPolymer
Described is a sheet for forming a protective film, which can be used suitably in a process where marking is made on the protective film formed on work such as a wafer and the like. The sheet includes a release sheet and a protective film forming layer provided on the release surface of the release sheet, wherein the protective film forming layer includes 100 parts by weight of an epoxy resin, 50 to 200 parts by weight of a binder polymer, and 100 to 2,000 parts by weight of fillers, 30% by weight or more of total 100% by weight of the said epoxy resin being selected from epoxy resins represented by the following formulae (I) and (II);wherein, X's are —O—, —OCH(CH3)O— and the like; R's are a polyether skeleton and the like; and n's are in the range of 1 to 10.
Owner:LINTEC CORP
Wiring board manufacturing method
ActiveUS20060207088A1Firmly connectedImprove reliabilityPrinted circuit assemblingSemiconductor/solid-state device detailsSemiconductor chipPower strip
A method of manufacturing a wiring board includes: forming a first insulating layer on a supporting board; mounting at least one reinforcing member on the first insulating layer; mounting at least one semiconductor chip on the first insulating layer; forming a second insulating layer on the reinforcing member and the semiconductor chip; and forming a wiring on the second insulating layer, the wiring being connected to the semiconductor chip.
Owner:SHINKO ELECTRIC IND CO LTD
Marking method and sheet for both protective film forming and dicing
ActiveUS7935574B2Warpage suppressionImprove accuracySemiconductor/solid-state device detailsSolid-state devicesTectorial membraneEngineering
The invention provides a marking method in which marking is performed on a protective film formed on a work with a high accuracy while suppressing a warpage and, also, a sheet for both protective film forming and dicing which is advantageously used in the method. The marking method comprises irradiating laser light to a laminated structure comprising a support film tensely supported by a ring frame, a protective film releasably laminated on the support film and a work fixed to the protective film, wherein the protective film is irradiated laser light from a side of the support film, to thereby mark the protective film.
Owner:LINTEC CORP
Multilayered wiring substrate including wiring layers and insulating layers and method of manufacturing the same
InactiveUS7696613B2Suppress generationReduce thicknessSemiconductor/solid-state device detailsPrinted circuit aspectsEngineeringElectrical and Electronics engineering
A multilayered wiring substrate is constructed by stacking wiring layers 105, 108, 110, 112 and insulating layers 104, 106, 107, 109 in predetermined number, with at least one of the wiring layers being formed as a reinforcing wiring layer 103 whose thickness is 35 to 150 μm arranged in one layer or plural layers. Also, the thickness of the reinforcing wiring layer is larger than that of the other wiring layers.
Owner:SHINKO ELECTRIC IND CO LTD
Probe card
ActiveUS20100164518A1Warpage suppressionCorrection of flatnessElectrical measurement instrument detailsIndividual semiconductor device testingProbe cardTransformer
A probe card is provided that is capable of accurately ensuring the flatness and the parallelism with respect to a predetermined reference surface. A point (Q) of application of force applied from a leaf spring (17) that presses a portion near an edge portion of a surface of a probe head (15) from which a plurality of probes projects over an entire circumference in a direction of a substrate to the probe head (15) is positioned inside of an outer edge of the probe head (15), and a point (P) of application of force applied from the retainer (16) that presses a portion near an edge portion of a space transformer (14) over an entire circumference in the direction of the substrate to the space transformer (14) is positioned inside of an outer edge of the space transformer (14).
Owner:NHK SPRING CO LTD
Sample handling plate
InactiveUS7410617B2Avoid warpingAccurate measurementMaterial analysis by observing effect on chemical indicatorChemical analysis using titrationEngineeringSample processing
A sample handling plate 1 has wells 4 on the side of the surface 1a thereof, and lightening portions 6 on the side of the reverse 1b thereof, each of the wells 4 substantially having the same shape and volume as those of each of the lightening portions 6 so that the amount of shrinkage on the side of the surface 1a is equal to that on the side of the reverse 1b during cooling after the injection molding.
Owner:ENPLAS CORP
Coating composition, hard coat film, and optical disk
ActiveUS20050147809A1Maintaining surface hardnessSufficient surface hardnessPhotomechanical apparatusRecord information storageSimple Organic CompoundsOligomer
One side of a substrate film 11 is coated with a coating composition containing (A) a reactive particle produced by chemically bonding an organic compound having at least one polymerizable unsaturated group in its molecule to an inorganic oxide particle, (B) a monomer or oligomer of an organic compound having at least two polymerizable unsaturated groups in its molecule, (C) an organic compound with a weight average molecular weight of at least 1500 and having at least one polymerizable unsaturated group in its molecule, and, if desired, (D) a siloxane compound having a dimethylsiloxane skeleton, and the coating composition is cured by irradiation with ionizing radiation to form a hard coat layer 12 with a thickness of 2 to 20 μm. This provides a hard coat film having adequate surface hardness and suppressed warpage.
Owner:LINTEC CORP
Heat treatment device
ActiveUS20080135207A1Warpage suppressionCool evenlySemiconductor/solid-state device manufacturingHot plates heating arrangementsEngineeringSemiconductor
In a heat treatment device including a heating chamber having a heating plate heating a semiconductor wafer, a cooling plate cooling the wafer heated by the heating chamber, and a transporting device transporting the wafer into and from the heating chamber, the cooling plate is provided with a coolant passage, a plurality of projections carrying the wafer with a space between the wafer and the surface of the cooling plate, and suction holes neighboring to the respective projections and connected to a suction device.
Owner:TOKYO ELECTRON LTD
Polarizing film and image display
InactiveUS7110177B2Little strengthImprove display characteristicsOptical articlesPolarising elementsSheet filmPolyvinyl alcohol
The present invention provides a polarizing film or a polarizer that has an elastic modulus of at most about 3500 N / mm2 and suppresses occurrence of warping, the polarizing film is obtained by adsorbing a dichroic material in a polyvinyl alcohol-based film 20 μm in thickness and stretching the tilin. The polarizing film has a transmittance of at least 43% and a polarization degree of at least 98%. A transparent protective layer is laminated on at least one surface of the polarizing film to form a polarizing plate.
Owner:NITTO DENKO CORP
Wiring board and method for manufacturing the same
InactiveUS20060272854A1Warpage suppressionSmall thicknessPrinted circuit assemblingPrinted electric component incorporationSemiconductor chipEngineering
A wiring board includes: a semiconductor chip; an insulating layer in which the semiconductor chip is embedded; a wiring connected to the semiconductor chip; and reinforcing layers for reinforcing the insulating layer, the reinforcing layers respectively formed on a front face side of the insulating layer and a rear face side of the insulating layer.
Owner:SHINKO ELECTRIC IND CO LTD
Liquid-crystalline polyester resin composition and connector using the same
ActiveCN101875762AAdequate solder resistanceWarpage suppressionLiquid crystal compositionsCouplings bases/casesLiquid crystallineVolume average
Owner:SUMITOMO CHEM CO LTD
Secondary lining integral formworking construction method for tunnel with super-large cross section
The invention belongs to the technical field of construction engineering and provides a secondary lining integral formworking construction method for a tunnel with a super-large cross section. The method includes a main line which includes bogie designing and manufacturing, track laying, assembling and adjusting, bogie front and back position adjusting and locking, plug formwork erecting, formwork center line elevation adjusting, concrete pouring, curing, formwork removing and next formwork constructing; in the main line, surveying and setting out, waterproof board laying, rebar manufacturing and mounting, rebar checking and accepting and plug formwork erecting are performed; in the main line, concrete raw material selecting, concrete mix proportion optimizing, mix proportion onsite checking, concrete agitating and concrete pouring are performed; in the main line, formwork bogie locking device checking and concrete pouring are performed; in the main line, curing and roughened joint treating are performed. By integration of specially-made assembly frame and large formwork, the integral formwork bogie is formed, and one-time pouring forming of secondary lining concrete is guaranteed.
Owner:CHINA CONSTR EIGHTH ENG DIV
Pressure-sensitive adhesive type polarizer with retardation layer, process for producing the same, optical film, and image display
ActiveCN101080657AEasy to identifySuppresses changes in optical propertiesPolarising elementsAcid polymer adhesivesPolyvinyl alcoholPotassium
Owner:NITTO DENKO CORP
BiFeO3 target and film production method
InactiveCN101429642ALow costFine and uniform powderVacuum evaporation coatingSputtering coatingDrain currentOxide
The invention provides a preparation method for a BiFeO3 target material. The preparation method for the BiFeO3 target material comprises the following steps: carrying out grinding, ball milling, preburning, re-ball milling, granulation and screening for the mixture of bismuth oxide Bi2O3 and ferric oxide Fe2O3 to obtain the target material; and then carrying out batch dropping, baking, heating with pressure, heat insulation and cooling for the target material. The invention also provides a method for preparing a film through the BiFeO3 target material. The method comprises the following steps: selecting a Pt / TiO2 / SiO2 / p-Si substrate; preparing the BiFeO3 film through a radio frequency magnetron sputtering method; and finally carrying out the annealing treatment of the prepared BiFeO3 film. The target material has the advantages of no impurity phase, levelness and compactness. The film prepared through the target material has a compact and even surface, better crystallinity, no impurity phase, low drain current, saturated electric hysteresis loop, good fatigue characteristic, and good repeatability.
Owner:HUAZHONG UNIV OF SCI & TECH
Who we serve
- R&D Engineer
- R&D Manager
- IP Professional
Why Patsnap Eureka
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com